CN113034344B - Two-dimensional FFT method with low memory resource overhead - Google Patents
Two-dimensional FFT method with low memory resource overhead Download PDFInfo
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- CN113034344B CN113034344B CN202110453396.5A CN202110453396A CN113034344B CN 113034344 B CN113034344 B CN 113034344B CN 202110453396 A CN202110453396 A CN 202110453396A CN 113034344 B CN113034344 B CN 113034344B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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Abstract
The invention discloses a two-dimensional FFT structure with low memory resource expense, which is applied to the field of signal processing and aims at the problem of higher consumption of computing resources and memory resources in the existing two-dimensional FFT technology; the invention introduces data splicing to optimize the storage cost on the basis of the traditional two-dimensional FFT structure; when the image data is input, the odd-even rows are spliced by using a shift register; carrying out one-dimensional FFT on each line of the spliced image, and caching the result into an internal storage resource; when the line transformation is finished, generating a data reading address index according to the columns, and restoring an original one-dimensional FFT transformation result when the data is not spliced; carrying out one-dimensional FFT on each column of the restored image so as to obtain a two-dimensional FFT result of the original image; the invention combines data splicing, directly halving the data volume in the calculation process, and effectively reducing the consumption of storage resources.
Description
Technical Field
The invention belongs to the field of signal processing, and particularly relates to a low-storage-overhead two-dimensional FFT (Fast Fourier Transform, FFT) technology.
Background
The fast fourier transform (Fast Fourier Transform, FFT) technique is an efficient fourier transform method, which reduces the computation time by decomposing the complex computation steps in the discrete fourier transform. With the development of image sensors, visual images have become important as a two-dimensional discrete signal for recording and processing.
The two-dimensional FFT technique is capable of converting an image from the spatial domain to the frequency domain, enabling researchers to analyze and process image signals from different angles. When the image data is input in a data stream mode according to a line, the traditional two-dimensional FFT method puts the image data into a real part, and the imaginary part is set to 0, and the image data is sent into a two-dimensional conversion module formed by sequentially cascading two one-dimensional FFT modules. Although the method is simple and easy to implement, more computing resources and storage resources are consumed.
Disclosure of Invention
In order to solve the technical problems, the invention provides a two-dimensional FFT method with low storage resource expense, which is realized in an FPGA by utilizing the advantage of low power consumption of the FPGA platform based on the data splicing method.
The invention adopts the technical scheme that: a low memory resource overhead two-dimensional FFT method comprising: the device comprises a shift register, a first one-dimensional FFT module, a memory, a data reduction module and a second one-dimensional FFT module;
the shift register is used for storing odd-numbered line data of an image, splicing even-numbered line data of the image and the stored odd-numbered line data into a complex sequence, the first one-dimensional FFT module performs one-dimensional FFT conversion operation on the complex sequence in the line direction, the first one-dimensional FFT module stores the conversion result into the memory, the data reduction module reduces the conversion result stored in the memory into one-dimensional FFT conversion results of all lines of the image input before splicing, and the second one-dimensional FFT module performs one-dimensional FFT conversion operation on the one-dimensional FFT conversion results of all lines of the image input before splicing in the column direction, so that two-bit FFT calculation results of the image input are obtained.
When odd-numbered line data of an image is input, a write enable signal of a shift register is generated, and the odd-numbered line data is sequentially stored in the shift register.
When even line data of an image is input, a reading enabling signal of a shift register is generated, cached odd line data is read out and spliced with the input even line data to obtain a spliced complex sequence.
The first one-dimensional FFT module stores the transformation result into a memory, and the adopted memory address format is as follows: according to the conversion result output by the first one-dimensional FFT module, sequentially generating storage addresses according to the corresponding mode of splicing the row address and the column address, wherein the generated storage addresses are expressed as follows: { row address, column address }.
The memory is a dual-port RAM, and the dual ports of the RAM are respectively marked as an A port and a B port.
The data reduction module specifically comprises: data data_a is read from an a port of the dual-port RAM by using a clock rising edge and addr_a { row address, u }, data data_b is read from a B port of the dual-port RAM by using a clock falling edge and addr_b { row address, N-1-u }, and thus a one-dimensional FFT conversion result of each row of the image input before splicing is obtained, u=0.
The invention has the beneficial effects that: compared with the traditional two-dimensional FFT method, the data quantity is directly halved through data splicing, namely, the calculation consumption and the storage consumption of the data are reduced, so that the calculation power consumption and the memory resource consumed in algorithm realization can be effectively reduced.
Drawings
FIG. 1 is an overall flow chart of the method of the present invention.
FIG. 2 is a timing diagram of the read and data recovery of the dual port RAM of the present invention.
Detailed Description
The present invention will be further explained below with reference to the drawings in order to facilitate understanding of technical contents of the present invention to those skilled in the art.
The present example takes as input an image with a resolution of 64 x 64 pixels. The invention relates to a method for realizing a low-memory-overhead two-dimensional FFT technology in a field programmable gate array (Field Programmable Gate Array, FPGA), wherein a two-dimensional FFT structure realization flow chart is shown in figure 1, and the method comprises the following steps:
step one: the images are read and input in line order. A shift register with a depth of 64 is defined, when the odd-numbered line data x o [n]When n is more than or equal to 1 and less than or equal to 64, the shift register is enabled to write, and data is shifted and registered.
Step two: when the image is even-numbered line data x e [n]When inputting, the shift register is enabled to read, the buffered odd line data is read in sequence, and the buffered odd line data and even line data are spliced into a complex sequencez[n]。
In the splicing method, the composition mode of the complex sequence z [ n ] is as follows:
z[n]＝x o [n]+jx e [n]
where j is the imaginary symbol.
Step three: the complex sequence Z [ n ] is sent to a first one-dimensional FFT module to obtain complex conversion Z [ u ], wherein u is more than or equal to 1 and less than or equal to 64, and when the result of the first one-dimensional FFT module starts to be output, storage addresses are sequentially generated according to the mode of splicing row addresses and column addresses corresponding to data, and the generated storage addresses can be expressed as follows: { row address, column address }; the number of data lines after splicing is halved, so the result is stored in a dual port RAM with a depth of 64×32=2048.
The Fourier transform mode from Z [ n ] to Z [ u ] is as follows:
where N is the number of data for one FFT transform, where n=64. e is a natural index.
Step four: generating data index addresses by columns; specifically, the method is as follows in fig. 2: the row conversion Z data data_a is read from the a port of the dual port RAM by the rising edge of the clock clk_p and the address addr_a (where addr_a is formed by splicing { row address, u }, u=0..the., 63), and the data data_b is read from the B port of the dual port RAM by the falling edge of the clock (inverted clock clk_n) and the corresponding address addr_b in the row (where addr_b is formed by splicing { row address, N-1-u }, n=64), so that the data can be restored to the conversion result data_recovery of X before parity splicing.
The data reduction method is exemplified by the 1 st row data and the 2 nd row data:
for x 1 [n]And x 2 [n]Complex sequence z of components 1 [n]The result of the Fourier transform is Z 1 [u]. Can be represented by Z 1 [u]Reduction of x 1 [n]And x 2 [n]Fourier transform result X of (2) 1 [u]And X 2 [u]：
Step five: and sending the data of the column index to a second one-dimensional FFT module, and finally obtaining the calculation result of the two-dimensional FFT of the original image.
Compared with the traditional two-dimensional FFT calculation method, the method reduces the required storage resources by half in the data caching stage after the line transformation, and the working time is not increased compared with the original method due to the adoption of double data reading rate. Finally, a two-dimensional FFT structure with low memory resource overhead is realized in the FPGA.
Those of ordinary skill in the art will recognize that the embodiments described herein are for the purpose of aiding the reader in understanding the principles of the present invention and should be understood that the scope of the invention is not limited to such specific statements and embodiments. Various modifications and variations of the present invention will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.
Claims (6)
1. A two-dimensional FFT method with low memory resource overhead, comprising: the device comprises a shift register, a first one-dimensional FFT module, a memory, a data reduction module and a second one-dimensional FFT module;
the method comprises the steps of reading an image and inputting the image according to a row sequence, wherein a shift register is used for storing odd-numbered row data of the image, splicing even-numbered row data of the image and the stored odd-numbered row data into a complex sequence, sending the complex sequence Z [ n ] to a first one-dimensional FFT module to obtain complex conversion Z [ u ] which is more than or equal to 1 and less than or equal to 64, carrying out one-dimensional FFT conversion operation on the complex sequence in the row direction by the first one-dimensional FFT module, storing a conversion result in a memory by the first one-dimensional FFT module, restoring the conversion result stored in the memory into one-dimensional FFT conversion results of each row of the image input before splicing by the data restoring module, and carrying out one-dimensional FFT conversion operation on the one-dimensional FFT conversion results of each row of the image input before splicing by the second one-dimensional FFT module in the row direction, so as to obtain a two-bit FFT calculation result of the image input.
2. The two-dimensional FFT method with low memory resource overhead according to claim 1, wherein when the odd-numbered line data of the image is inputted, a write enable signal of the shift register is generated, and the odd-numbered line data is sequentially stored in the shift register.
3. The method of claim 2, wherein when even line data of an image is input, a read enable signal of a shift register is generated, the buffered odd line data is read out and spliced with the input even line data to obtain a spliced complex sequence.
4. The method of claim 3, wherein the first one-dimensional FFT module stores the transformation result in a memory address format: according to the conversion result output by the first one-dimensional FFT module, sequentially generating storage addresses according to the corresponding mode of splicing the row address and the column address, wherein the generated storage addresses are expressed as follows: { row address, column address }.
5. The method of claim 4, wherein the memory is a dual port RAM, and the dual ports of the RAM are designated as ports a and B, respectively.
6. The two-dimensional FFT method of claim 4 wherein the data recovery module is specifically: data data_a is read from an a port of the dual-port RAM by using a clock rising edge and addr_a { row address, u }, data data_b is read from a B port of the dual-port RAM by using a clock falling edge and addr_b { row address, N-1-u }, and thus a one-dimensional FFT conversion result of each row of the image input before splicing is obtained, u=0.
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| CN106021182B (en) * | 2016-05-17 | 2018-11-30 | 华中科技大学 | A kind of row transposition architecture design method based on Two-dimensional FFT processor |
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