CN113034344A

CN113034344A - Two-dimensional FFT structure with low storage resource overhead

Info

Publication number: CN113034344A
Application number: CN202110453396.5A
Authority: CN
Inventors: 卢有亮; 罗壹航; 陈勇; 唐豪; 郑伟生; 罗建平
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2021-04-26
Filing date: 2021-04-26
Publication date: 2021-06-25
Anticipated expiration: 2041-04-26
Also published as: CN113034344B

Abstract

The invention discloses a two-dimensional FFT structure with low storage resource overhead, which is applied to the field of signal processing and aims at solving the problem that the existing two-dimensional FFT technology has higher consumption of computing resources and storage resources; on the basis of the traditional two-dimensional FFT structure, data splicing is introduced to optimize storage overhead; when image data is input, splicing odd and even lines by using a shift register; performing one-dimensional FFT on each row of the spliced image, and caching the result into an internal storage resource; when the row transformation is finished, generating data reading address indexes according to columns, and restoring the original one-dimensional FFT transformation result when the data are not spliced; performing one-dimensional FFT on each row of the restored image to obtain a two-dimensional FFT result of the original image; the invention combines data splicing to directly reduce the data volume in the calculation process by half, thereby effectively reducing the consumption of storage resources.

Description

Two-dimensional FFT structure with low storage resource overhead

Technical Field

The invention belongs to the field of signal processing, and particularly relates to a Fast Fourier Transform (FFT) technology with low storage overhead.

Background

Fast Fourier Transform (FFT) technology is a highly efficient Fourier Transform method, which greatly reduces the computation time by decomposing the complex computation steps in discrete Fourier Transform. With the development of image sensors, the recording and processing of visual images as a two-dimensional discrete signal becomes very important.

The two-dimensional FFT technique can convert the image from the spatial domain to the frequency domain, so that the researcher can analyze and process the image signal from different angles. When image data is input in rows in a data stream mode, the image data is put into a real part and an imaginary part of the image data is set to be 0 by a traditional two-dimensional FFT method, and the image data is sent into a two-dimensional transformation module formed by sequentially cascading two one-dimensional FFT modules. Although this method is simple and easy to implement, it usually consumes more computing resources and storage resources.

Disclosure of Invention

In order to solve the technical problem, the invention provides a two-dimensional FFT structure with low storage resource overhead, which is realized in an FPGA (field programmable gate array) by utilizing the advantage of low power consumption of an FPGA platform based on a data splicing method.

The technical scheme adopted by the invention is as follows: a two-dimensional FFT structure with low memory resource overhead, comprising: the device comprises a shift register, a first one-dimensional FFT module, a memory, a data restoration module and a second one-dimensional FFT module;

the shift register is used for storing odd line data of an image and splicing the even line data and the stored odd line data of the image into a complex sequence, the first one-dimensional FFT module carries out one-dimensional FFT conversion operation in the line direction on the complex sequence, the first one-dimensional FFT module stores the conversion result into the memory, the data reduction module reduces the conversion result stored by the memory into one-dimensional FFT conversion results of each line input by the image before splicing, and the second one-dimensional FFT module carries out one-dimensional FFT conversion operation in the column direction on the one-dimensional FFT conversion results of each line input by the image before splicing, so that a two-bit FFT calculation result of the image input is obtained.

When odd line data of an image is input, a write enable signal of the shift register is generated, and the data of the odd line is sequentially stored in the shift register.

When even line data of an image is input, a read enable signal of a shift register is generated, the cached odd line data is read out and is spliced with the input even line data to obtain a spliced complex sequence.

The first one-dimensional FFT module stores the conversion result into a memory, and the adopted memory address format is as follows: according to the transformation result output by the first one-dimensional FFT module, sequentially generating storage addresses in a mode of splicing corresponding row addresses and column addresses, wherein the generated storage addresses are expressed as follows: { row address, column address }.

The memory is a dual-port RAM, and the dual ports of the RAM are respectively marked as an A port and a B port.

The data restoration module specifically comprises: the data _ A is read from the port A of the dual-port RAM by using a clock rising edge and addr _ A { row address, u }, and the data _ B is read from the port B of the dual-port RAM by using a clock falling edge and addr _ B { row address, N-1-u }, so that a one-dimensional FFT result of each row of the image input before splicing is obtained, wherein u is 0.

The invention has the beneficial effects that: compared with the traditional two-dimensional FFT method, the data volume is directly halved through data splicing, namely the calculation consumption and the storage consumption of the data are reduced, so that the calculation power consumption and the memory resource consumed in the algorithm implementation can be effectively reduced.

Drawings

FIG. 1 is an overall flow diagram of the method of the present invention.

FIG. 2 is a timing diagram of reading and data recovery of the dual port RAM of the present invention.

Detailed Description

In order to facilitate the understanding of the technical contents of the present invention by those skilled in the art, the present invention will be further explained with reference to the accompanying drawings.

The present example takes as input an image with a resolution of 64 x 64 pixels. The invention relates to a method for realizing a two-dimensional FFT technology with low storage cost in a Field Programmable Gate Array (FPGA), the two-dimensional FFT structure realization flow chart is shown in figure 1, and the method comprises the following steps:

the method comprises the following steps: the image is read and input in line order. Defining a shift register with a depth of 64, when the odd row of data x_o[n]When n is more than or equal to 1 and less than or equal to 64, the shift register is enabled to write and register data.

Step two: when the image is in even line data x_e[n]When inputting, the shift register is enabled to read the odd line data of the buffer memory in sequence, and the odd line data and the even line are spliced into a complex sequence z [ n ]]。

In the splicing method, the composition mode of a complex sequence z [ n ] is as follows:

z[n]＝x_o[n]+jx_e[n]

where j is the imaginary sign.

Step three: sending the complex sequence Z [ n ] into a first one-dimensional FFT module to obtain a complex transform Z [ u ], wherein u is more than or equal to 1 and less than or equal to 64, when the result of the first one-dimensional FFT module starts to be output, sequentially generating storage addresses according to a mode of splicing row addresses and column addresses corresponding to data, wherein the generated storage addresses can be expressed as: { row address, column address }; since the number of rows of data after splicing is halved, the result is stored in a dual-port RAM with a depth of 64 × 32 ═ 2048.

The Fourier transform mode from Z [ n ] to Z [ u ] is as follows:

where N is the number of data in one FFT, where N is 64. e is a natural index.

Step four: generating data index addresses by columns; specifically, according to the mode of fig. 2: the data can be restored to the conversion result data _ receiver of X before parity concatenation by reading the row conversion Z data _ a from the a port of the dual port RAM using the rising edge of the clock clk _ p and the address addr _ a (where addr _ a is formed by concatenating { row address, u }, and u is 0.. multidot.63), and reading the data _ B from the B port of the dual port RAM using the falling edge of the clock (inverted clock clk _ N) and the corresponding address addr _ B in the row (where addr _ B is formed by concatenating { row address, N-1-u }, and N is 64).

The data reduction method takes the 1 st row of data and the 2 nd row of data as an example:

for x₁[n]And x₂[n]Composed complex sequence z₁[n]Fourier transform result of Z₁[u]. Can be composed of Z₁[u]Reduction to x₁[n]And x₂[n]Result of Fourier transform of X₁[u]And X₂[u]：

Step five: and sending the data of the row index into a second one-dimensional FFT module to finally obtain a two-dimensional FFT calculation result of the original image.

Compared with the traditional two-dimensional FFT calculation method, the method reduces the required storage resources by half in the data caching stage after line transformation, and the working time is not increased compared with the original method due to the adoption of double data reading rate. And finally, a two-dimensional FFT structure with low storage resource overhead is realized in the FPGA.

It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A two-dimensional FFT structure with low memory resource overhead, comprising: the device comprises a shift register, a first one-dimensional FFT module, a memory, a data restoration module and a second one-dimensional FFT module;

2. The two-dimensional FFT architecture with low memory resource overhead of claim 1, wherein when odd row data of the image is inputted, a write enable signal of the shift register is generated, and the odd row data is sequentially stored in the shift register.

3. The two-dimensional FFT architecture with low storage resource overhead as claimed in claim 2, wherein when the even row data of the image is inputted, a read enable signal of the shift register is generated, and the buffered odd row data is read out and spliced with the inputted even row data to obtain a spliced complex sequence.

4. The two-dimensional FFT architecture with low storage resource overhead of claim 3, wherein the first one-dimensional FFT module stores the transformation result in a memory, and the storage address format adopted by the first one-dimensional FFT module is as follows: according to the transformation result output by the first one-dimensional FFT module, sequentially generating storage addresses in a mode of splicing corresponding row addresses and column addresses, wherein the generated storage addresses are expressed as follows: { row address, column address }.

5. The two-dimensional FFT architecture with low storage resource overhead of claim 4, wherein the memory is a dual port RAM, and the dual ports of the RAM are respectively marked as an A port and a B port.

6. The two-dimensional FFT architecture with low storage resource overhead according to claim 4, wherein the data recovery module is specifically: the data _ A is read from the port A of the dual-port RAM by using a clock rising edge and addr _ A { row address, u }, and the data _ B is read from the port B of the dual-port RAM by using a clock falling edge and addr _ B { row address, N-1-u }, so that a one-dimensional FFT result of each row of the image input before splicing is obtained, wherein u is 0.