CN113034341B

CN113034341B - Data acquisition processing circuit for Cameralink high-speed industrial camera

Info

Publication number: CN113034341B
Application number: CN202110569514.9A
Authority: CN
Inventors: 郑建; 胡美琴; 钟洪萍
Original assignee: Zhejiang Shuangyuan Technology Co ltd
Current assignee: Zhejiang Shuangyuan Technology Co ltd
Priority date: 2021-05-25
Filing date: 2021-05-25
Publication date: 2021-08-03
Anticipated expiration: 2041-05-25
Also published as: CN113034341A

Abstract

The invention discloses a data acquisition processing circuit for a Cameralink high-speed industrial camera, which comprises a Cameralink signal decoding module, an image processing module, a defect positioning and screening module, an image caching read-write module, an auxiliary data processing module, a local area network transceiving module and a parameter command configuration module, wherein the image processing module is used for processing a plurality of images; the Camera link signal decoding module receives and decodes the signal of the camera sensor and then respectively sends the decoded signal to the image processing module and the image cache read-write module; the image processing module generates a standard binary image and sends the standard binary image to the defect positioning and screening module; the defect positioning and screening module is used for positioning and screening defects; the local area network transceiver module is used for actively reading the data of the defect positioning and screening module, the image cache read-write module and the auxiliary data processing module and sending the data to the upper computer; and the parameter command configuration module decodes the network packet command after receiving the network packet command, so that each module can set parameters. The invention can meet the detection precision requirement and the defect detection real-time requirement which are continuously promoted in the field of sheets.

Description

Data acquisition processing circuit for Cameralink high-speed industrial camera

Technical Field

The invention belongs to the field of sheet defect detection, and particularly relates to a data acquisition processing circuit for a Cameralink high-speed industrial camera.

Background

The sheet defect detection system and the sheet defect detection equipment are widely applied to the film industry, the papermaking industry, the non-woven fabric industry and the lithium battery industry.

Common foreign sheet defect detection devices mainly comprise MXopen WIS of Measurex Roibox company, AUTO SPE system of OMRON company and ULMA and ESI 7 of ABB company, and are in blank state in China. The defects of the sheet defect detection system developed abroad generally have the defects of high price, high maintenance cost and the like.

There are some sheet defect detection devices in China, for example, the Chinese patent document with publication number CN103543162A discloses a method and a device for detecting surface defects and thickness of semiconductor sheets, which comprises a tool, a control cabinet and a computer connected in sequence by connecting cables, wherein data collected by a data acquisition card in the tool is transmitted to the computer through RS232 communication, and the surface defects and thickness information of the semiconductor sheets are analyzed by software of the computer. Chinese patent publication No. CN202433316U discloses a synchronous system device applied to the online detection process of surface defects of long plastic sheets, which comprises a frame, a linear array CCD camera, an acquisition module and a central control module, wherein the acquisition module comprises a high-speed acquisition card connected with the linear array CCD camera and interconnected with the central control module.

However, the above devices all adopt a processing mode of "CCD camera + acquisition card + Pc machine". With the increasing real-time data volume of camera images, the serial structure and the working mode of a computer inevitably limit the operation speed, so that the speed bottleneck effect of an acquisition card mode is formed, and the rapidity and the reliability improvement of a detection system are seriously restricted.

Disclosure of Invention

The invention provides a data acquisition processing circuit for a Cameralink high-speed industrial camera, which meets the detection precision requirement and the defect detection real-time requirement which are continuously promoted in the field of sheets and provides an embedded solution which is stackable, low in energy consumption, high in real-time performance and high in stability.

A data acquisition processing circuit for a Cameralink high-speed industrial camera comprises a Cameralink signal decoding module, an image processing module, a defect positioning and screening module, an image cache read-write module, an auxiliary data processing module, a local area network transceiving module and a parameter command configuration module;

the Camera link signal decoding module receives the camera signal for decoding, decodes the camera signal into original image data and then respectively sends the original image data to the image processing module and the image cache read-write module;

the image processing module receives and processes original image data, generates a standard binary image and sends the standard binary image to the defect positioning and screening module;

the defect positioning and screening module receives the standard binary image to position and screen defects, encodes screened defect data, stores the encoded data in a defect FIFO, and waits for the reading of the local area network transceiver module;

the image cache read-write module receives original image data and then divides the original image data into two paths, wherein one path of original image data is used for the local area network transceiver module to read one line of image data from the image cache read-write module according to a line reading image request of a user; the other path of original image data is used for circularly writing the cached image and the local area network transceiving module carries out image reading operation according to the reading request of the user;

the auxiliary data processing module is used for acquiring state data and sending the state data to the local area network transceiving module, wherein the state data at least comprises a vehicle speed signal, an environment temperature and an edge value of a material to be detected;

the local area network transceiving module is used for actively reading data of the defect positioning and screening module, the image cache read-write module and the auxiliary data processing module, sending the data to the upper computer and sending a network packet command of the upper computer to the parameter command configuration module;

and the parameter command configuration module decodes the network packet command after receiving the network packet command, so that each module can set parameters.

The invention thoroughly solves the real-time problem of image data stream processing by realizing one-stop integration of each process of defect detection.

Furthermore, the Cameralink signal decoding module comprises a dynamic phase adjustment module, a camera data serial-parallel conversion byte recovery module, a row data recovery module, and a data inversion and row frequency flash synchronization separation module;

the dynamic phase adjustment module is used for solving the problem of offset between different cameras and between different data in the cameras when receiving data of the camera sensor;

the camera data serial-parallel conversion byte recovery module is used for recovering a high-speed clock and a corresponding data signal output by a camera, and recombining the high-speed clock and the corresponding data signal according to a Cameralink protocol standard to obtain a line effective signal, a data effective signal and a data point signal;

the line data recovery module is used for switching the multichannel read-write RAM through an internal mode according to the configuration of the camera sensor and the number of channels needing to be output subsequently;

the data inversion and line frequency flash synchronous separation module is used for realizing the forward and reverse switching of data, and if the data inversion and line frequency flash synchronous separation module is used in a multi-light stroboscopic occasion, line data obtained by different light fields are automatically switched into respective output channels according to stroboscopic synchronous signals so as to realize the channel separation of the light fields.

Further, the image processing module comprises a standardization processing module, a synchronous parameter generation module, a multi-mode parallel binarization processing module and a mathematical morphology processing module;

the standardized processing module is used for carrying out filtering, brightness analysis and noise analysis on input original image data;

the synchronous parameter generation module is used for automatically generating parameters of corresponding different detection modules according to the position information of the input original image data and providing the parameters to the multi-mode parallel binarization processing module;

the multi-mode parallel binarization processing module receives data generated by the standardization processing module and the synchronous parameter generation module, realizes parallel processing of points, lines and planes, and generates a standard binary image;

the mathematical morphology processing module is used for carrying out mathematical morphology processing on the standard binary image so as to remove isolated miscellaneous points and recover the integral structure of the defect.

Furthermore, the defect positioning and screening module comprises a defect positioning and fusing module, a defect filtering and screening module and a defect cache module to be sent;

the defect positioning fusion module is used for carrying out transverse and longitudinal fusion on the received standard binary image and generating a defect characteristic value at the same time;

the defect filtering and screening module receives the fused defect characteristic values, and filters and screens the defects which are set by the upper computer and do not meet the characteristic value conditions to obtain defect data to be sent;

the defect to-be-sent cache module is used for carrying out 32-bit coding on defect data to be sent, storing the defect data into the defect FIFO memory and waiting for the local area network transceiver module to actively read the coded defect data.

Further, the image cache read-write module comprises a line image read-write cache module, an image write control module, an image read-write DDR drive module and an image cache module to be sent;

the line image reading and writing cache module receives original image data and directly sends a line of image data to the image cache module to be sent when receiving a line image reading request of a user;

the image writing control module receives original image data to carry out 128-bit assembly, and generates a DDR (double data rate) writing address according to a data position, wherein the DDR adopts a cycle writing mode;

the image reading control module is used for starting a process of reading the DDR memory area according to an image acquisition command requested by a user until the reading is finished; the image acquisition command comprises a DDR starting address, an image width, an image height and an image interval;

the DDR drive module is used for coordinating the read-write module request between the image read control module and the image write control module, and ensuring that continuous operation can be realized during each read-write;

the image cache module to be sent is used for storing the acquired image data and line image data into an image reading cache FIFO after 32-bit assembly so as to be actively read by a subsequent local area network transceiver module.

Furthermore, the auxiliary data processing module comprises a vehicle speed processing module, an IO-temperature-serial port processing module, an edge detection module and a state data collection module;

the vehicle speed processing module is used for providing a vehicle speed signal according to the running speed of the detected material and further controlling to generate a camera line scanning synchronous signal; specifically, an externally input one-way or two-way orthogonal coding vehicle speed signal is filtered to obtain a periodic signal, the periodic signal is filtered to obtain a stable input period, the periodic data obtains a real camera line scanning synchronous signal according to a vehicle speed proportional parameter set by a user, and meanwhile, the vehicle speed signal is output to an upper computer through a state data collection module.

The IO-temperature-serial port processing module is used for realizing general input and output, detecting ambient temperature and realizing the function of communication among the upper computer, the external equipment and the camera through a serial port protocol. The universal input signal is used for functions of user button, material fracture detection, peripheral state detection and the like, the state value of the universal input signal is output to the upper computer through the state data collection module, the output function realizes synchronization of scanning signals, alarming, light source brightness control, action control and the like, and the temperature detection is realized by acquiring the temperature value of environments including a light source and the like through the one-line digital temperature sensor and outputting the temperature value to the upper computer through the state data collection module; the serial port module can intercommunicate the character string packet received and transmitted by the upper computer through the network with the command configuration interface of the camera Cameralink signal channel, can intercommunicate the character string packet received and transmitted by the upper computer through the network with the RS232 interface of the external device, and can intercommunicate the command configuration interface of the camera Cameralink signal channel with the RS232 interface of the external device.

The edge detection module is used for realizing the tracking function of the front edge and the rear edge according to the input image original data, and the edge detection result is output and uploaded through the state data collection module;

the state data collection module collects data to be uploaded by the vehicle speed processing module, the IO-temperature-serial port processing module and the edge detection module, and then the data are assembled into network state data to be sent to the local area network receiving and sending module.

Furthermore, the local area network transceiver module comprises a defect location data packaging module, an image data packaging module, a state data packaging module, a packet sending control module, a network MAC layer and an ICMP interpretation module;

the defect positioning data packaging module is used for actively reading data in a defect FIFO of the defect positioning and screening module;

the image data package module is used for actively reading in the image data and the line image data of the image cache read-write module;

the state data package module is used for actively reading in the state data of the auxiliary data processing module;

the packet sending control module is used for carrying out sending switching scheduling on the defect location data packet module, the image data packet module and the state data packet module according to the sending condition of the network MAC layer;

the network MAC layer is used for assembling a UDP layer, an IP layer and the MAC layer on the sent packet data, calculating a CRC value, loading the CRC value to a packet queue to be sent and waiting for sending;

the ICMP interpretation module is used for responding to a network packet command of the upper computer in real time.

Furthermore, the parameter command detection module comprises a command analysis module, a data configuration module and a firmware upgrading module;

the command analysis module is used for receiving a network packet command of the upper computer and decoding parameters to acquire working parameter settings required by the Cameralink signal decoding module, the image processing module, the defect positioning and screening module, the image cache read-write module, the auxiliary data processing module and the like; the data configuration module is used for receiving the parameters of the command interpretation module, storing the parameters into the FLASH parameter area, and actively loading the stored parameters during power-on initialization for initial setting of each module;

the firmware upgrading module is used for receiving upgrading commands and data of the upper computer, checking in a segmented mode in the upgrading process and supporting a failure retransmission mechanism.

Compared with the prior art, the invention has the following beneficial effects:

1. the whole process from camera signal decoding to defect extraction and network full hardware coding and decoding is realized by FPGA hardware logic, and a parallel flow structure is adopted in the FPGA, so that high real-time performance is ensured;

2. the integral one-stop embedded design provides a core guarantee for high-speed, high-precision and large-breadth material defect detection;

3. each data acquisition processing circuit can support 1-2 camera signal inputs, the cost is close to that of a Cameralink acquisition card, and the overall cost performance is very high;

4. the power consumption of each data acquisition and processing circuit is lower than 10 watts and far lower than that of a defect detection system based on a computer, and the data acquisition and processing circuit runs for a long time and contributes to energy conservation and emission reduction of enterprises.

Drawings

Fig. 1 is an overall structural diagram of a data acquisition processing circuit for a Cameralink high-speed industrial camera according to the present invention.

Fig. 2 is a schematic structural diagram of a Cameralink signal decoding module in the embodiment of the present invention.

Fig. 3 is a schematic structural diagram of an image processing module according to an embodiment of the present invention.

Fig. 4 is a structural design view of a defect localization and screening module according to an embodiment of the present invention.

Fig. 5 is a schematic structural diagram of an image cache read-write module in the embodiment of the present invention.

Fig. 6 is a schematic structural diagram of an auxiliary data processing module according to an embodiment of the present invention.

Fig. 7 is a schematic structural diagram of a local area network transceiver module according to an embodiment of the present invention.

Fig. 8 is a schematic structural diagram of a parameter command configuration module according to an embodiment of the present invention.

Detailed Description

The invention will be described in further detail below with reference to the drawings and examples, which are intended to facilitate the understanding of the invention without limiting it in any way.

As shown in fig. 1, a data acquisition processing circuit for a Cameralink high-speed industrial camera includes a Cameralink signal decoding module a, an image processing module B, a defect location screening module C, an image cache read-write module D, an auxiliary data processing module E, a local area network transceiver module F, and a parameter command configuration module G.

The output end of the Cameralink signal decoding module A is respectively connected with the receiving ends of the image processing module B and the image cache reading-writing module D, the output end of the image processing module B is connected with the receiving end of the defect positioning screening module C, the output ends of the defect positioning screening module C, the image cache reading-writing module D and the auxiliary data processing module E are all connected with the receiving end of the local area network receiving-transmitting module F, and the output end of the local area network receiving-transmitting module F is connected with the receiving end of the parameter command configuration module G.

The specific structure of each module is described in further detail below.

As shown in fig. 2, the Cameralink signal decoding module a includes a dynamic phase adjustment module a1, a camera data serial-to-parallel conversion byte recovery module a2, a row data recovery module A3, and a data inversion and row flash synchronization separation module a 4.

The dynamic phase adjustment module a1 is for solving the skew problem between different cameras and data in the cameras of different manufacturers, and can adapt to the camera signal of not higher than 85M master clock frequency in accordance with the CAMERALINK standard.

The camera data serial-to-parallel conversion byte recovery module a2 is used to recover a high-speed clock and a corresponding data signal output by a camera, and reassembles the high-speed clock and the corresponding data signal according to a camera link protocol standard to obtain a row valid signal, a data valid signal and a data point signal, and may output multiple data simultaneously according to a camera configuration condition.

The data recovery module A3 can be parity data of different positions or multi-line data (R, G, B) of color camera according to the camera configuration, and the module switches the multi-channel read-write RAM according to the data module of camera and the number of the channels needed to be output subsequently, so as to realize the wide adaptability of camera according with camera alink standard.

Data reversal and line frequency flash synchronization separation module A4 have realized that the just reversal of data switches, if in many light stroboscopic occasions, according to stroboscopic synchronizing signal, the data that this module obtained different light fields cut into respective output channel automatically to realize the channel separation of light field, make things convenient for subsequent processing.

As shown in fig. 3, the image processing module B includes a normalization processing module B1, a synchronization parameter generation module B2, a multi-modal parallel binarization processing module B3, and a mathematical morphology processing module B4.

The normalization processing module B1 performs filtering, luminance analysis and noise analysis on the input raw image data, and provides a stable data reference source for the subsequent binarization processing.

The synchronization parameter generation module B2 automatically generates parameters of different corresponding detection modules according to the input position information of the original image, including different positions in the transverse direction and the longitudinal direction, and provides the parameters to the subsequent detection modules.

The multi-mode parallel binarization processing module B3 realizes the parallel processing of point, line and surface, 6 detection methods and sets different detection gray level threshold values for point defects to perform separate judgment. And (4) carrying out separate judgment on the linear defects by adopting a multidirectional matching threshold value. And for the planar shallow contrast defect, performing overall judgment by adopting a precision-reducing noise-reducing multi-dimensional threshold. Each detection mode can be matched with different detection working conditions of defects and the reaction of different light paths, and finally, the result is uniformly generated into a standard binary image by adopting an OR mode. The mathematical morphology processing module B4 performs mathematical morphology processing on the binary image to remove some isolated outliers and restore the overall structure of the defect.

As shown in fig. 4, the defect location screening module C includes a defect location fusion module C1, a defect filtering screening module C2, and a defect pending-sending cache module C3.

The defect positioning fusion module C1 performs horizontal and vertical fusion on the binary image output from the preceding stage, and obtains information such as area size and position of different components such as light, dark, and hole.

And the defect filtering and screening module C2 filters and screens the defects which do not meet the characteristic value condition according to the parameters set by the same user, so as to further reduce the subsequently sent defect data.

The defect to-be-sent buffer module C3 performs 32-bit encoding on the defect data to be launched, stores the encoded data into the defect FIFO, and waits for the network sending module to actively read the defect data to be sent.

As shown in fig. 5, the image buffer read-write module D includes a line image read-write buffer module D1, an image write control module D2, an image read control module D3, an image read-write DDR drive module D4, and an image buffer module D5 to be transmitted.

In the line image read-write buffer module D1, one path of the original image signal passes through the line image read-write buffer module D1 and enters the line image read-write buffer, and if a user line image read request is received, a line of data is directly sent to the image buffer module D5 to be sent.

The image write control module D2 assembles 128 bits of the original image, generates a DDR write address according to the data position, and the DDR uses a circular write mode, and can stop writing under a specific command, so as to ensure that the user completely reads data in the DDR.

In the image reading control module D3, the image acquisition command requested by the user includes a DDR start address, an image width, a height, and an interval, and the module starts a process of reading a DDR memory area according to these parameters until the reading is completed.

The image read-write DDR drive module D4 is used for coordinating the read-write module request, ensuring that continuous operation can be realized for each read-write to realize the best efficiency, and simultaneously, the module performs bottom layer read-write sequential operation on the DDR.

The image data and line image data acquired from the DDR by the image cache module D5 to be transmitted are assembled by 32 bits and then stored in the FIFO buffer for active reading by the subsequent network transmission module.

As shown in fig. 6, the auxiliary data processing module E includes a vehicle speed processing module E1, an IO-temperature-serial port processing module E2, an edge detection module E3, and a status data collection module E4.

The vehicle speed processing module E1 receives an externally input one-way or two-way orthogonal coding vehicle speed signal, the vehicle speed signal is filtered to obtain a periodic signal, the periodic signal is filtered to obtain a stable input period, the periodic data obtains a real camera exposure synchronizing signal according to a vehicle speed proportional parameter set by a user, and the vehicle speed signal is output through the state data collection module E4.

All input signals of the IO-temperature-serial port processing module E2 are subjected to filtering processing set by a user and then serve as scanning and frame triggering, state information is uploaded through the state data collection module E4, the source of an output signal can be set by the user to be output, and can also be a line scanning synchronous signal, the temperature module realizes the reading operation of a line temperature sensor, a temperature value is uploaded through the state data collection module E4, and the serial port module realizes the free switching function of three channels of a camera, an upper computer and a serial port on a board.

The edge detection module E3 realizes the tracking function of the front and back edges according to the input image original data, and the result is uploaded by the state data collection module E4.

The state data collection module E4 receives data to be uploaded by each submodule, such as temperature, IO level, vehicle speed, edge value, DDR read-write position, serial port received data and the like, and then assembles the data into network state data to be sent at intervals of 1-5 milliseconds at regular time, and meanwhile, the module also provides immediate sending control to realize rapid uploading of the state data.

As shown in fig. 7, the local area network transceiver module F includes a defect location data packet module F1, an image data packet module F2, a status data packet module F3, a transmission packet control module F4, a network MAC layer F5, and an ICMP interpretation module F6.

The defect location data package module F1 actively reads data in the previous stage defect FIFO under the control of the package control module F4, and in this module, data organization of the application data layer is realized, the first 32 bytes of the data are the identification code, sequence number, data length, etc. of the package data, and the following is the real defect location and feature data.

The image data packet packaging module F2 actively reads in the data in the image read buffer FIFO according to the control of the packet control module F4, and generates a frame of picture packet to be sent, where the front 32 bytes of the data are the identification code, sequence number, data length, picture ID, and other information of the packet data.

The state data packet module F3 reads data such as camera decoding state, input/output state, temperature value, vehicle speed value, edge position, serial port receiving character string, etc. according to the control of the packet control module F4, to form a frame of state packet to be sent, where the front 32 bytes of the data are information such as identification code, sequence number, data length, etc. of the packet data.

The transmission packet control module F4 performs transmission switching scheduling on the defect location data packet module F1, the image data packet module F2, and the status data packet module F3 according to the transmission condition of the following network MAC layer F5.

The network MAC layer F5 assembles the UDP layer, the IP layer, and the MAC layer of the transmitted packet data, calculates a CRC value, loads the CRC value to a packet queue to be transmitted, and waits for transmission.

The ICMP interpretation module F6 is used for realizing quick response to the Ping packet of the upper computer so as to facilitate network troubleshooting.

In the figure, the PHY chip is an ethernet physical interface transceiver (PHY) chip, and is connected to the network MAC layer F5 through interfaces (GMII/RGMII/SGMII, etc.), so as to implement ethernet data transceiving.

As shown in fig. 8, the parameter command detecting module G includes a command parsing module G1, a data configuration module G2, and a firmware upgrade module G3.

And the command analysis module G1 receives the network packet command of the upper computer and performs parameter decoding on the network packet command to acquire the working parameter setting required by each sub-module.

The data configuration module G2 receives the parameters of the command analysis module G1, stores the parameters into a FLASH parameter area, and actively loads the stored parameters during power-on initialization for initial setting of each module.

The firmware upgrading module G3 receives the upgrading command and data of the upper computer, the upgrading process is verified in sections, and a failure retransmission mechanism is supported.

The embodiments described above are intended to illustrate the technical solutions and advantages of the present invention, and it should be understood that the above-mentioned embodiments are only specific embodiments of the present invention, and are not intended to limit the present invention, and any modifications, additions and equivalents made within the scope of the principles of the present invention should be included in the scope of the present invention.

Claims

1. A data acquisition processing circuit for a Cameralink high-speed industrial camera is characterized by comprising a Cameralink signal decoding module, an image processing module, a defect positioning and screening module, an image cache read-write module, an auxiliary data processing module, a local area network transceiving module and a parameter command configuration module;

2. The data acquisition processing circuit for the Cameralink high-speed industrial camera as claimed in claim 1, wherein the Cameralink signal decoding module comprises a dynamic phase adjustment module, a camera data serial-parallel conversion byte recovery module, a row data recovery module, a data inversion and row flash synchronization separation module;

3. The data acquisition processing circuit for the Cameralink high-speed industrial camera as claimed in claim 1, wherein the image processing module comprises a standardization processing module, a synchronization parameter generation module, a multi-modal parallel binarization processing module and a mathematical morphology processing module;

4. The data acquisition and processing circuit for the Cameralink high-speed industrial camera as claimed in claim 1, wherein the defect localization and screening module comprises a defect localization and fusion module, a defect filtering and screening module and a defect to-be-sent cache module;

5. The data acquisition and processing circuit for the Cameralink high-speed industrial camera according to claim 1, wherein the image cache read-write module comprises a line image read-write cache module, an image write control module, an image read-write DDR drive module and an image cache module to be transmitted;

6. The data acquisition and processing circuit for the Cameralink high-speed industrial camera as claimed in claim 1, wherein the auxiliary data processing module comprises a vehicle speed processing module, an IO-temperature-serial port processing module, an edge detection module and a status data collection module;

the vehicle speed processing module is used for providing a vehicle speed signal according to the running speed of the detected material and further controlling to generate a camera line scanning synchronous signal; specifically, an externally input one-way or two-way orthogonal coding vehicle speed signal is filtered to obtain a periodic signal, the periodic signal is filtered to obtain a stable input period, the periodic data obtains a real camera line scanning synchronous signal according to a vehicle speed proportional parameter set by a user, and meanwhile, the vehicle speed signal is output to an upper computer through a state data collection module;

the IO-temperature-serial port processing module is used for realizing general input and output, detecting ambient temperature and realizing the functions of communication among the upper computer, the external equipment and the camera through a serial port protocol;

7. The data collecting and processing circuit for Cameralink high-speed industrial camera as claimed in claim 1, wherein said local area network transceiver module comprises a defect location data packet module, an image data packet module, a status data packet module, a transmission packet control module, a network MAC layer and an ICMP interpretation module;

the ICMP explanation module realizes the quick response to the Ping packet of the upper computer so as to facilitate the network troubleshooting.

8. The data acquisition processing circuit for a Cameralink high speed industrial camera as claimed in claim 1, wherein said parameter command detection module comprises a command parsing module, a data configuration module and a firmware upgrade module;

the command analysis module is used for receiving a network packet command of the upper computer and decoding parameters to obtain working parameter settings of the Cameralink signal decoding module, the image processing module, the defect positioning and screening module, the image cache read-write module and the auxiliary data processing module;

the data configuration module is used for receiving the parameters of the command interpretation module, storing the parameters into the FLASH parameter area, and actively loading the stored parameters during power-on initialization for initial setting of each module;