CN108924377B - DSP-based hardware compression core rapid reconfiguration method - Google Patents
DSP-based hardware compression core rapid reconfiguration method Download PDFInfo
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- CN108924377B CN108924377B CN201810588555.0A CN201810588555A CN108924377B CN 108924377 B CN108924377 B CN 108924377B CN 201810588555 A CN201810588555 A CN 201810588555A CN 108924377 B CN108924377 B CN 108924377B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/024—Details of scanning heads ; Means for illuminating the original
- H04N1/028—Details of scanning heads ; Means for illuminating the original for picture information pick-up
- H04N1/03—Details of scanning heads ; Means for illuminating the original for picture information pick-up with photodetectors arranged in a substantially linear array
- H04N1/031—Details of scanning heads ; Means for illuminating the original for picture information pick-up with photodetectors arranged in a substantially linear array the photodetectors having a one-to-one and optically positive correspondence with the scanned picture elements, e.g. linear contact sensors
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Abstract
A rapid reconfiguration method of a hardware compression core based on DSP is applied to a rapid reconfiguration device, the rapid reconfiguration device comprises the DSP, a CIS and an FPGA, an image acquisition circuit is constructed on the FPGA, the image acquisition circuit comprises the hardware compression core, and the method is characterized in that: it comprises the following steps: (1) constructing a logic layer of a hardware compression core based on a UART protocol on an FPGA; (2) image data are acquired in real time through the CIS and are transmitted to the DSP, and the DSP judges the image type according to the image data; (3) and (3) the DSP sends image compression configuration information to the hardware compression core through a preset UART protocol according to the image type, and returns to the step (2) to enter the configuration of the next image. The rapid reconfiguration method of the hardware compression core based on the DSP can issue image compression configuration information in real time according to image characteristics.
Description
Technical Field
The invention relates to the technical field of high-speed scanners, in particular to a rapid reconfiguration method of a hardware compression core based on a DSP.
Background
The electronization of the paper documents plays a positive role in improving the efficiency of electronic government affairs, and becomes an important mode for realizing the electronization of the government affairs. The contact image sensor (hereinafter referred to as CIS) scanner is an optical system because the CIS is an optical system, and an additional optical system is not needed, so that the contact image sensor has the advantages of simple structure, low cost, light weight and practicability, and is very suitable for image scanning of paper documents.
Spatial redundancy due to correlation between adjacent pixels in the image; temporal redundancy caused by correlation between different frames in the image sequence; spectral redundancy due to the correlation of different color planes or spectral bands. The goal of data compression is to reduce the number of bits required to represent the data by removing these data redundancies. Since the amount of image data is enormous, it is very difficult to store, transmit, and process the image data, and thus compression of the image data is very important. Different image compression ratios are selected according to different types of image characteristics, and the method has great significance for practical application.
The conventional high-speed CIS scanner generally includes an image capturing circuit for controlling capturing and processing related actions of an image and at least one control circuit for controlling actions of paper feeding, paper jamming, paper releasing, and the like. Currently, an FPGA is generally used to construct an image acquisition circuit and a control circuit, where the image acquisition circuit includes a hardware compression core and the control circuit includes a control chip. The hardware compression core based on the FPGA has the advantages of large compression bandwidth, high compression speed, low power consumption, good stability and the like, so that the hardware compression core based on the FPGA is widely applied to high-speed scanners. However, the hardware compression core constructed by the FPGA cannot determine the classification of the scanning medium by using a complex algorithm, so it is difficult to dynamically and automatically adjust the image compression configuration information of the hardware compression core, the image compression configuration information of the hardware compression core is mainly an image compression ratio, and under the condition that the image compression ratio of the hardware compression core is changed, the configuration information of a relevant register of a control chip of a general control circuit is also changed, such as the paper feeding speed and the like. The common method is to issue image compression configuration information at the PC, but because the PC itself needs to process many tasks, and the PC belongs to an upper protocol layer, and can reach a lower protocol layer through an intermediate multi-layer protocol layer, it is difficult to meet the real-time requirement of image scanning.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the rapid reconfiguration method of the hardware compression core based on the DSP, which can issue the image compression configuration information in real time according to the image characteristics, is provided.
The technical solution of the invention is as follows: a rapid reconfiguration method of a hardware compression core based on DSP is applied to a rapid reconfiguration device, the rapid reconfiguration device comprises the DSP, a CIS and an FPGA, an image acquisition circuit is constructed on the FPGA, the image acquisition circuit comprises the hardware compression core, and the method is characterized in that: it comprises the following steps:
(1) constructing a logic layer of a hardware compression core based on a UART protocol on an FPGA;
(2) image data are acquired in real time through the CIS and are transmitted to the DSP, and the DSP judges the image type according to the image data;
(3) and (3) the DSP sends image compression configuration information to the hardware compression core through a preset UART protocol according to the image type, and returns to the step (2) to enter the configuration of the next image.
After the method is adopted, the invention has the following advantages:
the rapid reconfiguration method of the hardware compression core based on the DSP utilizes the DSP to issue the image compression configuration information of the hardware compression core, and because the data processing capability of the DSP is very excellent and does not need to process a plurality of tasks like a PC terminal, the real-time requirement can be better met; secondly, as the PC end needs to process a plurality of tasks, the image data of the CIS can not be received in real time, the image data can be received only at intervals, and the DSP can receive the image data in real time, so that the image type can be judged more quickly; thirdly, as the DSP and the hardware compression core adopt a UART protocol at the bottom layer for communication, the image compression configuration information is more convenient and faster; the comprehensive action of the points enables the DSP to more quickly issue image compression configuration information in real time according to the image characteristics.
Preferably, in the step (2), the image type is determined according to a gray histogram of the image data, and the image type includes text and pictures. The gray level histogram is simple and convenient to operate, the judgment result is accurate, the real-time requirement can be met, and the image compression configuration information is more accurate.
Preferably, at least one control circuit is further constructed on the FPGA of the quick reconfiguration device, each control circuit at least includes one control chip, the logic layer based on the UART protocol of each control chip is further constructed on the FPGA in step (1), the hardware compression core and each UART protocol of each control chip include 4-10 bytes, each of the UART protocols includes a CRC check code, a control word, an address word and a data word, the control word includes a device number of the hardware compression core or one of the control chips of one of the control circuits, and the address word includes an address of a relevant register of the hardware compression core or one of the control chips of one of the control circuits. The setting firstly distinguishes the hardware compression core or the control chip of the control circuit on the control word, thereby being convenient to distinguish the address of the relevant register of the hardware compression core or the control chip of the control circuit on the address word, and further being more convenient to search the register.
Preferably, the control word further includes a broadcast address bit, and in the step (3), the DSP broadcasts and sends the image compression configuration information to the hardware compression core and each control chip of each control circuit through a preset UART protocol. The image compression configuration information is sent in a broadcasting mode, namely, the DSP can be divided into a plurality of branches only through one bus and then is directly connected to the hardware compression core and each control chip of each control circuit, the control words and the address words can be directly connected to the hardware compression core and relevant registers of each control chip of each control circuit through analysis, then the image compression configuration information can be rapidly sent to the hardware compression core and the relevant registers of each control chip of each control circuit through analysis of the data words, and the configuration speed is high.
Preferably, in the step (3), before the step (2) is returned to enter the configuration of the next image, the image compression configuration information of the hardware compression core and the relevant register of each control chip of each control circuit is read back through the DSP. The setting can be used for judging whether the image compression configuration information is reliably issued to the hardware compression core and the relevant registers of the control chips of the control circuits, and the reliability is higher.
Description of the drawings:
FIG. 1 is a main flow chart of a method for quickly reconfiguring a DSP-based hardware compression core according to the present invention;
Detailed Description
The invention is further described with reference to the following embodiments in conjunction with the accompanying drawings.
Example (b):
a method for quickly reconfiguring a hardware compression core based on a DSP is applied to a quick reconfiguration device, the quick reconfiguration device comprises the DSP, a CIS and an FPGA, an image acquisition circuit is constructed on the FPGA and comprises the hardware compression core, the image acquisition circuit adopts the prior art, and the method comprises the following steps:
(1) constructing a logic layer of a hardware compression core based on a UART protocol on an FPGA;
(2) image data are acquired in real time through the CIS and are transmitted to the DSP, and the DSP judges the image type according to the image data;
(3) and (3) the DSP sends image compression configuration information to the hardware compression core through a preset UART protocol according to the image type, and returns to the step (2) to enter the configuration of the next image.
The rapid reconfiguration method of the hardware compression core based on the DSP utilizes the DSP to issue the image compression configuration information of the hardware compression core, and because the data processing capability of the DSP is very excellent and does not need to process a plurality of tasks like a PC terminal, the real-time requirement can be better met; secondly, as the PC end needs to process a plurality of tasks, the image data of the CIS can not be received in real time, the image data can be received only at intervals, and the DSP can receive the image data in real time, so that the image type can be judged more quickly; thirdly, as the DSP and the hardware compression core adopt a UART protocol at the bottom layer for communication, the image compression configuration information is more convenient and faster; the comprehensive action of the points enables the DSP to more quickly issue image compression configuration information in real time according to the image characteristics.
Preferably, in the step (2), the image type is determined according to a gray histogram of the image data, and the image type includes text and pictures. The gray level histogram is simple and convenient to operate, the judgment result is accurate, the real-time requirement can be met, and the image compression configuration information is more accurate.
Preferably, at least one control circuit is further constructed on the FPGA of the quick reconfiguration device, each control circuit at least includes one control chip, the control circuit may adopt the prior art, the step (1) further constructs a logic layer based on the UART protocol of each control chip on the FPGA, each UART protocol of the hardware compression core and each control chip includes 4 to 10 bytes, for example, 7 bytes, including a CRC check code, a control word, an address word and a data word, the control word includes a device number of the hardware compression core or one control chip of one of the control circuits, and the address word includes an address of a relevant register of the hardware compression core or one of the control chips of one of the control circuits. The high-speed CIS scanner is provided with an image acquisition circuit for acquiring and processing images and a control circuit for controlling actions of paper feeding, paper jamming, paper releasing and the like, wherein image compression configuration information mainly configures the compression ratio of a hardware compression core of the image acquisition circuit, but under the condition that the compression ratio of the hardware compression core is changed, for example, the paper feeding speed is also changed correspondingly, so that a register related to the paper feeding speed in a control chip of the control circuit is also configured correspondingly, and the setting can distinguish the configuration of the hardware compression core from the control chip of the control circuit on a control word, so that the address of the related register of the hardware compression core or the control chip of the control circuit can be distinguished conveniently on the address word, and the register can be searched more conveniently.
Preferably, the control word further includes a broadcast address bit, and in the step (3), the DSP broadcasts and sends the image compression configuration information to the hardware compression core and each control chip of each control circuit through a preset UART protocol. The image compression configuration information is sent in a broadcasting mode, namely, the DSP can be divided into a plurality of branches only through one bus and then is directly connected to the hardware compression core and each control chip of each control circuit, the control words and the address words can be directly connected to the hardware compression core and relevant registers of each control chip of each control circuit through analysis, then the image compression configuration information can be rapidly sent to the hardware compression core and the relevant registers of each control chip of each control circuit through analysis of the data words, and the configuration speed is high.
Preferably, in the step (3), before the step (2) is returned to enter the configuration of the next image, the image compression configuration information of the hardware compression core and the relevant register of each control chip of each control circuit is read back through the DSP. The setting can be used for judging whether the image compression configuration information is reliably issued to the hardware compression core and the relevant registers of the control chips of the control circuits, and the reliability is higher.
Claims (1)
1. A rapid reconfiguration method of a hardware compression core based on DSP is applied to a rapid reconfiguration device, the rapid reconfiguration device comprises the DSP, a CIS and an FPGA, an image acquisition circuit is constructed on the FPGA, the image acquisition circuit comprises the hardware compression core, and the method is characterized by comprising the following steps: (1) constructing a logic layer of a hardware compression core based on a UART protocol on an FPGA;
(2) image data are acquired in real time through the CIS and are transmitted to the DSP, and the DSP judges the image type according to the image data; (3) the DSP sends image compression configuration information to the hardware compression core through a preset UART protocol according to the image type, and returns to the step (2) to enter the configuration of the next image; judging the image type according to the gray level histogram of the image data in the step (2), wherein the image type comprises a text and a picture; the FPGA of the quick reconfiguration device is further at least provided with a control circuit, each control circuit at least comprises a control chip, the FPGA of step (1) is further provided with a logic layer based on a UART protocol of each control chip, the hardware compression core and each UART protocol of each control chip comprise 4-10 bytes, each of the bytes comprises a CRC check code, a control word, an address word and a data word, the control word comprises a device number of the hardware compression core or one control chip of one of the control circuits, and the address word comprises an address of the hardware compression core or a relevant register of one control chip of one of the control circuits; the high-speed CIS scanner is provided with an image acquisition circuit for acquiring and processing images, and also provided with a control circuit for controlling paper feeding, paper jamming and paper placing actions, wherein image compression configuration information is the compression ratio of a hardware compression core for configuring the image acquisition circuit; the control word also comprises a broadcast address bit, and the DSP in the step (3) broadcasts and sends image compression configuration information to the hardware compression core and each control chip of each control circuit through a preset UART protocol; sending image compression configuration information in a broadcasting mode, namely enabling the DSP to be divided into a plurality of branches only through one bus, then directly connecting the branches to a hardware compression core and each control chip of each control circuit, directly connecting the branches to the hardware compression core and relevant registers of each control chip of each control circuit through analyzing control words and address words, and then quickly sending the image compression configuration information to the hardware compression core and the relevant registers of each control chip of each control circuit through analyzing data words; in the step (3), before returning to the step (2) to enter the configuration of the next image, the image compression configuration information of the hardware compression core and the relevant registers of the control chips of the control circuits is read back through the DSP; the setting can be used to determine whether the image compression configuration information is reliably issued to the hardware compression core and the relevant registers of the control chips of the control circuits.
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Denomination of invention: A fast reconfiguration method of hardware compression core based on DSP Effective date of registration: 20220125 Granted publication date: 20210706 Pledgee: Ningbo Tianjin Enterprise Service Co.,Ltd. Pledgor: NINGBO HUAGAO INFORMATION TECHNOLOGY CO.,LTD. Registration number: Y2022330000164 |
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Date of cancellation: 20230511 Granted publication date: 20210706 Pledgee: Ningbo Tianjin Enterprise Service Co.,Ltd. Pledgor: NINGBO HUAGAO INFORMATION TECHNOLOGY CO.,LTD. Registration number: Y2022330000164 |