CN102074003A - Mean shift-based embedded type image tracking system - Google Patents

Abstract

The invention relates to the field of industrial control and identification, in particular to a mean shift-based embedded type image tracking system. The mean shift-based embedded type image tracking system comprises a Cameralink interface, a field programmable gate array (FPGA), a first data storage, a shared storage, a digital signal processor (DSP), a second storage, a program storage, an analog/digital (A/D) chip, a digital/analog (D/A) chip and a display. For the mean shift-based embedded type image tracking system, the FPGA and the DSP serve as embedded type hardware platforms of an image processor; and on the basis of the conventional mean shift technique, a mean shift fast algorithm applicable to an embedded processor is invented, a special basic module group of the mean shift algorithm is established on the FPGA, and finally, major operations and decisions are performed on the DSP. So, the operation speed of the mean shift-based embedded type image tracking system is far faster than that of the conventional mean shift algorithm which uses a personal computer (PC) machine as a hardware platform.

Description

Embedded image tracker based on average drifting

Technical field

The present invention relates to Industry Control and identification field, particularly a kind of embedded image tracker based on average drifting.

Background technology

At present in computer vision and area of pattern recognition average drifting technology as a kind of extensive concern that has obtained the researcher based on the statistics iterative algorithm of feature.Many improvement algorithms based on average drifting have all obtained in image tracking field widely using, but great majority all are hardware platform with the PC based on the image processor of average drifting algorithm.Be that processing platform causes the entire image tracker can't accomplish miniaturization and involve great expense with the PC.And the image tracking processor of embedded platform is many with simple relatively type center algorithm, and related algorithm is main.Based on the image processor of these algorithms, follow the tracks of though can under simple background, carry out real-time and effective target, do not possess anti-the blocking property of average drifting algorithm, promptly there is the situation that target is blocked will lose objects slightly, cause following the tracks of inefficacy.Therefore, it is imperative to develop a kind of novel image tracking system.

Summary of the invention

At the problems referred to above, in order to address the deficiencies of the prior art, purpose of the present invention just is to provide a kind of embedded image tracker based on average drifting, can effectively solve the anti-problem that blocking property is poor, cost is high.

The technical scheme that technical solution problem of the present invention adopts is, embedded image tracker based on average drifting, comprise Cameralink interface, FPGA, first data-carrier store, shared storage, DSP, second memory, program storage, A/D chip, D/A chip and display, the Cameralink interface links to each other with FPGA, and the Cameralink interface passes to FPGA with digital video frequency flow; The A/D chip links to each other with FPGA, and the A/D chip passes to FPGA with the CVBS video flowing; FPGA links to each other with first data-carrier store, and FPGA stores to first data-carrier store processed video data transfer; FPGA links to each other with shared storage, FPGA will handle after data transfer store to shared storage; DSP links to each other with program storage, and DSP calls out program stored in the program storage; DSP links to each other with shared storage, and the data transfer that shared storage will be stored in is wherein given DSP; DSP links to each other with second data-carrier store, and the data transfer after DSP will handle stores for second data-carrier store and shared storage; FPGA links to each other with the D/A chip, and FPGA handles and pass to the D/A chip with the data that the shared storage transmission comes; The D/A chip links to each other with display, and the D/A chip shows the processed video data transfer to display.

The present invention is with FPGA and the DSP embedded hardware platform as image processor, on the basis of traditional average drifting technology, invented the average drifting fast algorithm that is applicable to flush bonding processor, and on FPGA, made up the basic module group of special-purpose average drifting algorithm, on DSP, carry out main computing and decision-making at last.Making its arithmetic speed be far longer than traditional is the arithmetic speed of the average drifting algorithm of hardware platform with the PC.

Description of drawings

Fig. 1 is the structured flowchart of the embedded image tracker based on average drifting of the present invention.

Fig. 2 is the algorithm flow chart of FPGA of the present invention and DSP.

Embodiment

Below in conjunction with accompanying drawing the specific embodiment of the present invention is elaborated.

By shown in Figure 1, embedded image tracker based on average drifting, it is characterized in that, comprise Cameralink interface, FPGA, first data-carrier store, shared storage, DSP, second memory, program storage, A/D chip, D/A chip and display, the Cameralink interface links to each other with FPGA, and the Cameralink interface passes to FPGA with digital video frequency flow; The A/D chip links to each other with FPGA, and the A/D chip passes to FPGA with the CVBS video flowing; FPGA links to each other with first data-carrier store, and FPGA stores to first data-carrier store processed video data transfer; FPGA links to each other with shared storage, and the data transfer after FPGA will handle is stored to shared storage; DSP links to each other with program storage, and DSP calls out program stored in the program storage; DSP links to each other with shared storage, and the data transfer that shared storage will be stored in is wherein given DSP; DSP links to each other with second data-carrier store, and the data transfer after DSP will handle stores for second data-carrier store and shared storage; FPGA links to each other with the D/A chip, and FPGA handles and pass to the D/A chip with the data that the shared storage transmission comes; The D/A chip links to each other with display, and the D/A chip shows the processed video data transfer to display.

By shown in Figure 2, the algorithm flow concrete steps of said FPGA and DSP are as follows:

1) FPGA sets the iterations K of K mean algorithm;

2) the FPGA search is positioned at each pixel histogram of FPGA candidate subregion;

3) FPGA calculates the target histogram on the not normalized FPGA candidate subregion

Obtain

Q wherein _uThe intensity profile of expression To Template, p _uThe intensity profile of expression candidate target;

4) each pixel of FPGA calculated candidate target area

W wherein _iThe weight of representing each pixel, δ _UrThe remarked pixel histogram;

5) FPGA calculate the new new center z=that transmits the view data of coming (x, y);

6) (x y) gives DSP by the shared data memory transfer to the new center z=of the new transmission that will calculate of the FPGA view data of coming;

7) (x y) carries out error-tested to DSP to the center z=that calculates

7.1) if error meets the demands or FPGA computation process in iterations surpass K, then DSP calculates and finishes, with new place-centric z=(x, y) data pass to FPGA by shared storage, FPGA passes to display with the view data that meets the demands by the D/A chip, and the algorithm of FPGA and DSP finishes;

7.2) if error does not meet the demands or FPGA computation process in iterations be no more than K, then DSP passes to FPGA with data by shared storage, FPGA resets iterations, returns step 1).

DSP is MS320C6416T in of the present invention, and FPGA adopts the ALTERA EP2C70-6 of company; The shared storage of DSP and FPGA adopts the IDT71321 two-port RAM, and the A/D chip adopts the BT835 dedicated video decoding chip of PHILPS company.

In the hardware design of total system, taken into full account the electromagnetic Compatibility Design of high speed signal, in the wiring of key signal (camralink differential signal, SDRAM data-signal), carried out isometric design, guaranteed that the impedance matching of each signal and sequential are synchronous.In whole plate design, utilize allegro software that Electro Magnetic Compatibility is detected and adjusts, satisfy the application need of high speed digital video signal.

Traditional average drifting algorithm is divided into 16*16*16 or other big or small sub-range uniformly with the color space of target area.The histogram processing of changing the branch generation like this needs a large amount of memory headrooms.Can't develop the hardware platform that parallel algorithm so portion are applicable to the FPGA framework at all, this programme at first carries out cluster analysis with means clustering algorithm to the color model of target, match by mixture gaussian modelling is carried out self-adaptation to the rgb space of target area and is divided then, and the color of object spatial division is become less histogram.Can express target distribution accurately with less subspace like this.

Original state adopt K mean algorithm (K-means) for each cluster u (u=1 ..., m-1), wherein m-1 is the number of cluster, uses the distribution of pixel data in each cluster of Gaussian function match of multivariate parameter then

$G({\mathrm{\μ}}_n,{\mathrm{\Σ}}_u)\∞\exp [-\frac{1}{2}{(c-{\mathrm{\μ}}_u)}^T{\mathrm{\Σ}}_u^{-1}(c-{\mathrm{\μ}}_u)]$

In the formula, G represents Gaussian function, and T represents matrix transpose, c represent pixel RGB vector; μ _uRepresent mean vector, ∑ _uRepresent covariance matrix.

The program initialization part is calculated good mean vector μ with m-1 on DSP _uWith the covariance matrix ∑ _uStore on the two-port RAM between DSP and the FPGA, when a new two field picture arrives, select a number of sub images of current goal region; The center of this number of sub images is exactly the center of previous frame tracking target, and the size of subimage is 2 times that previous frame is followed the general objective size.Then all rgb values of this subimage are transferred on the two-port RAM and store.

Utilize shift register to realize adding and computing of view data in the algorithm flow among the FPGA, The pipeline design is adopted in computing, and its unit-distance code time can shorten to 16 machine clock cycles.Utilize the large tracts of land characteristic of FPGA, can realize a plurality of thread block independent sub-histogram of independent processing simultaneously.Simultaneously in FPGA, adopt time-sequence control module, accurately dispose the read-write of two-port RAM, promptly accomplished FPGA and DSP shared data storer simultaneously, prevented the read/write conflict of sharing data area again.

The view data that DSP reads shared drive adopts the EDMA read-write mode, make core processor provide transmission at the EDMA manager and finish that notice CPU carries out Data Update when interrupting without the read-write operation of management data, utilize cpu resource to carry out arithmetic operation to greatest extent, improved data throughput capabilities and big data quantity arithmetic capability.

In the management of peripheral image A/D chip, adopt the I2C bussing technique, and realize, make system can support analog and digital video simultaneously, expanded the versatility of system with the FPGA state machine.

The present invention is with FPGA and the DSP embedded hardware platform as image processor, on the basis of traditional average drifting technology, invented the average drifting fast algorithm that is applicable to flush bonding processor, and on FPGA, made up the basic module group of special-purpose average drifting algorithm, on DSP, carry out main computing and decision-making at last.Making its arithmetic speed be far longer than traditional is the arithmetic speed of the average drifting algorithm of hardware platform with the PC.

Claims (2)

1. based on the embedded image tracking system of mean shift, it is characterized in that, comprises Cameralink interface, FPGA, the first data memory, shared memory, DSP, the second memory, program memory, A/D chip, D/A chip and display , the Cameralink interface is connected with the FPGA, and the Cameralink interface transmits the digital video stream to the FPGA; the A/D chip is connected with the FPGA, and the A/D chip transmits the CVBS video stream to the FPGA; the FPGA is connected with the first data memory, and the FPGA passes the processed The video data is transmitted to the first data memory for storage; the FPGA is connected to the shared memory, and the FPGA passes the processed data to the shared memory for storage; the DSP is connected to the program memory, and the DSP calls out the program stored in the program memory; the DSP and the shared memory connected, the shared memory transfers the data stored therein to the DSP; the DSP is connected to the second data memory, and the DSP transfers the processed data to the second data memory and the shared memory for storage; the FPGA is connected to the D/A chip, and the FPGA will The data transmitted by the shared memory is processed and transmitted to the D/A chip; the D/A chip is connected to the display, and the D/A chip transmits the processed video data to the display for display. 2. the embedded image tracking system based on mean value drift according to claim 1, is characterized in that, the algorithm flow concrete steps of said FPGA and DSP are as follows: 1) The number of iterations K of the K-means algorithm is set by the FPGA; 2) FPGA searches for each pixel histogram located in the FPGA candidate sub-region; 3) FPGA calculates the target histogram on the unnormalized FPGA candidate sub-region get

where q _u represents the gray distribution of the target template, and p _u represents the gray distribution of the candidate target; 4) FPGA calculates each pixel of the candidate target area

where W _i represents the weight of each pixel, δ _ur represents the pixel histogram; 5) FPGA calculates the new center position z=(x, y) of the image data that transmits newly; 6) FPGA transmits the new center position z=(x, y) of the newly transmitted image data calculated to DSP by the shared data memory; 7) DSP performs an error check on the calculated center position z=(x, y) 7.1) If the error meets the requirements or the number of iterations in the FPGA calculation process exceeds K, then the DSP calculation ends, and the new position center z=(x, y) data is passed to the FPGA through the shared memory, and the FPGA passes the image data that meets the requirements through The D/A chip is passed to the display, and the algorithm of FPGA and DSP ends; 7.2) If the error does not meet the requirements or the number of iterations in the FPGA calculation process does not exceed K, then the DSP transfers the data to the FPGA through the shared memory, the FPGA resets the number of iterations, and returns to step 1).

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