CN113030535A

CN113030535A - Short circuit probe card, wafer test system and fault cause detection method of system

Info

Publication number: CN113030535A
Application number: CN201911249807.8A
Authority: CN
Inventors: 甘仲轩; 林淑琪; 陈义超; 蔡元隆; 何玄敏
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2019-12-09
Filing date: 2019-12-09
Publication date: 2021-06-25

Abstract

The invention provides a short circuit probe card, a wafer test system and a fault cause detection method of the system, wherein the short circuit probe card comprises the following components: a substrate having an upper surface and a lower surface; a plurality of first contacts formed on the upper surface; and a plurality of second contacts formed on the lower surface and connected to the plurality of first contacts, wherein the plurality of first contacts and the plurality of second contacts are all grounded. The invention can rapidly distinguish the fault part of the wafer test system.

Description

Short circuit probe card, wafer test system and fault cause detection method of system

Technical Field

The invention relates to a short-circuit probe card, a wafer test system and a fault cause detection method of the wafer test system, which can quickly distinguish fault parts of the wafer test system.

Background

The mass-produced wafers (wafers) are sequentially placed into a wafer test system for electrical testing. The wafer test system is provided with a test head and a probe card, and the test head is used for contacting the wafer through the probe card. Before the formal test, the machine must be pre-tested to ensure that the test head and the probe card have no fault (such as short circuit or open circuit) so as to avoid the misjudgment of the wafer during the formal test. However, when a failure is found in a pretest, since it is not certain that the failure occurs at a portion of the test head or the probe card, it is necessary to perform inspection and maintenance of the test head and the probe card through complicated steps, and a lot of labor and inspection time are consumed.

Disclosure of Invention

The invention provides a short-circuit probe card, a wafer test system and a fault cause detection method of the wafer test system, which can quickly distinguish fault parts of the wafer test system.

The invention provides a short circuit probe card, comprising: a substrate having an upper surface and a lower surface; a plurality of first contacts formed on the upper surface; and a plurality of second contacts formed on the lower surface and connected to the plurality of first contacts, wherein the plurality of first contacts and the plurality of second contacts are all grounded.

The invention provides a wafer test system for testing electrical properties of a wafer, comprising: a short circuit probe card having a plurality of contacts connected to ground; a test head connected to the plurality of contacts of the shorting probe card; and a contact monitoring device connected to the test head for testing whether the plurality of contacts are all short-circuited.

The invention provides a fault reason detection method of a wafer test system, which comprises the following steps: connecting a test head with a probe card; contacting a probe surface of the probe card with a wafer to detect a plurality of detection points; checking whether there is an open circuit in the plurality of detection points; when an open circuit exists in the plurality of detection points, the probe card is replaced by a short circuit probe card, wherein all contacts on the short circuit probe card are grounded; and checking whether an open circuit still exists in the plurality of detection points.

Drawings

FIG. 1 is a schematic diagram showing a wafer test system according to the present invention.

Fig. 2A is an example of a touch monitoring device of the present invention displaying a detection result on a display.

Fig. 2B shows an example of the voltage determination level when the probe card is used for detection.

Fig. 3A is a top view illustrating a shorting probe card according to an embodiment of the present invention.

Fig. 3B is a cross-sectional view of a-a' line showing the shorting probe card of fig. 3A.

Fig. 4 is a schematic configuration diagram showing that the shorting probe card is replaced in the wafer test system according to the present invention.

Fig. 5 shows an example of the voltage determination level when the short-circuited probe card is used for detection.

FIG. 6 is a flow chart of the method for detecting the cause of failure in the wafer test system according to the present invention.

Description of the symbols

1. A wafer test system;

10. a probe card;

10a, shorting the probe card;

20. a test head;

30. a contact monitoring device;

101. a substrate;

101U, upper surface;

101L, lower surface;

102. a first contact;

103. a second contact;

104. a connector;

104U, upper contact;

104L, lower contact;

F. a detection point failing detection;

p, passing the detected point;

w, wafer.

Detailed Description

The following description provides many different embodiments for implementing different features of the invention. The particular examples set forth below are illustrative only and are not intended to be limiting. For example, the description of a structure having a first feature over or on a second feature may include direct contact between the first and second features, or another feature disposed between the first and second features, such that the first and second features are not in direct contact.

Spatially relative terms, such as above or below, are used herein for ease of description of one element or feature relative to another element or feature. Devices used or operated in different orientations than those depicted in the figures are also contemplated. The shapes of the figures, dimensions, and thicknesses may be exaggerated for clarity and are not drawn to scale or simplified for illustrative purposes only.

FIG. 1 is a schematic diagram showing a wafer test system according to the present invention. The wafer test system 1 includes: probe card 10, test head 20, contact monitoring device 30. In the wafer test, the lower surface (i.e., the probe surface) of the probe card 10 contacts the wafer W through the probes, the upper surface of the probe card 10 is electrically connected to the test head 20 through the probe card side connector, and the test head 20 transmits signals to the contact monitoring device 30. Therefore, the contact monitoring apparatus 30 can determine whether there is a short circuit or open circuit abnormality on the path of the test head 20 to the wafer W through the probe card 10 according to the received signal.

The upper and lower surfaces of the probe card 10 are provided with contacts electrically connected to each other. The contacts of the upper surface of the probe card 10 are electrically connected to a probe card side connector (not shown), and the contacts of the lower surface are electrically connected to probes also provided on the lower surface. Since the distribution pattern of the probes is designed according to the wafer W to be measured, the probe card 10 in which the probes are arranged corresponding to the wafer W is required to inspect different wafers W.

The test head 20 has a test head side connector (not shown) at its front end for electrical connection with the probe card side connector.

The contact monitoring device 30 may be, for example, a computer in which a contact monitoring program is installed for monitoring the electrical connection state between the wafer W, the probe card 10 and the test head 20. When the contact monitoring apparatus 30 executes the contact monitoring program, the electrical connection status (e.g., voltage) between the wafer W, the probe card 10 and the test head 20 can be displayed on the display according to the signal transmitted from the test head 20, so that the operator can view the detection result.

For example, when the wafer testing system 1 tests the wafer W, the contact monitoring apparatus 30 may execute the contact monitoring program to display the results of all the probes detected by the wafer W on the display. As shown in fig. 2A, a plurality of points are displayed on the screen, where a detection point P indicated by o represents a detection point that passes detection, and a detection point F indicated by ● represents a detection point that fails detection (for example, short circuit or open circuit). For example, as shown in fig. 2B, the contact monitoring program may preset to display the point where the voltage is between 0V and 0.2V (Short) and the voltage is higher than 1V (Open) as the detection point F of failing detection, and set to display the point where the voltage is between 0.2V and 1V as the detection point p (pass) of passing detection. Further, each point has detailed detection information (for example, voltage, etc.), and when there is a detection point F that fails detection, the operator can confirm that the detection point F is open or short-circuited, and then perform failure removal.

For example, when the detecting point F that fails the detection is short-circuited, the detection can be performed again at different positions on the wafer W, and if the detecting point F that has the same short-circuit continues to appear, it represents a problem that the wafer test system 1 itself has a short-circuit, and it is necessary to further determine whether the probe card 10 or the test head 20 is short-circuited for maintenance. In one embodiment, the probe card 10 can be removed from the wafer test system 1, and if the short-circuited detection point F is changed to an open-circuit state, it represents a problem of short-circuit of the probe card 10; if the short circuit is still detected at the detection point F, it represents a short circuit problem in the test head 20. Therefore, it can quickly distinguish whether the probe card 10 or the test head 20 has a short circuit problem, and immediately proceed to eliminate the fault.

When the detection point F that fails the detection is open, the detection can be performed again at a different position on the wafer W, and if the detection point F that is open continues to appear, the problem of open circuit of the wafer test system 1 itself is represented, and it is necessary to further determine whether the probe card 10 or the test head 20 is open for maintenance. However, since all the detecting points are always displayed as the open detecting points F when the probe card 10 is removed from the wafer test system 1, the probe card 10 and the test head 20 must be inspected at the same time to confirm the source of the failure, which causes a problem of complicated and time-consuming steps.

The following embodiments further provide the shorting probe card of the present invention and a method for rapidly distinguishing whether the probe card 10 or the test head 20 is open in the wafer test system 1 through the shorting probe card. First, a shorting probe card 10a is provided. The shorting probe card 10a can be formed by improving the probe card 10. Fig. 3A is a top view illustrating a shorting probe card according to an embodiment of the present invention. Fig. 3B is a cross-sectional view of a-a' line showing the shorting probe card of fig. 3A. As can be seen in fig. 3A and 3B, shorting probe card 10a has a circular substrate 101. A plurality of first contacts 102 are formed on the upper surface 101U of the substrate 101. A plurality of second contacts 103 are formed on the lower surface 101L of the substrate 101, and each of the second contacts 103 is electrically connected to one of the first contacts 102 of the upper surface 101U.

In particular, all the second contacts 103 of the shorting probe card 10a according to the present invention are grounded by means of soldering or the like. Thus, all the potentials of all the contacts on the shorted probe card 10a are grounded to form a short circuit. In other embodiments of the present invention, all the first contacts 102 may be soldered to ground to form a short circuit.

In one embodiment, the upper surface 101U of the shorting probe card is further configured with a plurality of connectors 104 (i.e., the probe card side connectors described above) for engaging the shorting probe card 10a with the test head 20. The connector 104 has a bottom plate and an upright wall rising from the center of the bottom plate, and is in the shape of an inverted T when viewed from the side. A plurality of upper contacts 104U are formed on both sides of the upright wall, and a plurality of lower contacts 104L (connector contacts) are formed on the bottom plate. Each of the upper contacts 104U is electrically connected to a respective one of the lower contacts 104L. Each lower contact 104L of the connector 104 contacts a first contact 102 on the upper surface 101U. In this way, the electrical data can be transmitted through the electrical connection path formed by each of the upper contact 104U, the lower contact 104L, the first contact 102, and the second contact 103 of the connector 104.

When the wafer test system 1 has an open circuit failure, the present invention can rapidly distinguish whether the probe card 10 or the test head 20 is open by shorting the probe card 10a as described above. Specifically, for example, as shown in fig. 4, the probe card 10 is taken out of the wafer test system 1 and replaced with a short-circuited probe card 10 a. Here, since all the second contacts of the shorting probe card 10a are grounded, the contact monitoring device 30 detects the detection result of the short circuit after being bonded to the test head 20. At this time, if the detection point of the open circuit occurs, it represents that the test head 20 has an open circuit fault; on the contrary, if there is no open detection point, it represents that the original probe card 10 has an open failure. By replacing the shorting probe card 10a in the wafer test system 1, the open-circuit fault location in the wafer test system 1 can be quickly identified.

In one embodiment, the determination levels of the contact monitoring device 30 for determining short circuits and open circuits and the display mode may be modified in response to the use of the short circuit probe card 10 a. Fig. 5 shows an example of the voltage determination level when the short-circuited probe card 10a is used for detection. Here, when the detected voltage is between 0V and 0.1V, the contact monitoring device 30 may determine that it is a short circuit and display it as the passing detection point o, and when the detected voltage is higher than 0.1V, the contact monitoring device 30 may determine that it is an open circuit and display it as the failing detection point ●, so as to facilitate rapid determination by visualization. That is, when the detected voltage is 0-0.1V, it represents that the original probe card 10 has an open circuit fault. When a voltage above 0.1 is detected, it indicates an open circuit fault with test head 20.

Next, a method for detecting a cause of failure in a wafer test system according to the present invention will be described. FIG. 6 is a flow chart of the method for detecting the cause of failure in the wafer test system according to the present invention. In fig. 6, a pretest is first performed to detect the presence or absence of a failure in the wafer test system 1. In step S1, the test head 20 and the probe card 10 are connected. Next, in step S2, the probes of the lower surface (i.e., the probe surface) of the probe card 10 are brought into contact with the wafer W to obtain a detection result. In step S3, the presence or absence of the point F of failure detection is confirmed, and if the point F of failure detection is not present, it represents that the wafer test system is not faulty, and all steps are terminated. If the detection result shows that the detection point F fails to pass the detection, the state of open circuit or short circuit is further judged according to the voltage level. If the detection point F failing the detection is open, the process proceeds to step S4 to determine the location of the open circuit, and if the detection point F failing the detection is short, the process proceeds to step S8 to determine the location of the short circuit.

In step S4, the probe card 10 is removed and replaced with a shorted probe card 10a as shown in fig. 3A and 3B in which all contacts are grounded. Next, in step S5, the connection state of the shorting probe card 10a is checked. At this time, since all the contacts of the short-circuited probe card 10a are short-circuited, if the detection result indicates that there is no open circuit, it is confirmed that the open circuit failure originally detected at step S3 is a portion of the probe card 10, and the probe card 10 is maintained (step S6). On the other hand, if the detection result indicates an open detection point, it is confirmed that the open failure detected in step S3 occurred at the site of the test head 20, and the test head 20 is repaired (step S7).

When it is determined in step S3 that the detection point F that failed detection is a short circuit, the routine proceeds to step S8. In step S8, the probe card 10 is removed. Next, in step S9, the state of the test head 20 itself is checked. At this time, if the detection result shows that there is no short circuit on the wafer test system, it is confirmed that the short circuit failure originally detected at step S3 is occurred at the portion of the probe card 10, and the probe card 10 is repaired (step S10). On the contrary, if the detection result shows that there is a short circuit in the wafer test system, it is confirmed that the short circuit fault originally detected in step S3 is occurred at the site of the test head 20, and the test head 20 is repaired (step S11).

According to the method for detecting the fault cause of the wafer test system, whether the wafer test system has open circuit or short circuit fault can be quickly detected, the fault part can be confirmed, and the time for repeatedly confirming the fault state of the probe card 10 and the test head 20 can be saved.

While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation, such that various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention. Therefore, the above embodiments should not be taken as limiting the scope of the invention, which is defined by the following claims.

Claims

1. A shorting probe card, comprising:

a substrate having an upper surface and a lower surface;

a plurality of first contacts formed on the upper surface; and

a plurality of second contacts formed on the lower surface and connected to the plurality of first contacts,

wherein the plurality of first contacts and the plurality of second contacts are all grounded.

2. The shorting probe card of claim 1, further comprising:

a plurality of connectors having a plurality of upper contacts and a plurality of lower contacts connected to the plurality of upper contacts,

the connector is configured on the upper surface, so that the plurality of lower contacts are electrically connected to at least one part of the first contacts.

3. The shorting probe card of claim 1, wherein the plurality of second contacts are soldered to ground.

4. The shorting probe card of claim 1, wherein the first plurality of contacts are soldered to ground.

5. A wafer test system for electrical testing of a wafer, comprising:

a short circuit probe card having a plurality of contacts connected to ground;

a test head connected to the plurality of contacts of the shorting probe card; and

and the contact monitoring device is connected to the test head and used for testing whether the contacts are all short-circuited.

6. The wafer test system of claim 5, wherein the shorting probe card further has a plurality of connectors for connecting with the test head, the plurality of connectors having a plurality of connector contacts corresponding to the plurality of contacts connected to the shorting probe card.

7. A method for detecting fault causes of a wafer test system is characterized by comprising the following steps:

connecting a test head with a probe card;

contacting a probe surface of the probe card with a wafer to detect a plurality of detection points;

checking whether there is an open circuit in the plurality of detection points;

when an open circuit exists in the plurality of detection points, the probe card is replaced by a short-circuit probe card, wherein all contacts on the short-circuit probe card are grounded; and

checking whether there is still an open circuit in the plurality of detection points.

8. The method as claimed in claim 7, wherein the checking whether there is still an open circuit in the plurality of inspection points further comprises:

if the plurality of detection points have no open circuit, judging that the probe card has open circuit fault; and

and if the plurality of detection points still have open circuits, judging that the test head has open circuit faults.

9. The method of claim 7, further comprising:

contacting the probe face of the probe card with the wafer;

checking whether there is a short circuit in the plurality of detection points;

removing the probe card under the condition that short circuit exists in the plurality of detection points; and

checking whether there is still a short circuit in the plurality of detection points.

10. The method as claimed in claim 9, wherein the checking whether there is still a short circuit in the plurality of detection points further comprises:

if the plurality of detection points are not short-circuited, judging that the probe card has a short-circuit fault; and

and if the plurality of detection points still have short circuits, judging that the test head has a short circuit fault.