CN113012739A - Memory device and operation method thereof - Google Patents
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- CN113012739A CN113012739A CN201911322465.8A CN201911322465A CN113012739A CN 113012739 A CN113012739 A CN 113012739A CN 201911322465 A CN201911322465 A CN 201911322465A CN 113012739 A CN113012739 A CN 113012739A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
Abstract
A memory device includes a memory cell array, a first reference cell, a second reference cell, and a control unit. The memory cell array has a plurality of memory cells. The first reference cell provides a first reference current. The second reference unit provides a second reference current, wherein the current value of the first reference current is smaller than that of the second reference current. The control unit is coupled with the storage unit, the first reference unit and the second reference unit, and provides a first current to the storage unit during data writing operation, reads a second current generated by the storage unit in response to the first current, and selects and compares the second current with the first reference current or compares the second current with the second reference current according to the data writing state of the storage unit to determine whether the data writing of the data writing state is successful, thereby effectively increasing the reliability and accuracy of the memory.
Description
Technical Field
Embodiments of the present invention relate to a memory, and more particularly, to a memory device and an operating method thereof.
Background
Generally, after data is written into a memory cell of a memory, a current of the memory cell is read by a sensing circuit and compared with a preset current to determine whether the data is successfully written into the memory cell. However, when the sensing window formed by the current and the predetermined current is narrow, erroneous determination is easily caused, and the reliability of the memory cell is reduced.
To improve the reliability degradation caused by the narrow sensing window, a two-transistor two-resistor (2T2R) architecture can be used to store a single bit. Thus, the margin of the sensing window formed by the current of the memory cell and the reference current can be increased and the reliability of the memory cell can be improved, but the above design reduces the storage capacity of the memory. Therefore, there is still room for improvement in the design of the memory.
Disclosure of Invention
Embodiments of the present invention provide a memory device and an operating method thereof, so as to effectively increase the reliability and accuracy of memory verification.
The embodiment of the invention provides a memory device which comprises a memory cell array, a first reference unit, a second reference unit and a control unit. The memory cell array has a plurality of memory cells. The first reference cell provides a first reference current. The second reference unit provides a second reference current, wherein the current value of the first reference current is smaller than that of the second reference current. The control unit is coupled with the storage unit, the first reference unit and the second reference unit, provides a first current to the storage unit during data writing operation, reads a second current generated by the storage unit in response to the first current, and selects and compares the second current with the first reference current or compares the second current with the second reference current according to the data writing state of the storage unit to determine whether the data writing in the data writing state is successful or not.
An embodiment of the invention provides an operation method of a memory device, which includes the following steps. A memory cell array is provided having a plurality of memory cells. A first reference cell is provided that provides a first reference current. And providing a second reference unit which provides a second reference current, wherein the current value of the first reference current is smaller than that of the second reference current. In a data write operation, a first current is provided to a memory cell, and a second current generated by the memory cell in response to the first current is read. And selecting and comparing the second current with the first reference current or comparing the second current with the second reference current to determine whether the data writing in the data writing state is successful or not in the data writing state of the memory unit.
The memory device and the operation method thereof disclosed by the embodiment of the invention can select different reference currents according to the data writing state of the memory unit so as to determine whether the data writing in the data writing state is successful or not. Therefore, the reliability and the precision of the memory can be effectively improved.
Drawings
FIG. 1 is a diagram of a memory cell array according to an embodiment of the invention.
FIG. 2 is a diagram illustrating a memory cell, a first reference cell and a second reference cell according to an embodiment of the invention.
FIG. 3 is a diagram illustrating the sensing windows of the second current and the second reference current when the data writing state of the memory cell is at the low logic level according to an embodiment of the invention.
FIG. 4 is a diagram illustrating the sensing windows of the second current and the first reference current when the data writing state of the memory cell is at a high logic level according to an embodiment of the invention.
FIG. 5 is a schematic diagram of a memory cell array according to another embodiment of the invention.
FIG. 6 is a flow chart of a method of operating a memory device according to an embodiment of the invention.
FIG. 7 is a flow chart of a method of operating a memory device according to another embodiment of the invention.
Reference numerals:
100. 500: memory device
110: memory cell array
111_11 to 111_ MN: memory cell
120: first reference cell
130: second reference cell
140: control unit
511_1 to 511_ O: first sub-reference unit
521_1 to 521_ P: second sub-reference unit
I1: first current
I2: the second current
I _ HRS, I' _ HRS: a first reference current
I _ LRS, I' _ LRS: second reference current
R: resistance (RC)
T: transistor with a metal gate electrode
W1, W2, W3, W4: sensing window
S602 to S610, S702 to S704: step (ii) of
Detailed Description
In each of the embodiments listed below, the same or similar elements or components will be denoted by the same reference numerals.
FIG. 1 is a diagram of a memory device according to an embodiment of the invention. Referring to fig. 1, a memory device 100 includes a memory cell array 110, a first reference cell 120, a second reference cell 130, and a control unit 140.
The memory cell array 110 has a plurality of memory cells 111_ 11-111 _ MN, wherein N, M is a positive integer greater than 1. In addition, N and M may be the same or different. In the present embodiment, each of the memory cells 111_ 11-111 _ MN includes a resistor R and a transistor T, and the resistor R is coupled to the transistor T, as shown in FIG. 2.
The first reference cell 120 provides a first reference current I _ HRS. The second reference unit 130 provides a second reference current I _ LRS, wherein the current value of the first reference current I _ HRS is smaller than that of the second reference current I _ LRS. In the present embodiment, the first reference cell 120 and the second reference cell also include a resistor R and a transistor T, respectively, and the resistor R is coupled to the transistor T, as shown in fig. 2.
In addition, the first reference cell 120 and the second reference cell 130 are disposed at the side or the periphery of the memory cell array 110. Moreover, the position of the first reference unit 120 and the second reference unit 130 shown in fig. 1 is only an exemplary embodiment of the present invention, and is not limited to the embodiment of the present invention. The user can adjust the positions of the first reference cell 120 and the second reference cell 130 according to his/her needs, and the positions are located at the side or around the memory cell array 110. In addition, the first reference cell 120 and the second reference cell 130 can be disposed on the same side or different sides of the memory cell array 110. In the embodiment, the resistors R of the memory cells 111_ 11-111 _ MN, the first reference cell 120 and the second reference cell 130 are the same as the transistor T in size.
The control unit 140 is coupled to the memory units 111_11 to 111_ MN, the first reference unit 120 and the second reference unit 130. During a data write operation, the control unit 140 provides a first current I1 to a memory cell, such as the memory cell 111_ 11. Then, the control unit 140 reads the second current I2 generated by the memory cell 111_11 in response to the first current I1, and selects to compare the second current I2 with the first reference current I _ HRS or compare the second current I2 with the second reference current I _ LRS according to the data writing state of the memory cell 111_1 to determine whether the data writing in the data writing state is successful.
Further, when the data writing state of the memory cell 111_11 is high, it indicates that the written data is 1. Then, the control unit 140 selectively compares the second current I2 with the second reference current I _ LRS to determine whether the data writing in the data writing state is successful. For example, as shown in fig. 3, I2 is the second current, I _ LRS is the second reference current, and W1 is the sensing window (sensing window) between the second current I2 and the second reference current I _ LRS.
When the control unit 140 determines that the current value of the second current I2 is smaller than the current value of the second reference current I _ LRS, the control unit 140 determines that the data writing in the data writing state is successful, i.e. the written data in the memory cell 111_11 is exactly 1. When the control unit 140 determines that the current value of the second current I2 is not less than the current value of the second reference current I _ LRS, the control unit 140 determines that the data writing in the data writing state is not successful, i.e. the written data in the memory cell 111_11 is not 1. The data write operation of the remaining memory cells can refer to the data write operation of the memory cell 111_11, and therefore, the description thereof is omitted.
In some embodiments, the size of the transistor T of the second reference cell 130 can be set to be larger than the size of the transistors T of the memory cells 111_ 11-110 _ MN and the first reference cell 120, so that the switching capability of the transistor T of the second reference cell 130 is increased. Therefore, the current provided by the second reference cell 130 is changed from the second reference current I _ LRS to the second reference current I '_ LRS, and the length of the sensing window W2 between the second current I2 and the second reference current I' _ LRS is longer than the length of the sensing window W1 between the second current I2 and the second reference current I _ LRS, as shown in FIG. 3. Therefore, the reliability and the precision of the memory can be effectively improved.
On the other hand, when the data writing state of the memory cell 111_11 is the low logic level, it indicates that the written data is 0. Then, the control unit 140 selectively compares the second current I2 with the first reference current I _ HRS to determine whether the data writing in the data writing state is successful. For example, as shown in FIG. 4, I2 is the second current, I _ HRS is the first reference current, and W3 is the sensing window between the second current I2 and the first reference current I _ HRS.
When the control unit 140 determines that the current value of the second current I2 is greater than the current value of the first reference current I _ HRS, the control unit 140 determines that the data writing in the data writing state is successful, i.e. the written data in the memory cell 111_11 is indeed 0. When the control unit 140 determines that the current value of the second current I2 is not greater than the current value of the first reference current I _ HRS, the control unit 140 determines that the data writing in the data writing state is not successful, i.e. the data written in the memory cell 111_11 is not 0.
In some embodiments, the resistance R of the first reference cell 120 can be smaller than the resistance R of the memory cells 111_ 11-111 _ MN and the second reference cell 130. Therefore, the current provided by the first reference cell 120 is changed from the first reference current I _ HRS to the second reference current I '_ HRS, and the length of the sensing window W4 between the second current I2 and the first reference current I' _ HRS is longer than the length of the sensing window W3 between the second current I2 and the first reference current I _ HRS, as shown in FIG. 4. Therefore, the reliability and the precision of the memory can be effectively improved.
In addition, during a data reading operation, the control unit 140 reads the second current I2 corresponding to the memory cell (e.g., the memory cell 111_ 11). Then, the control unit 140 determines the logic level of the data writing state of the memory cell according to the second current I2, the first reference current I _ HRS and the second reference current I _ LRS.
In the present embodiment, the control unit 140 determines the logic level to be the high logic level or the low logic level according to a first difference (e.g., I2-I _ HRS) between the second current I2 and the first reference current I _ HRS and a second difference (e.g., I2-I _ LRS) between the second current I2 and the second reference current I _ LRS. Further, the control unit 140 may compare the absolute value of the first difference (e.g., | I2-I _ HRS |) and the absolute value of the second difference (e.g., | I2-I _ LRS |) to determine whether the logic level is the high logic level or the low logic level.
For example, when the absolute value of the first difference (e.g., | I2-I _ HRS |) is greater than the absolute value of the second difference (e.g., | I2-I _ LRS |), the control unit 140 determines that the data writing status of the memory cell 111_11 is at the low logic level.
When the absolute value of the first difference (e.g., | I2-I _ HRS |) is smaller than the absolute value of the second difference (e.g., | I2-I _ LRS |), the control unit 140 determines that the data writing status of the memory cell 111_11 is at a high logic level.
That is, when a read operation is performed on the memory cell, the control unit 140 can know the data writing state of the memory cell in the above-described manner. Thus, the convenience in use can be increased.
FIG. 5 is a diagram of a memory device according to another embodiment of the invention. Referring to fig. 5, the memory device 500 includes a memory cell array 110, a first reference cell 120, a second reference cell 130, and a control unit 140. The memory cell array 110 and the control unit 140 of fig. 5 are the same as or similar to the memory cell array 110 and the control unit 140 of fig. 1, and reference may be made to the description of the embodiment of fig. 1, so that no further description is provided herein.
In this embodiment, the first reference cell 120 may include a plurality of first sub-reference cells 511_1 to 511_ O, and provide a plurality of first sub-reference currents, where O is a positive integer greater than 1. In addition, the first reference unit 120 uses the median or the average of the first sub-reference currents as the current value of the first reference current I _ HRS.
The second reference cell 130 may include a plurality of second sub-reference cells 521_ P providing a plurality of second sub-reference currents, where P is a positive integer greater than 1. In addition, the second reference unit 130 uses the median or the average of the second sub-reference currents as the current value of the second reference current I _ LRS.
In the present embodiment, the number of the first sub-reference cells 511_1 to 511_ O and the second sub-reference cells 521_ P varies according to the size of the memory cell array 110. In addition, the numbers of the first sub-reference cells 511_1 to 511_ O and the second sub-reference cells 521_ P are the same or different, i.e., O and P may be the same or different.
In view of the foregoing description, the present invention further provides a method for operating a memory device. FIG. 6 is a flow chart of a method of operating a memory device according to an embodiment of the invention. In step S602, a memory cell array having a plurality of memory cells is provided. In step S604, a first reference cell is provided, which provides a first reference current. In step S606, a second reference unit is provided, which provides a second reference current, wherein the current value of the first reference current is smaller than the current value of the second reference current.
In step S608, a first current is provided to a memory cell during a data write operation, and a second current generated by the memory cell in response to the first current is read. In step S610, according to the data writing state of the memory cell, the second current and the first reference current are selectively compared, or the second current and the second reference current are compared, so as to determine whether the data writing in the data writing state is successful.
Further, step S610 includes the following steps. When the data writing state of the memory cell is at a low logic level, the second current and the first reference current are selected and compared to determine whether the data writing in the data writing state is successful. When the data writing state of the memory cell is at a high logic level, the second current and the second reference current are selected and compared to determine whether the data writing in the data writing state is successful. In addition, the first reference unit comprises a plurality of first sub-reference units for providing a plurality of first sub-reference currents, the first reference unit uses the median or the average value of the first sub-reference currents as the current value of the first reference current, the second reference unit comprises a plurality of second sub-reference units for providing a plurality of second sub-reference currents, and the second reference unit uses the median or the average value of the second sub-reference currents as the current value of the second reference current.
FIG. 7 is a flow chart of a method of operating a memory device according to another embodiment of the invention. In step S702, a second current corresponding to the memory cell is read during a data read operation. In step S704, the logic level of the data writing state of the memory cell is determined according to the second current, the first reference current and the second reference current. Further, step S704 includes the following steps. And judging the data writing state of the memory unit to be a high logic level or a low logic level according to the first difference value of the second current and the first reference current and the absolute value of the second difference value of the second current and the second reference current. When the absolute value of the first difference is larger than the absolute value of the second difference, the memory cell is judged to be at a low logic level. On the other hand, when the absolute value of the first difference is smaller than the absolute value of the second difference, the memory cell is determined to be at the low logic level.
In summary, in the memory device and the operating method thereof disclosed in the embodiments of the invention, the first reference cell provides the first reference current and the second reference cell provides the second reference current, wherein the current value of the first reference current is smaller than the current value of the second reference current. During data writing operation, the control unit can select and compare the second current with the first reference current or compare the second current with the second reference current according to the data writing state of the memory unit so as to determine whether the data writing in the data writing state is successful or not. Therefore, the reliability and the precision of the memory can be effectively improved. In addition, by changing the size of the resistor of the first reference unit and/or the size of the transistor of the second reference unit, the length of the sensing window can be increased, and the reliability and the precision of the memory can be further increased.
In addition, during the data reading operation, the control unit reads the second current corresponding to the memory unit and judges the logic level of the data writing state of the memory unit according to the second current, the first reference current and the second reference current. Therefore, after the data is written into the memory cell, the logic level of the data writing state of the memory cell can be effectively known, so that the convenience in use is improved.
Although the present invention has been described with reference to particular embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (14)
1. A memory device, comprising:
a memory cell array having a plurality of memory cells;
a first reference unit for providing a first reference current;
a second reference unit for providing a second reference current, wherein the current value of the first reference current is smaller than that of the second reference current; and
the control unit is coupled with the storage unit, the first reference unit and the second reference unit, and provides a first current to the storage unit during a data writing operation, reads a second current generated by the storage unit in response to the first current, and selectively compares the second current with the first reference current or compares the second current with the second reference current according to a data writing state of the storage unit to determine whether data writing in the data writing state is successful or not.
2. The memory device according to claim 1, wherein the control unit selectively compares the second current with the first reference current to determine whether the data writing of the data writing state is successful when the data writing state of the memory cell is a low logic level, and selectively compares the second current with the second reference current to determine whether the data writing of the data writing state is successful when the data writing state of the memory cell is a high logic level.
3. The memory device of claim 1, wherein the first reference cell and the second reference cell are disposed at sides or around the memory cell array.
4. The memory device of claim 1, wherein the first reference cell comprises a plurality of first sub-reference cells providing a plurality of first sub-reference currents, and the first reference cell has a median or an average of the first sub-reference currents as the current value of the first reference current, and the second reference cell comprises a plurality of second sub-reference cells providing a plurality of second sub-reference currents, and the second reference cell has a median or an average of the second sub-reference currents as the current value of the second reference current.
5. The memory device of claim 1, wherein the memory cell, the first reference cell, and the second reference cell each comprise a resistor and a transistor, and wherein the resistor and the transistor are coupled.
6. The memory device of claim 5, wherein a size of the resistance of the first reference cell is smaller than a size of the resistance of the memory cell and the second reference cell.
7. The memory device of claim 5, wherein a size of the transistor of the second reference cell is larger than a size of the transistors of the memory cell and the first reference cell.
8. The memory device according to claim 1, wherein in a data read operation, the control unit reads the second current corresponding to the memory cell and determines a logic level of the data write state of the memory cell according to the second current, the first reference current and the second reference current.
9. The memory device according to claim 8, wherein the control unit determines the logic level to be a high logic level or a low logic level according to a first difference between the second current and the first reference current and a second difference between the second current and the second reference current.
10. A method of operating a memory device, comprising:
providing a memory cell array having a plurality of memory cells;
providing a first reference unit, which provides a first reference current;
providing a second reference unit, which provides a second reference current, wherein the current value of the first reference current is smaller than that of the second reference current;
providing a first current to a memory cell during a data write operation, and reading a second current generated by the memory cell in response to the first current; and
and selecting and comparing the second current with the first reference current or comparing the second current with the second reference current according to a data writing state of the memory unit so as to determine whether data writing in the data writing state is successful or not.
11. The method of claim 10, wherein the step of selectively comparing the second current with the first reference current or comparing the second current with the second reference current to determine whether the data write of the data write state is successful according to a data write state of the memory cell comprises:
when the data writing state of the memory cell is a low logic level, selectively comparing the second current with the first reference current to determine whether the data writing in the data writing state is successful; and
when the data writing state of the memory cell is a high logic level, selectively comparing the second current with the second reference current to determine whether the data writing of the data writing state is successful.
12. The method of claim 10, wherein the first reference cell comprises a plurality of first sub-reference cells providing a plurality of first sub-reference currents, and the first reference cell has a median or mean of the first sub-reference currents as the current value of the first reference current, and the second reference cell comprises a plurality of second sub-reference cells providing a plurality of second sub-reference currents, and the second reference cell has a median or mean of the second sub-reference currents as the current value of the second reference current.
13. The method of claim 10, further comprising:
reading the second current corresponding to the memory cell during a data reading operation; and
and judging a logic level of the data writing state of the memory unit according to the second current, the first reference current and the second reference current.
14. The method of claim 13, wherein the step of determining the logic level of the data write state of the memory cell according to the second current, the first reference current and the second reference current comprises:
and judging the logic level to be a high logic level or a low logic level according to a first difference value of the second current and the first reference current and a second difference value of the second current and the second reference current.
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| US20110058414A1 (en) * | 2009-09-09 | 2011-03-10 | Macronix International Co., Ltd. | Memory with multiple reference cells |
| US20140133214A1 (en) * | 2012-11-14 | 2014-05-15 | SK Hynix Inc. | Resistive memory device and method for driving the same |
| US20140185361A1 (en) * | 2012-12-27 | 2014-07-03 | Eun Cho Oh | Non-volatile random access memory device and data read method thereof |
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