CN113012739B - Memory device and operation method thereof - Google Patents
Memory device and operation method thereof Download PDFInfo
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- CN113012739B CN113012739B CN201911322465.8A CN201911322465A CN113012739B CN 113012739 B CN113012739 B CN 113012739B CN 201911322465 A CN201911322465 A CN 201911322465A CN 113012739 B CN113012739 B CN 113012739B
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- 238000000034 method Methods 0.000 title claims description 14
- 230000004044 response Effects 0.000 claims abstract description 7
- 210000004027 cell Anatomy 0.000 claims 40
- 210000000352 storage cell Anatomy 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 7
- 238000011017 operating method Methods 0.000 description 2
- 238000012790 confirmation Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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Abstract
A memory device includes a memory cell array, a first reference cell, a second reference cell, and a control cell. The memory cell array has a plurality of memory cells. The first reference unit provides a first reference current. The second reference unit provides a second reference current, wherein the current value of the first reference current is smaller than the current value of the second reference current. The control unit is coupled to the memory unit, the first reference unit and the second reference unit, and is used for providing a first current to the memory unit and reading a second current generated by the memory unit in response to the first current during a data writing operation, and selectively comparing the second current with the first reference current or the second current with the second reference current according to a data writing state of the memory unit so as to determine whether the data writing of the data writing state is successful or not, thereby effectively increasing the reliability and the accuracy of the confirmed memory.
Description
Technical Field
The present invention relates to a memory, and more particularly, to a memory device and an operating method thereof.
Background
Generally, after writing data into a memory cell of the memory, the sensing circuit can read the current of the memory cell and compare the current with a preset current to determine whether the writing data into the memory cell is successful. However, when the sensing window formed by the current and the preset current is narrower, erroneous judgment is easily caused, and the reliability of the confirmed memory cell is reduced.
To improve the situation that the narrower sensing window leads to the reduced reliability, a two-transistor (2T 2R) architecture may be used to store a single bit. Thus, the margin of the sensing window formed by the current of the memory cell and the reference current can be increased and the reliability of the memory cell can be improved, but the above design can reduce the storage capacity of the memory. Therefore, there is still room for improvement in the design of the memory.
Disclosure of Invention
The embodiment of the invention provides a memory device and an operation method thereof, which are used for effectively increasing the reliability and the accuracy of a confirmation memory.
The embodiment of the invention provides a memory device, which comprises a memory cell array, a first reference cell, a second reference cell and a control unit. The memory cell array has a plurality of memory cells. The first reference unit provides a first reference current. The second reference unit provides a second reference current, wherein the current value of the first reference current is smaller than the current value of the second reference current. The control unit is coupled to the memory unit, the first reference unit and the second reference unit, and is used for providing a first current to the memory unit and reading a second current generated by the memory unit in response to the first current during a data writing operation, and selectively comparing the second current with the first reference current or comparing the second current with the second reference current according to a data writing state of the memory unit so as to determine whether the data writing of the data writing state is successful.
The embodiment of the invention provides an operation method of a memory device, which comprises the following steps. A memory cell array is provided having a plurality of memory cells. A first reference cell is provided that provides a first reference current. A second reference unit is provided which provides a second reference current, wherein the current value of the first reference current is smaller than the current value of the second reference current. During a data writing operation, a first current is provided to a memory cell, and a second current generated by the memory cell in response to the first current is read. And the data writing state of the memory cell is selected to compare the second current with the first reference current or the second current with the second reference current so as to determine whether the data writing in the data writing state is successful or not.
According to the memory device and the operation method thereof disclosed by the embodiment of the invention, different reference currents can be selected according to the data writing state of the memory cell so as to determine whether the data writing of the data writing state is successful or not. Therefore, the reliability and the precision of the memory can be effectively increased.
Drawings
FIG. 1 is a schematic diagram of a memory cell array according to an embodiment of the invention.
FIG. 2 is a schematic diagram of a memory cell, a first reference cell and a second reference cell according to an embodiment of the invention.
FIG. 3 is a diagram illustrating a sensing window of a second current and a second reference current when a data writing state of a memory cell is a low logic level according to an embodiment of the invention.
FIG. 4 is a diagram of a sensing window of a second current and a first reference current when a data writing state of a memory cell is a high logic level according to an embodiment of the invention.
FIG. 5 is a schematic diagram of a memory cell array according to another embodiment of the invention.
FIG. 6 is a flowchart of a method of operating a memory device according to an embodiment of the invention.
FIG. 7 is a flowchart of a method of operating a memory device according to another embodiment of the invention.
Reference numerals:
100. 500: memory device
110: memory cell array
111_11 to 111_mn: memory cell
120: first reference unit
130: second reference unit
140: control unit
511_1 to 511_o: first sub-reference unit
521_1 to 521_P: second sub-reference unit
I1: first current
I2: second current
I_hrs, I' _hrs: first reference current
I_lrs, I' _lrs: second reference current
R: resistor
T: transistor with a high-voltage power supply
W1, W2, W3, W4: sensing window
S602 to S610, S702 to S704: step (a)
Detailed Description
In the various embodiments listed below, the same or similar elements or components will be denoted by the same reference numerals.
FIG. 1 is a schematic diagram of a memory device according to an embodiment of the invention. Referring to fig. 1, the memory device 100 includes a memory cell array 110, a first reference cell 120, a second reference cell 130, and a control unit 140.
The memory cell array 110 has a plurality of memory cells 111_11 to 111_mn, wherein N, M is a positive integer greater than 1. In addition, N and M may be the same or different. In the present embodiment, the memory cells 111_11 to 111_mn each include a resistor R and a transistor T, and the resistor R is coupled to the transistor T as shown in fig. 2.
The first reference unit 120 provides a first reference current i_hrs. The second reference unit 130 provides a second reference current i_lrs, wherein a current value of the first reference current i_hrs is smaller than a current value of the second reference current i_lrs. In this embodiment, the first reference cell 120 and the second reference cell also each include a resistor R and a transistor T, and the resistor R is coupled to the transistor T, as shown in fig. 2.
In addition, the first reference unit 120 and the second reference unit 130 are disposed at the side or around the memory cell array 110. Moreover, the setting positions of the first reference unit 120 and the second reference unit 130 shown in fig. 1 are only one embodiment example of the present invention, and are not intended to limit the embodiments of the present invention. The user can also adjust the setting positions of the first reference unit 120 and the second reference unit 130 according to the requirements, and the setting positions are located at the side or around the memory cell array 110. In addition, the first reference unit 120 and the second reference unit 130 may be disposed on the same side or different sides of the memory cell array 110. In the present embodiment, the resistances R of the memory cells 111_11 to 111_mn, the first reference cell 120, and the second reference cell 130 are the same as the size of the transistor T.
The control unit 140 is coupled to the memory units 111_11 to 111_mn, the first reference unit 120 and the second reference unit 130. During a data writing operation, the control unit 140 provides the first current I1 to a memory cell, such as the memory cell 111_11. Next, the control unit 140 reads the second current I2 generated by the memory cell 111_11 in response to the first current I1, and selectively compares the second current I2 with the first reference current i_hrs or the second current I2 with the second reference current i_lrs according to the data writing state of the memory cell 111_1 to determine whether the data writing of the data writing state is successful.
Further, when the data writing state of the memory cell 111_11 is at the high logic level, it indicates that the writing data is 1. Next, the control unit 140 selectively compares the second current I2 with the second reference current i_lrs to determine whether the data writing in the data writing state is successful. For example, as shown in fig. 3, I2 is the second current, i_lrs is the second reference current, and W1 is the sensing window (sensing window) between the second current I2 and the second reference current i_lrs.
When the control unit 140 determines that the current value of the second current I2 is smaller than the current value of the second reference current i_lrs, the control unit 140 determines that the data writing in the data writing state is successful, that is, the writing data of the memory cell 111_11 is indeed 1. When the control unit 140 determines that the current value of the second current I2 is not smaller than the current value of the second reference current i_lrs, the control unit 140 determines that the data writing in the data writing state is unsuccessful, that is, the writing data of the memory cell 111_11 is not 1. The data writing operation of the remaining memory cells can refer to the data writing operation of the memory cell 111_11, and thus will not be described herein.
In some embodiments, the size of the transistor T of the second reference cell 130 may be set larger than the sizes of the memory cells 111_11 to 110_mn and the transistor T of the first reference cell 120, so that the switching capability of the transistor T of the second reference cell 130 is increased. Therefore, the current provided by the second reference unit 130 is changed from the second reference current i_lrs to the second reference current I '_lrs, and the length of the sensing window W2 between the second current I2 and the second reference current I' _lrs is longer than the length of the sensing window W1 between the second current I2 and the second reference current i_lrs, as shown in fig. 3. Therefore, the reliability and the precision of the memory can be effectively increased.
On the other hand, when the data writing state of the memory cell 111_11 is the low logic level, it means that the writing data is 0. Next, the control unit 140 selectively compares the second current I2 with the first reference current i_hrs to determine whether the data writing in the data writing state is successful. For example, as shown in fig. 4, I2 is the second current, i_hrs is the first reference current, and W3 is the sensing window between the second current I2 and the first reference current i_hrs.
When the control unit 140 determines that the current value of the second current I2 is greater than the current value of the first reference current i_hrs, the control unit 140 determines that the data writing in the data writing state is successful, that is, the writing data of the memory cell 111_11 is indeed 0. When the control unit 140 determines that the current value of the second current I2 is not greater than the current value of the first reference current i_hrs, the control unit 140 determines that the data writing in the data writing state is unsuccessful, that is, the writing data of the memory cell 111_11 is not 0.
In some embodiments, the resistance R of the first reference cell 120 may be smaller than the resistances R of the memory cells 111_11-111_MN and the second reference cell 130. Therefore, the current provided by the first reference cell 120 is changed from the first reference current i_hrs to the second reference current I '_hrs, and the length of the sensing window W4 between the second current I2 and the first reference current I' _hrs is longer than the length of the sensing window W3 between the second current I2 and the first reference current i_hrs, as shown in fig. 4. Therefore, the reliability and the precision of the memory can be more effectively increased.
In addition, during the data reading operation, the control unit 140 reads the second current I2 corresponding to the memory cell (e.g., the memory cell 111_11). Next, the control unit 140 determines the logic level of the data writing state of the memory cell according to the second current I2, the first reference current i_hrs and the second reference current i_lrs.
In the present embodiment, the control unit 140 determines the logic level to be a high logic level or a low logic level according to a first difference (e.g., I2-i_hrs) between the second current I2 and the first reference current i_hrs and a second difference (e.g., I2-i_lrs) between the second current I2 and the second reference current i_lrs. Further, the control unit 140 may compare the absolute value of the first difference (e.g., |i2-i_hrs|) with the absolute value of the second difference (e.g., |i2-i_lrs|), and determine whether the logic level is a high logic level or a low logic level.
For example, when the absolute value (e.g., |i2-i_hrs|) of the first difference is greater than the absolute value (e.g., |i2-i_lrs|) of the second difference, the control unit 140 determines the data writing state of the memory unit 111_11 to be the low logic level.
When the absolute value (e.g., |i2-i_hrs|) of the first difference is smaller than the absolute value (e.g., |i2-i_lrs|) of the second difference, the control unit 140 determines the data writing state of the memory cell 111_11 to be a high logic level.
That is, when a read operation is performed on the memory cell, the control unit 140 can learn the data writing state of the memory cell in the above-described manner. In this way, the convenience in use can be increased.
FIG. 5 is a schematic diagram of a memory device according to another embodiment of the invention. Referring to fig. 5, the memory device 500 includes a memory cell array 110, a first reference cell 120, a second reference cell 130 and a control unit 140. The memory cell array 110 and the control unit 140 of fig. 5 are the same as or similar to the memory cell array 110 and the control unit 140 of fig. 1, and reference is made to the description of the embodiment of fig. 1, so that the description thereof is omitted here.
In the present embodiment, the first reference unit 120 may include a plurality of first sub-reference units 511_1 to 511_o, which provide a plurality of first sub-reference currents, wherein O is a positive integer greater than 1. In addition, the first reference unit 120 uses the median or average value of the first sub-reference current as the current value of the first reference current i_hrs.
The second reference unit 130 may include a plurality of second sub-reference units 521_521_p providing a plurality of second sub-reference currents, where P is a positive integer greater than 1. In addition, the second reference unit 130 uses the median or average value of the second sub-reference current as the current value of the second reference current i_lrs.
In the present embodiment, the number of the first sub-reference units 511_1 to 511_o and the second sub-reference units 521_521_p varies according to the size of the memory cell array 110. In addition, the first sub-reference units 511_1 to 511_o and the second sub-reference units 521_521_p may be the same or different in number, i.e., O and P may be the same or different.
By the above description of the embodiments, the present invention further provides a method for operating a memory device. FIG. 6 is a flowchart of a method of operating a memory device according to an embodiment of the invention. In step S602, a memory cell array having a plurality of memory cells is provided. In step S604, a first reference cell is provided that provides a first reference current. In step S606, a second reference unit is provided, which provides a second reference current, wherein the current value of the first reference current is smaller than the current value of the second reference current.
In step S608, a first current is provided to a memory cell during a data writing operation, and a second current generated by the memory cell in response to the first current is read. In step S610, the second current is selected to be compared with the first reference current or the second current is selected to be compared with the second reference current according to the data writing state of the memory cell, so as to determine whether the data writing in the data writing state is successful.
Further, step S610 includes the following steps. When the data writing state of the memory cell is a low logic level, the second current is selected and compared with the first reference current to determine whether the data writing in the data writing state is successful. When the data writing state of the memory cell is at the high logic level, the second current is selected and compared with the second reference current to determine whether the data writing in the data writing state is successful. In addition, the first reference unit comprises a plurality of first sub-reference units for providing a plurality of first sub-reference currents, wherein the first reference unit takes the median or average value of the first sub-reference currents as the current value of the first reference current, and the second reference unit comprises a plurality of second sub-reference units for providing a plurality of second sub-reference currents, and the second reference unit takes the median or average value of the second sub-reference currents as the current value of the second reference current.
FIG. 7 is a flowchart of a method of operating a memory device according to another embodiment of the invention. In step S702, during a data reading operation, a second current corresponding to the memory cell is read. In step S704, the logic level of the data writing state of the memory cell is determined according to the second current, the first reference current and the second reference current. Further, step S704 includes the following steps. And judging the data writing state of the memory cell to be a high logic level or a low logic level according to the first difference value between the second current and the first reference current and the absolute value of the second difference value between the second current and the second reference current. When the absolute value of the first difference is larger than that of the second difference, the storage unit is judged to be at a low logic level. On the other hand, when the absolute value of the first difference is smaller than the absolute value of the second difference, the memory cell is determined to be at the low logic level.
In summary, according to the memory device and the operating method thereof disclosed in the embodiments of the present invention, the first reference unit provides the first reference current and the second reference unit provides the second reference current, wherein the current value of the first reference current is smaller than the current value of the second reference current. During the data writing operation, the control unit can select to compare the second current with the first reference current or compare the second current with the second reference current according to the data writing state of the memory unit, so as to determine whether the data writing in the data writing state is successful. Therefore, the reliability and the precision of the memory can be effectively increased. In addition, by changing the size of the resistor of the first reference unit and/or the size of the transistor of the second reference unit, the length of the sensing window can be increased, and the reliability and the accuracy of the memory can be further improved.
In addition, during the data reading operation, the control unit reads the second current corresponding to the memory cell, and determines the logic level of the data writing state of the memory cell according to the second current, the first reference current and the second reference current. Therefore, after the data is written into the memory cell, the logic level of the data writing state of the memory cell can be effectively known, so that the convenience in use is improved.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but may be modified or altered somewhat by persons skilled in the art without departing from the spirit and scope of the invention.
Claims (12)
1. A memory device, comprising:
a memory cell array having a plurality of memory cells;
a first reference unit for providing a first reference current;
a second reference unit for providing a second reference current, wherein the current value of the first reference current is smaller than that of the second reference current; and
the control unit is coupled with the storage unit, the first reference unit and the second reference unit, provides a first current to the storage unit during a data writing operation, reads a second current generated by the storage unit in response to the first current, and selectively compares the second current with the first reference current or the second current with the second reference current according to a data writing state of the storage unit so as to determine whether the data writing of the data writing state is successful;
when the data writing state of the memory cell is a low logic level, the control unit selectively compares the second current with the first reference current to determine whether the data writing of the data writing state is successful, and when the data writing state of the memory cell is a high logic level, the control unit selectively compares the second current with the second reference current to determine whether the data writing of the data writing state is successful.
2. The memory device of claim 1, wherein the first reference cell and the second reference cell are disposed at sides or around the memory cell array.
3. The memory device of claim 1, wherein the first reference cell comprises a plurality of first sub-reference cells providing a plurality of first sub-reference currents, the first reference cell having a median or an average of the first sub-reference currents as the current value of the first reference current, and the second reference cell comprises a plurality of second sub-reference cells providing a plurality of second sub-reference currents, the second reference cell having a median or an average of the second sub-reference currents as the current value of the second reference current.
4. The memory device of claim 1, wherein the memory cell, the first reference cell, and the second reference cell each comprise a resistor and a transistor, and the resistor is coupled to the transistor.
5. The memory device of claim 4, wherein a size of the resistance of the first reference cell is smaller than a size of the resistances of the memory cell and the second reference cell.
6. The memory device of claim 4, wherein a size of the transistor of the second reference cell is larger than a size of the transistors of the storage cell and the first reference cell.
7. The memory device of claim 1, wherein the control unit reads the second current corresponding to the memory cell during a data read operation, and determines a logic level of the data writing state of the memory cell according to the second current, the first reference current, and the second reference current.
8. The memory device of claim 7, wherein the control unit determines the logic level to be a high logic level or a low logic level according to a first difference between the second current and the first reference current and a second difference between the second current and the second reference current.
9. A method of operating a memory device, comprising:
providing a memory cell array with a plurality of memory cells;
providing a first reference unit which provides a first reference current;
providing a second reference unit, which provides a second reference current, wherein the current value of the first reference current is smaller than that of the second reference current;
providing a first current to a memory cell during a data writing operation, and reading a second current generated by the memory cell in response to the first current; and
selecting to compare the second current with the first reference current or the second current with the second reference current according to a data writing state of the memory cell, so as to determine whether a data writing of the data writing state is successful;
the step of determining whether the data writing in the data writing state is successful by selecting and comparing the second current with the first reference current or comparing the second current with the second reference current according to a data writing state of the memory cell comprises the following steps:
when the data writing state of the memory cell is a low logic level, selecting and comparing the second current with the first reference current to determine whether the data writing of the data writing state is successful; and
when the data writing state of the memory cell is a high logic level, the second current and the second reference current are selected and compared to determine whether the data writing of the data writing state is successful.
10. The method of claim 9, wherein the first reference cell comprises a plurality of first sub-reference cells providing a plurality of first sub-reference currents, the first reference cell having a median or an average of the first sub-reference currents as the current value of the first reference current, and the second reference cell comprises a plurality of second sub-reference cells providing a plurality of second sub-reference currents, the second reference cell having a median or an average of the second sub-reference currents as the current value of the second reference current.
11. The method of operation of a memory device of claim 9, further comprising:
reading the second current corresponding to the memory cell during a data reading operation; and
and judging a logic level of the data writing state of the memory cell according to the second current, the first reference current and the second reference current.
12. The method of claim 11, wherein determining the logic level of the data writing state of the memory cell according to the second current, the first reference current and the second reference current comprises:
and judging the logic level as a high logic level or a low logic level according to a first difference value between the second current and the first reference current and a second difference value between the second current and the second reference current.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9508435B1 (en) * | 2015-06-17 | 2016-11-29 | Winbond Electronics Corp. | Writing method for resistive memory apparatus |
| CN106373606A (en) * | 2015-07-21 | 2017-02-01 | 华邦电子股份有限公司 | Resistive memory apparatus and writing method thereof |
Family Cites Families (3)
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| US8189357B2 (en) * | 2009-09-09 | 2012-05-29 | Macronix International Co., Ltd. | Memory with multiple reference cells |
| KR102115440B1 (en) * | 2012-11-14 | 2020-05-27 | 에스케이하이닉스 주식회사 | Nonvolatile memory device and method of driving the same |
| KR102060488B1 (en) * | 2012-12-27 | 2019-12-30 | 삼성전자주식회사 | Non-volatile random access memory device and data read method thereof |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US9508435B1 (en) * | 2015-06-17 | 2016-11-29 | Winbond Electronics Corp. | Writing method for resistive memory apparatus |
| CN106373606A (en) * | 2015-07-21 | 2017-02-01 | 华邦电子股份有限公司 | Resistive memory apparatus and writing method thereof |
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