TWI715329B - Memory device and operation method thereof - Google Patents

Memory device and operation method thereof Download PDF

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TWI715329B
TWI715329B TW108144247A TW108144247A TWI715329B TW I715329 B TWI715329 B TW I715329B TW 108144247 A TW108144247 A TW 108144247A TW 108144247 A TW108144247 A TW 108144247A TW I715329 B TWI715329 B TW I715329B
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data writing
memory
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reference current
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TW202123227A (en
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劉家銘
林銘哲
吳伯倫
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華邦電子股份有限公司
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Abstract

A memory device includes a memory array, a first reference unit, a second reference unit and a control unit. The memory array includes a plurality of memory cells. The first reference unit provides a first reference current. The second reference unit provides a second reference current, wherein a current value of the first reference current is less than a current value of the second reference current. The control unit is coupled to the memory cells, the first reference unit and the second reference unit. In a data writing operation, the control provides a first current to a memory cell, reads a second current generated by the memory cell in response to the first current, and selects to compare the second current with the first reference current or compare the second current with the second reference current according to a data writing state of the memory cell, so as to determine whether a data writing of the data writing state is successful.

Description

記憶體裝置與其操作方法Memory device and operation method thereof

本發明實施例關於一種記憶體，特別是關於一種記憶體裝置與其操作方法。The embodiment of the present invention relates to a memory, and particularly relates to a memory device and an operating method thereof.

一般來說，在記憶體之記憶體單元寫入資料後，可以透過感測電路讀取記憶體單元的電流，並將上述電流與一預設電流進行比對，以確認記憶體單元的寫入資料是否成功。然而，當上述電流與預設電流所形成的感測窗較窄，容易造成誤判的情況發生，而降低確認記憶體單元的可靠度。Generally speaking, after data is written in the memory cell of the memory, the current of the memory cell can be read through the sensing circuit, and the current can be compared with a preset current to confirm the writing of the memory cell Whether the data is successful. However, when the sensing window formed by the above current and the preset current is narrow, it is easy to cause misjudgment and reduce the reliability of confirming the memory cell.

為了改善上述感測窗較窄導致可靠度降低的情況，可以使用二電晶體二電阻(2T2R)的架構來儲存單一位元。如此，可以增加記憶體單元之電流與參考電流所形成的感測窗的裕度並改善記憶體單元的可靠度，但是上述設計會降低記憶體的儲存容量。因此，記憶體的設計上仍有改善的空間。In order to improve the above-mentioned situation of reduced reliability due to the narrow sensing window, a two-transistor two-resistor (2T2R) architecture can be used to store a single bit. In this way, the margin of the sensing window formed by the current of the memory cell and the reference current can be increased and the reliability of the memory cell can be improved. However, the above design will reduce the storage capacity of the memory. Therefore, there is still room for improvement in the design of the memory.

本發明實施例提供一種記憶體裝置與其操作方法，藉以有效地增加確認記憶體的可靠度及精準度。The embodiment of the present invention provides a memory device and an operating method thereof, so as to effectively increase the reliability and accuracy of the memory confirmation.

本發明實施例提供一種記憶體裝置，包括記憶體陣列、第一參考單元、第二參考單元與控制單元。記憶體陣列具有多個記憶體單元。第一參考單元提供第一參考電流。第二參考單元提供第二參考電流，其中第一參考電流的電流值小於第二參考電流的電流值。控制單元耦接記憶體單元、第一參考單元與第二參考單元，於資料寫入操作時，控制單元提供第一電流至一記憶體單元，並讀取記憶體單元回應於第一電流產生的第二電流，且依據記憶單元的資料寫入狀態，選擇比對第二電流與第一參考電流，或是比對第二電流與第二參考電流，以確定資料寫入狀態的資料寫入是否成功。An embodiment of the present invention provides a memory device including a memory array, a first reference unit, a second reference unit, and a control unit. The memory array has a plurality of memory cells. The first reference unit provides a first reference current. The second reference unit provides a second reference current, wherein the current value of the first reference current is smaller than the current value of the second reference current. The control unit is coupled to the memory unit, the first reference unit and the second reference unit. During a data writing operation, the control unit provides a first current to a memory unit, and reads the memory unit in response to the first current. The second current, and according to the data write state of the memory cell, select whether to compare the second current with the first reference current, or compare the second current with the second reference current to determine whether the data is written in the data write state success.

本發明實施例提供一種記憶體裝置的操作方法，包括。提供記憶體陣列，其具有多個記憶體單元。提供第一參考單元，其提供第一參考電流。提供第二參考單元，其提供第二參考電流，其中第一參考電流的電流值小於第二參考電流的電流值。於資料寫入操作時，提供第一電流至一記憶體單元，並讀取記憶體單元回應於第一電流產生的第二電流。記憶體單元的資料寫入狀態，選擇比對第二電流與第一參考電流，或是比對第二電流與第二參考電流，以確定資料寫入狀態的資料寫入是否成功。The embodiment of the present invention provides an operating method of a memory device, including. A memory array is provided, which has a plurality of memory cells. A first reference unit is provided, which provides a first reference current. A second reference unit is provided, which provides a second reference current, wherein the current value of the first reference current is smaller than the current value of the second reference current. During the data writing operation, a first current is provided to a memory cell, and the second current generated by the memory cell in response to the first current is read. The data writing state of the memory cell is selected to compare the second current with the first reference current or compare the second current with the second reference current to determine whether the data writing in the data writing state is successful.

本發明實施例所揭露之記憶體裝置與其操作方法，可依據記憶單元的資料寫入狀態，選擇不同的參考電流以確定資料寫入狀態的資料寫入是否成功。如此一來，可以有效地增加記憶體的可靠度及精準度。In the memory device and its operating method disclosed in the embodiments of the present invention, different reference currents can be selected according to the data writing state of the memory cell to determine whether the data writing in the data writing state is successful. In this way, the reliability and accuracy of the memory can be effectively increased.

在以下所列舉的各實施例中，將以相同的標號代表相同或相似的元件或組件。In the embodiments listed below, the same reference numerals will be used to represent the same or similar elements or components.

第1圖為依據本發明一實施例之記憶體裝置的示意圖。請參考第1圖，記憶體裝置100包括記憶體陣列110、第一參考單元120、第二參考單元130與控制單元140。FIG. 1 is a schematic diagram of a memory device according to an embodiment of the invention. Please refer to FIG. 1, the memory device 100 includes a memory array 110, a first reference unit 120, a second reference unit 130 and a control unit 140.

記憶體陣列110具有多個記憶體單元111_11~111_MN，其中N、M為大於1的正整數。另外，N與M可為相同或不同。在本實施例中，記憶體單元111_11~111_MN各自包括電阻R與電晶體T，且電阻R與電晶體T耦接，如第2圖所示。The memory array 110 has a plurality of memory cells 111_11 to 111_MN, where N and M are positive integers greater than one. In addition, N and M may be the same or different. In this embodiment, the memory cells 111_11 to 111_MN each include a resistor R and a transistor T, and the resistor R is coupled to the transistor T, as shown in FIG. 2.

第一參考單元120提供第一參考電流I_HRS。第二參考單元130提供第二參考電流I_LRS，其中第一參考電流I_HRS的電流值小於第二參考電流I_LRS的電流值。在本實施例中，第一參考單元120與第二參考單元也各自包括電阻R與電晶體T，且電阻R與電晶體T耦接，如第2圖所示。The first reference unit 120 provides a first reference current I_HRS. The second reference unit 130 provides a second reference current I_LRS, wherein the current value of the first reference current I_HRS is smaller than the current value of the second reference current I_LRS. In this embodiment, the first reference unit 120 and the second reference unit also each include a resistor R and a transistor T, and the resistor R is coupled to the transistor T, as shown in FIG. 2.

另外，第一參考單元120與第二參考單元130設置於記憶體陣列110的側邊或周圍。並且，第1圖所示出之第一參考單元120與第二參考單元130的設置位置僅為本發明的一種實施範例，不用於限制本發明實施例。使用者亦可視其需求，調整第一參考單元120與第二參考單元130的設置位置，且設置位置於記憶體陣列110的側邊或周圍。此外，第一參考單元120與第二參考單元130可以設置於記憶體陣列110的同一側邊或不同側邊。在本實施例中，記憶體單元111_11~111_MN、第一參考單元120與第二參考單元130的電阻R與電晶體T的尺寸相同。In addition, the first reference unit 120 and the second reference unit 130 are disposed on the side or around the memory array 110. Moreover, the location of the first reference unit 120 and the second reference unit 130 shown in FIG. 1 is only an example of the implementation of the present invention, and is not used to limit the embodiment of the present invention. The user can also adjust the placement positions of the first reference unit 120 and the second reference unit 130 according to their needs, and the placement positions are on the side or around the memory array 110. In addition, the first reference unit 120 and the second reference unit 130 may be disposed on the same side or different sides of the memory array 110. In this embodiment, the memory cells 111_11 to 111_MN, the resistance R of the first reference cell 120 and the second reference cell 130 and the transistor T have the same size.

控制單元140耦接記憶體單元111_11~111_MN、第一參考單元120與第二參考單元130。於資料寫入操作時，控制單元140提供第一電流I1至一記憶體單元，例如記憶體單元111_11。接著，控制單元140讀取記憶體單元111_11回應於第一電流I1產生的第二電流I2，且依據記憶單元111_1的資料寫入狀態，選擇比對第二電流I2與第一參考電流I_HRS，或是比對第二電流I2與第二參考電流I_LRS，以確定資料寫入狀態的資料寫入是否成功。The control unit 140 is coupled to the memory units 111_11 to 111_MN, the first reference unit 120 and the second reference unit 130. During the data writing operation, the control unit 140 provides the first current I1 to a memory cell, such as the memory cell 111_11. Then, the control unit 140 reads the second current I2 generated by the memory cell 111_11 in response to the first current I1, and selects and compares the second current I2 with the first reference current I_HRS according to the data writing state of the memory cell 111_1, or It compares the second current I2 with the second reference current I_LRS to determine whether the data writing in the data writing state is successful.

進一步來說，當記憶體單元111_11的資料寫入狀態為高邏輯準位時，表示寫入資料為1。接著，控制單元140會選擇比對第二電流I2與第二參考電流I_LRS，以確定資料寫入狀態的資料寫入是否成功。舉例來說，如第3圖所示，I2為第二電流，I_LRS為第二參考電流，W1為第二電流I2與第二參考電流I_LRS之間的感測窗(sensing window)。Furthermore, when the data writing state of the memory cell 111_11 is a high logic level, it means that the writing data is 1. Then, the control unit 140 selects and compares the second current I2 with the second reference current I_LRS to determine whether the data writing in the data writing state is successful. For example, as shown in Figure 3, I2 is the second current, I_LRS is the second reference current, and W1 is the sensing window between the second current I2 and the second reference current I_LRS.

當控制單元140確認出第二電流I2的電流值小於第二參考電流I_LRS的電流值時，控制單元140會確定資料寫入狀態的資料寫入是成功的，亦即記憶體單元111_11的寫入資料確實為1。當控制單元140確認出第二電流I2的電流值未小於第二參考電流I_LRS的電流值時，控制單元140會確定資料寫入狀態的資料寫入未成功的，亦即記憶體單元111_11的寫入資料不為1。其餘記憶體單元的資料寫入操作可參考記憶體單元111_11的資料寫入操作，故在此不再贅述。When the control unit 140 determines that the current value of the second current I2 is less than the current value of the second reference current I_LRS, the control unit 140 determines that the data writing in the data writing state is successful, that is, the writing of the memory cell 111_11 The data is indeed 1. When the control unit 140 determines that the current value of the second current I2 is not less than the current value of the second reference current I_LRS, the control unit 140 determines that the data writing in the data writing state is unsuccessful, that is, the writing of the memory cell 111_11 The input data is not 1. The data writing operation of the remaining memory cells can refer to the data writing operation of the memory cell 111_11, so it will not be repeated here.

在一些實施例中，第二參考單元130的電晶體T的尺寸可以設置大於記憶體單元111_11~110_MN與第一參考單元120的電晶體T的尺寸，使得第二參考單元130的電晶體T的開關能力增加。因此，第二參考單元130所提供電流由第二參考電流I_LRS變為第二參考電流I’_LRS，且第二電流I2與第二參考電流I’_LRS之間的感測窗W2的長度會長於第二電流I2與第二參考電流I_LRS之間的感測窗W1的長度，如第3圖所示。如此一來，可以有效地增加記憶體的可靠度及精準度。In some embodiments, the size of the transistor T of the second reference unit 130 can be set to be larger than the size of the transistor T of the memory unit 111_11~110_MN and the first reference unit 120, so that the size of the transistor T of the second reference unit 130 Increased switching capacity. Therefore, the current provided by the second reference unit 130 changes from the second reference current I_LRS to the second reference current I'_LRS, and the length of the sensing window W2 between the second current I2 and the second reference current I'_LRS will be longer than The length of the sensing window W1 between the second current I2 and the second reference current I_LRS is as shown in FIG. 3. In this way, the reliability and accuracy of the memory can be effectively increased.

另一方面，當記憶體單元111_11的資料寫入狀態為低邏輯準位時，表示寫入資料為0。接著，控制單元140會選擇比對第二電流I2與第一參考電流I_HRS，以確定資料寫入狀態的資料寫入是否成功。舉例來說，如第4圖所示，I2為第二電流，I_HRS為第一參考電流，W3為第二電流I2與第一參考電流I_HRS之間的感測窗。On the other hand, when the data writing state of the memory cell 111_11 is a low logic level, it means that the writing data is 0. Then, the control unit 140 selects and compares the second current I2 with the first reference current I_HRS to determine whether the data writing in the data writing state is successful. For example, as shown in Figure 4, I2 is the second current, I_HRS is the first reference current, and W3 is the sensing window between the second current I2 and the first reference current I_HRS.

當控制單元140確認出第二電流I2的電流值大於第一參考電流I_HRS的電流值時，控制單元140會確定資料寫入狀態的資料寫入是成功的，亦即記憶體單元111_11的寫入資料確實為0。當控制單元140確認出第二電流I2的電流值未大於第一參考電流I_HRS的電流值時，控制單元140會確定資料寫入狀態的資料寫入未成功的，亦即記憶體單元111_11的寫入資料不為0。When the control unit 140 determines that the current value of the second current I2 is greater than the current value of the first reference current I_HRS, the control unit 140 determines that the data writing in the data writing state is successful, that is, the writing of the memory cell 111_11 The data is indeed 0. When the control unit 140 determines that the current value of the second current I2 is not greater than the current value of the first reference current I_HRS, the control unit 140 determines that the data writing in the data writing state is unsuccessful, that is, the writing of the memory cell 111_11 The input data is not 0.

在一些實施例中，第一參考單元120的電阻R的尺寸可以設置於小於記憶體單元111_11~111_MN與第二參考單元130的電阻R的尺寸。因此，第一參考單元120所提供電流由第一參考電流I_HRS變為第二參考電流I’_HRS，且第二電流I2與第一參考電流I’_HRS之間的感測窗W4的長度會長於第二電流I2與第一參考電流I_HRS之間的感測窗W3的長度，如第4圖所示。如此一來，可以更有效地增加記憶體的可靠度及精準度。In some embodiments, the size of the resistance R of the first reference unit 120 may be set to be smaller than the size of the resistance R of the memory cells 111_11 to 111_MN and the second reference unit 130. Therefore, the current provided by the first reference unit 120 changes from the first reference current I_HRS to the second reference current I'_HRS, and the length of the sensing window W4 between the second current I2 and the first reference current I'_HRS will be longer than The length of the sensing window W3 between the second current I2 and the first reference current I_HRS is as shown in FIG. 4. In this way, the reliability and accuracy of the memory can be more effectively increased.

另外，於資料讀取操作時，控制單元140讀取記憶體單元(例如記憶體單元111_11)所對應的第二電流I2。接著，控制單元140依據第二電流I2、第一參考電流I_HRS與第二參考電流I_LRS，判斷記憶體單元的資料寫入狀態的邏輯準位。In addition, during the data reading operation, the control unit 140 reads the second current I2 corresponding to the memory unit (for example, the memory unit 111_11). Then, the control unit 140 determines the logic level of the data writing state of the memory cell according to the second current I2, the first reference current I_HRS, and the second reference current I_LRS.

在本實施例中，控制單元140依據第二電流I2與第一參考電流I_HRS的第一差值(例如I2-I_HRS)以及第二電流I2與第二參考電流I_LRS的第二差值(例如I2-I_LRS)，判斷邏輯準位為高邏輯準位或低邏輯準位。進一步來說，控制單元140可以比較第一差值的絕對值(例如|I2-I_HRS|)以及第二差值的絕對值(例如|I2-I_LRS|)，判斷邏輯準位為高邏輯準位或低邏輯準位。In this embodiment, the control unit 140 is based on the first difference between the second current I2 and the first reference current I_HRS (for example, I2-I_HRS) and the second difference between the second current I2 and the second reference current I_LRS (for example, I2 -I_LRS), to determine whether the logic level is a high logic level or a low logic level. Further, the control unit 140 may compare the absolute value of the first difference (for example |I2-I_HRS|) and the absolute value of the second difference (for example |I2-I_LRS|), and determine that the logic level is a high logic level Or low logic level.

舉例來說，當第一差值的絕對值(例如|I2-I_HRS|)大於第二差值的絕對值(例如|I2-I_LRS|)時，控制單元140判斷記憶體單元111_11的資料寫入狀態為低邏輯準位。For example, when the absolute value of the first difference (e.g. |I2-I_HRS|) is greater than the absolute value of the second difference (e.g. |I2-I_LRS|), the control unit 140 determines that the data written in the memory unit 111_11 The state is low logic level.

當第一差值的絕對值(例如|I2-I_HRS|)小於第二差值的絕對值(例如|I2-I_LRS|)時，控制單元140判斷記憶體單元111_11的資料寫入狀態為高邏輯準位。When the absolute value of the first difference (for example |I2-I_HRS|) is less than the absolute value of the second difference (for example |I2-I_LRS|), the control unit 140 determines that the data writing state of the memory unit 111_11 is high logic Level.

也就是說，當對記憶體單元進行讀取操作時，控制單元140可以透過上述的方式來得知記憶體單元的資料寫入狀態。如此一來，可以增加使用上的便利性。In other words, when the memory cell is read, the control unit 140 can learn the data writing status of the memory cell in the above-mentioned manner. In this way, the convenience of use can be increased.

第5圖為依據本發明另一實施例之記憶體裝置的示意圖。請參考第5圖，記憶體裝置500包括記憶體陣列110、第一參考單元120、第二參考單元130與控制單元140。第5圖之記憶體陣列110與控制單元140與第1圖之記憶體陣列110與控制單元140相同或相似，可參考第1圖之實施例的說明，故在此不再贅述。FIG. 5 is a schematic diagram of a memory device according to another embodiment of the invention. Please refer to FIG. 5, the memory device 500 includes a memory array 110, a first reference unit 120, a second reference unit 130, and a control unit 140. The memory array 110 and the control unit 140 in FIG. 5 are the same as or similar to the memory array 110 and the control unit 140 in FIG. 1. The description of the embodiment in FIG. 1 can be referred to, so the details are omitted here.

在本實施例中，第一參考單元120可以包括多個第一子參考單元511_1~511_O，提供多個第一子參考電流，其中O為大於1的正整數。另外，第一參考單元120以上述第一子參考電流的中位數或是平均值作為第一參考電流I_HRS的電流值。In this embodiment, the first reference unit 120 may include a plurality of first sub-reference units 511_1 to 511_O to provide a plurality of first sub-reference currents, where O is a positive integer greater than 1. In addition, the first reference unit 120 uses the median or average value of the first sub-reference current as the current value of the first reference current I_HRS.

第二參考單元130可以包括多個第二子參考單元521_~521_P，提供多個第二子參考電流，其中P為大於1的正整數。另外第二參考單元130以上述第二子參考電流的中位數或是平均值作為第二參考電流I_LRS的電流值。The second reference unit 130 may include a plurality of second sub-reference units 521_˜521_P to provide a plurality of second sub-reference currents, where P is a positive integer greater than one. In addition, the second reference unit 130 uses the median or average value of the second sub-reference current as the current value of the second reference current I_LRS.

在本實施例中，第一子參考單元511_1~511_O與第二子參考單元521_~521_P的數量依據記憶體陣列110的尺寸而改變。另外，第一子參考單元511_1~511_O與第二子參考單元521_~521_P的數量相同或不同，亦即O與P可以相同或不同。In this embodiment, the numbers of the first sub-reference units 511_1 to 511_O and the second sub-reference units 521_ to 521_P vary according to the size of the memory array 110. In addition, the numbers of the first sub-reference units 511_1~511_O and the second sub-reference units 521_~521_P are the same or different, that is, O and P can be the same or different.

藉由上述實施例的說明，本發明另提出一種記憶體裝置的操作方法。第6圖為依據本發明一實施例之記憶體裝置的操作方法的流程圖。在步驟S602中，提供記憶體陣列，其具有多個記憶體單元。在步驟S604中，提供第一參考單元，其提供第一參考電流。在步驟S606中，提供第二參考單元，其提供第二參考電流，其中第一參考電流的電流值小於第二參考電流的電流值。Based on the description of the above-mentioned embodiments, the present invention further provides an operating method of a memory device. FIG. 6 is a flowchart of a method of operating a memory device according to an embodiment of the invention. In step S602, a memory array is provided, which has a plurality of memory cells. In step S604, a first reference unit is provided, which provides a first reference current. In step S606, a second reference unit is provided, which provides a second reference current, wherein the current value of the first reference current is smaller than the current value of the second reference current.

在步驟S608中，於資料寫入操作時，提供第一電流至一記憶體單元，並讀取記憶體單元回應於第一電流產生的第二電流。在步驟S610中，依據記憶單元的資料寫入狀態，選擇比對第二電流與第一參考電流，或是比對第二電流與第二參考電流，以確定資料寫入狀態的資料寫入是否成功。In step S608, during the data writing operation, a first current is provided to a memory cell, and a second current generated by the memory cell in response to the first current is read. In step S610, according to the data writing state of the memory cell, it is selected to compare the second current with the first reference current, or compare the second current with the second reference current, to determine whether the data writing in the data writing state success.

進一步來說，步驟S610包括下列步驟。當記憶體單元的資料寫入狀態為低邏輯準位時，選擇比對第二電流與第一參考電流，以確定資料寫入狀態的資料寫入是否成功。當記憶體單元的資料寫入狀態為高邏輯準位時，選擇比對第二電流與第二參考電流，以確定資料寫入狀態的資料寫入是否成功。另外，第一參考單元包括多個第一子參考單元，提供多個第一子參考電流，而第一參考單元以第一子參考電流的中位數或是平均值作為第一參考電流的電流值，以及第二參考單元包括多個第二子參考單元，提供多個第二子參考電流，而第二參考單元以第二子參考電流的中位數或是平均值作為第二參考電流的電流值。Furthermore, step S610 includes the following steps. When the data writing state of the memory cell is a low logic level, the second current and the first reference current are selected and compared to determine whether the data writing in the data writing state is successful. When the data writing state of the memory cell is at a high logic level, the second current and the second reference current are selected and compared to determine whether the data writing in the data writing state is successful. In addition, the first reference unit includes a plurality of first sub-reference units to provide a plurality of first sub-reference currents, and the first reference unit uses the median or average value of the first sub-reference currents as the current of the first reference current Value, and the second reference unit includes a plurality of second sub-reference units to provide a plurality of second sub-reference currents, and the second reference unit uses the median or average of the second sub-reference currents as the second reference current Current value.

第7圖為依據本發明另一實施例之記憶體裝置的操作方法的流程圖。在步驟S702中，於資料讀取操作時，讀取記憶體單元所對應的第二電流。在步驟S704中，依據第二電流、第一參考電流與第二參考電流，判斷記憶體單元的該資料寫入狀態的邏輯準位。進一步來說，步驟S704包括下列步驟。依據第二電流與第一參考電流的第一差值以及第二電流與第二參考電流的第二差值的絕對值大小，判斷記憶體單元的資料寫入狀態為高邏輯準位或低邏輯準位。當第一差值的絕對值大於第二差值的絕對值時，判斷記憶體單元為低邏輯準位。另一方面，當第一差值的絕對值小於第二差值的絕對值時，判斷記憶體單元為低邏輯準位。FIG. 7 is a flowchart of a method of operating a memory device according to another embodiment of the invention. In step S702, during the data reading operation, the second current corresponding to the memory cell is read. In step S704, the logic level of the data writing state of the memory cell is determined according to the second current, the first reference current, and the second reference current. Furthermore, step S704 includes the following steps. According to the first difference between the second current and the first reference current and the absolute value of the second difference between the second current and the second reference current, determine whether the data writing state of the memory cell is a high logic level or a low logic level Level. When the absolute value of the first difference is greater than the absolute value of the second difference, it is determined that the memory cell is at a low logic level. On the other hand, when the absolute value of the first difference is smaller than the absolute value of the second difference, it is determined that the memory cell is at a low logic level.

綜上所述，本發明實施例所揭露之記憶體裝置與其操作方法，透過第一參考單元提供第一參考電流以及第二參考單元提供第二參考電流，其中第一參考電流的電流值小於第二參考電流的電流值。於資料寫入操作時，控制單元可依據記憶單元的資料寫入狀態，選擇比對第二電流與第一參考電流，或是比對第二電流與第二參考電流，以確定資料寫入狀態的資料寫入是否成功。如此一來，可以有效地增加記憶體的可靠度及精準度。另外，透過改變第一參考單元的電阻的尺寸及/或第二參考單元的電晶體的尺寸，可以增加感測窗的長度，更能增加記憶體的可靠度及精準度。In summary, in the memory device and its operating method disclosed in the embodiments of the present invention, the first reference current is provided by the first reference unit and the second reference current is provided by the second reference unit, wherein the current value of the first reference current is smaller than the first reference current 2. The current value of the reference current. During the data writing operation, the control unit can choose to compare the second current with the first reference current, or compare the second current with the second reference current, according to the data writing state of the memory cell, to determine the data writing state Whether the data is written successfully. In this way, the reliability and accuracy of the memory can be effectively increased. In addition, by changing the size of the resistor of the first reference unit and/or the size of the transistor of the second reference unit, the length of the sensing window can be increased, and the reliability and accuracy of the memory can be increased.

此外，於資料讀取操作時，控制單元讀取記憶體單元所對應的第二電流，並依據第二電流、第一參考電流與第二參考電流，判斷記憶體單元的資料寫入狀態的邏輯準位。如此一來，在記憶體單元寫入資料後，可以有效地得知記憶體單元之資料寫入狀態的邏輯準位，以增加使用上的便利性。In addition, during the data reading operation, the control unit reads the second current corresponding to the memory cell, and determines the logic of the data write state of the memory cell based on the second current, the first reference current, and the second reference current Level. In this way, after the data is written in the memory cell, the logic level of the data writing state of the memory cell can be effectively known to increase the convenience of use.

本發明雖以實施例揭露如上，然其並非用以限定本發明的範圍，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可做些許的更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention is disclosed as above by embodiments, it is not intended to limit the scope of the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100、500:記憶體裝置 110:記憶體陣列 111_11~111_MN:記憶體單元 120:第一參考單元 130:第二參考單元 140:控制單元 511_1~511_O:第一子參考單元 521_1~521_P:第二子參考單元 I1:第一電流 I2:第二電流 I_HRS、I’_HRS:第一參考電流 I_LRS、I’_LRS:第二參考電流 R:電阻 T:電晶體 W1、W2、W3、W4:感測窗 S602~S610、S702~S704:步驟100, 500: memory device 110: memory array 111_11~111_MN: Memory unit 120: The first reference unit 130: second reference unit 140: control unit 511_1~511_O: the first sub-reference unit 521_1~521_P: The second sub-reference unit I1: first current I2: second current I_HRS, I’_HRS: the first reference current I_LRS, I’_LRS: second reference current R: resistance T: Transistor W1, W2, W3, W4: sensing window S602~S610, S702~S704: steps

第1圖為依據本發明一實施例之記憶體陣列的示意圖。 第2圖為依據本發明一實施例之記憶體單元、第一參考單元與第二參考單元的示意圖。 第3圖為依據本發明一實施例之記憶體單元之資料寫入狀態為低邏輯準位時之第二電流與第二參考電流的感測窗的示意圖。 第4圖為依據本發明一實施例之記憶體單元之資料寫入狀態為高邏輯準位時之第二電流與第一參考電流的感測窗的示意圖。 第5圖為依據本發明另一實施例之記憶體陣列的示意圖。 第6圖為依據本發明一實施例之記憶體裝置的操作方法的流程圖。 第7圖為依據本發明另一實施例之記憶體裝置的操作方法的流程圖。 FIG. 1 is a schematic diagram of a memory array according to an embodiment of the invention. FIG. 2 is a schematic diagram of a memory unit, a first reference unit, and a second reference unit according to an embodiment of the invention. FIG. 3 is a schematic diagram of the sensing window of the second current and the second reference current when the data write state of the memory cell is a low logic level according to an embodiment of the present invention. FIG. 4 is a schematic diagram of the sensing window of the second current and the first reference current when the data writing state of the memory cell is a high logic level according to an embodiment of the present invention. FIG. 5 is a schematic diagram of a memory array according to another embodiment of the invention. FIG. 6 is a flowchart of a method of operating a memory device according to an embodiment of the invention. FIG. 7 is a flowchart of a method of operating a memory device according to another embodiment of the invention.

100:記憶體裝置 100: Memory device

110:記憶體陣列 110: memory array

110_11~110_MN:記憶體單元 110_11~110_MN: Memory unit

120:第一參考單元 120: The first reference unit

130:第二參考單元 130: second reference unit

140:控制單元 140: control unit

I1:第一電流 I1: first current

I2:第二電流 I2: second current

I_HRS:第一參考電流 I_HRS: first reference current

I_LRS:第二參考電流 I_LRS: second reference current

Claims (14)

一種記憶體裝置，包括： 一記憶體陣列，具有多個記憶體單元； 一第一參考單元，提供一第一參考電流； 一第二參考單元，提供一第二參考電流，其中該第一參考電流的電流值小於該第二參考電流的電流值；以及 一控制單元，耦接該些記憶體單元、該第一參考單元與該第二參考單元，於一資料寫入操作時，該控制單元提供一第一電流至一記憶體單元，並讀取該記憶體單元回應於該第一電流產生的一第二電流，且依據該記憶單元的一資料寫入狀態，選擇比對該第二電流與該第一參考電流，或是比對該第二電流與該第二參考電流，以確定該資料寫入狀態的一資料寫入是否成功。 A memory device includes: A memory array with a plurality of memory cells; A first reference unit, providing a first reference current; A second reference unit providing a second reference current, wherein the current value of the first reference current is smaller than the current value of the second reference current; and A control unit is coupled to the memory units, the first reference unit and the second reference unit. During a data writing operation, the control unit provides a first current to a memory unit and reads the memory unit The memory cell responds to a second current generated by the first current, and selects to compare the second current with the first reference current, or compare the second current according to a data writing state of the memory cell And the second reference current to determine whether a data writing in the data writing state is successful. 如申請專利範圍第1項所述之記憶體裝置，其中當該記憶體單元的該資料寫入狀態為一低邏輯準位時，該控制單元選擇比對該第二電流與該第一參考電流，以確定該資料寫入狀態的該資料寫入是否成功，當該記憶體單元的該資料寫入狀態為一高邏輯準位時，該控制單元選擇比對該第二電流與該第二參考電流，以確定該資料寫入狀態的該資料寫入是否成功。For the memory device described in claim 1, wherein when the data writing state of the memory unit is a low logic level, the control unit selects to compare the second current with the first reference current , To determine whether the data writing in the data writing state is successful, when the data writing state of the memory unit is a high logic level, the control unit selects to compare the second current with the second reference Current to determine whether the data writing in the data writing state is successful. 如申請專利範圍第1項所述之記憶體裝置，其中該第一參考單元與該第二參考單元設置於該記憶體陣列的側邊或周圍。According to the memory device described in claim 1, wherein the first reference unit and the second reference unit are arranged on the side or around the memory array. 如申請專利範圍第1項所述之記憶體裝置，其中該第一參考單元包括多個第一子參考單元，提供多個第一子參考電流，而該第一參考單元以該些第一子參考電流的一中位數或是一平均值作為該第一參考電流的電流值，以及該第二參考單元包括多個第二子參考單元，提供多個第二子參考電流，而該第二參考單元以該些第二子參考電流的一中位數或是一平均值作為該第二參考電流的電流值。According to the memory device described in claim 1, wherein the first reference unit includes a plurality of first sub-reference units to provide a plurality of first sub-reference currents, and the first reference unit uses the first sub-reference units A median or an average value of the reference current is used as the current value of the first reference current, and the second reference unit includes a plurality of second sub-reference units to provide a plurality of second sub-reference currents, and the second reference current The reference unit uses a median or an average value of the second sub-reference currents as the current value of the second reference current. 如申請專利範圍第1項所述之記憶體裝置，其中該些記憶體單元、該第一參考單元與該第二參考單元各自包括一電阻與一電晶體，且該電阻與該電晶體耦接。The memory device described in claim 1, wherein the memory cells, the first reference cell and the second reference cell each include a resistor and a transistor, and the resistor is coupled to the transistor . 如申請專利範圍第5項所述之記憶體裝置，其中該第一參考單元的該電阻的尺寸小於該些記憶體單元與該第二參考單元的該些電阻的尺寸。In the memory device described in claim 5, the size of the resistor of the first reference cell is smaller than the size of the resistors of the memory cell and the second reference cell. 如申請專利範圍第5項所述之記憶體裝置，其中該第二參考單元的該電晶體的尺寸大於該些記憶體單元與該第一參考單元的該些電晶體的尺寸。The memory device described in claim 5, wherein the size of the transistor of the second reference unit is larger than the size of the memory cells and the transistors of the first reference unit. 如申請專利範圍第1項所述之記憶體裝置，其中於一資料讀取操作時，該控制單元讀取該記憶體單元所對應的該第二電流，並依據該第二電流、該第一參考電流與該第二參考電流，判斷該記憶體單元的該資料寫入狀態的一邏輯準位。For the memory device described in claim 1, wherein during a data reading operation, the control unit reads the second current corresponding to the memory unit, and according to the second current, the first The reference current and the second reference current determine a logic level of the data writing state of the memory cell. 如申請專利範圍第8項所述之記憶體裝置，其中該控制單元依據該第二電流與該第一參考電流的一第一差值以及該第二電流與該第二參考電流的一第二差值，判斷該邏輯準位為一高邏輯準位或一低邏輯準位。For the memory device described in claim 8, wherein the control unit is based on a first difference between the second current and the first reference current and a second difference between the second current and the second reference current The difference value determines whether the logic level is a high logic level or a low logic level. 一種記憶體裝置的操作方法，包括： 提供一記憶體陣列，其具有多個記憶體單元； 提供一第一參考單元，其提供一第一參考電流； 提供一第二參考單元，其提供一第二參考電流，其中該第一參考電流的電流值小於該第二參考電流的電流值； 於一資料寫入操作時，提供一第一電流至一記憶體單元，並讀取該記憶體單元回應於該第一電流產生的一第二電流；以及 依據該記憶單元的一資料寫入狀態，選擇比對該第二電流與該第一參考電流，或是比對該第二電流與該第二參考電流，以確定該資料寫入狀態的一資料寫入是否成功。 An operating method of a memory device includes: Provide a memory array with a plurality of memory cells; Providing a first reference unit, which provides a first reference current; Providing a second reference unit that provides a second reference current, wherein the current value of the first reference current is smaller than the current value of the second reference current; During a data writing operation, providing a first current to a memory cell, and reading a second current generated by the memory cell in response to the first current; and According to a data writing state of the memory cell, selecting a data that compares the second current with the first reference current, or compares the second current with the second reference current to determine the data writing state Whether the writing was successful. 如申請專利範圍第10項所述之記憶體裝置的操作方法，其中依據該記憶單元的一資料寫入狀態，選擇比對該第二電流與該第一參考電流，或是比對該第二電流與該第二參考電流，以確定該資料寫入狀態的該資料寫入是否成功的步驟包括： 當該記憶體單元的該資料寫入狀態為一低邏輯準位時，選擇比對該第二電流與該第一參考電流，以確定該資料寫入狀態的該資料寫入是否成功；以及 當該記憶體單元的該資料寫入狀態為一高邏輯準位時，選擇比對該第二電流與該第二參考電流，以確定該資料寫入狀態的該資料寫入是否成功。 According to the operating method of the memory device described in claim 10, according to a data writing state of the memory cell, it is selected to compare the second current with the first reference current, or compare the second current with the first reference current. The steps of determining whether the data writing in the data writing state is successful by using the current and the second reference current include: When the data writing state of the memory cell is a low logic level, selecting and comparing the second current with the first reference current to determine whether the data writing in the data writing state is successful; and When the data writing state of the memory cell is a high logic level, the second current is selected to compare with the second reference current to determine whether the data writing in the data writing state is successful. 如申請專利範圍第10項所述之記憶體裝置的操作方法，其中該第一參考單元包括多個第一子參考單元，提供多個第一子參考電流，而該第一參考單元以該些第一子參考電流的一中位數或是一平均值作為該第一參考電流的電流值，以及該第二參考單元包括多個第二子參考單元，提供多個第二子參考電流，而該第二參考單元以該些第二子參考電流的一中位數或是一平均值作為該第二參考電流的電流值。According to the operating method of the memory device described in claim 10, the first reference unit includes a plurality of first sub-reference units and provides a plurality of first sub-reference currents, and the first reference unit uses the A median or an average value of the first sub-reference current is used as the current value of the first reference current, and the second reference unit includes a plurality of second sub-reference units to provide a plurality of second sub-reference currents, and The second reference unit uses a median or an average value of the second sub-reference currents as the current value of the second reference current. 如申請專利範圍第10項所述之記憶體裝置的操作方法，更包括： 於一資料讀取操作時，讀取該記憶體單元所對應的該第二電流；以及 依據該第二電流、該第一參考電流與該第二參考電流，判斷該記憶體單元的該資料寫入狀態的一邏輯準位。 The operating method of the memory device described in item 10 of the scope of patent application further includes: Reading the second current corresponding to the memory cell during a data reading operation; and According to the second current, the first reference current, and the second reference current, a logic level of the data writing state of the memory cell is determined. 如申請專利範圍第13項所述之記憶體裝置的操作方法，其中該依據該第二電流、該第一參考電流與該第二參考電流，判斷該記憶體單元的該資料寫入狀態的該邏輯準位的步驟包括： 依據該第二電流與該第一參考電流的一第一差值以及該第二電流與該第二參考電流的一第二差值，判斷該邏輯準位為一高邏輯準位或一低邏輯準位。 According to the operating method of the memory device described in claim 13, wherein the data writing state of the memory cell is determined based on the second current, the first reference current, and the second reference current The logic level steps include: According to a first difference between the second current and the first reference current and a second difference between the second current and the second reference current, determine whether the logic level is a high logic level or a low logic level Level.
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