JP2010073236A - Nonvolatile memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile memory device capable of reducing a leakage current during reading and improving a data detection margin. <P>SOLUTION: The nonvolatile memory device includes memory cells 1a, 1b and 2 configured by serially connecting a resistance change element 5 and a bidirectional current limit element 6 and disposed at intersection points between word lines WL1 to WL5 and bit lines BL1 to BL4, the memory cell 1a being fixed in a high resistant state for partial pressure, and the memory cell 1b being fixed in a predetermined resistant state for correction, a row decoder and a word line driver 3 for selecting one of the word lines WL2 to WL5 and applying a reading voltage between the selected word line and the word line WL1, a comparator 7b for comparing partial-pressure voltage of the memory cell 1b and the memory cell 1a with a threshold value, and a correction processing part 21 for connecting the bit line BL1 with a predetermined voltage via a predetermined correction resistor when the result of the threshold comparison is different from a result expected from the resistant state for correction. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a non-volatile memory device in which a plurality of non-volatile memories each including a memory cell capable of electrically writing or erasing data using a resistance change element whose electric resistance changes, and more particularly to each memory cell. Relates to a cross-point type nonvolatile memory device having a current limiting element having two terminals.

  Nonvolatile memory devices are widely installed in portable devices such as mobile phones and digital cameras, and their use is rapidly expanding. In recent years, opportunities for handling audio data and image data have increased, and there has been a strong demand for a nonvolatile memory device that has a larger capacity and operates at a higher speed than before. At the same time, since there are many applications for portable devices, the demand for low power consumption has further increased.

  In response to such a demand, in recent years, a memory cell does not include a selection element such as a transistor, and has a configuration in which a memory element and a current control element (for example, a diode) are connected in series. There are increasing proposals of cross-point type nonvolatile memory devices (hereinafter also referred to as cross-point memories) that are directly connected to word lines (row selection lines) and bit lines (column selection lines) to form a memory array.

  This is because, since the selection transistor is omitted, the layout area and control wiring necessary for the transistor are eliminated, a high-density memory array with the minimum pitch of the wiring rule is possible, and it is suitable for large capacity. In particular, ReRAM (Resistive RAM), which changes resistance at high speed with an electric pulse, has a simple structure in which a resistance change film is sandwiched between a pair of electrodes. The device is expected to be feasible.

  A cross-point memory 65 shown in FIG. 13 is a cross-point memory disclosed in Patent Document 1, and a memory cell 61 is arranged at a point where a row selection line 62 and a column selection line 60 intersect. It comprises a resistance change element 64 and a current limiting element (diode) 66.

  The diode 66 has a well-known characteristic that current flows in one direction (forward direction).

  FIG. 14 shows voltage-current characteristics with the horizontal axis representing voltage and the vertical axis representing current. For example, taking a commercially available general-purpose diode as an example, the forward current (a) flows about 100 μA to 1 mA when a voltage of 0.2 V is applied.

  On the other hand, the reverse current (b) is substantially constant until the applied voltage reaches the break voltage, and is as small as about 10 nA to 1 μA. The absolute amount of current varies with the size of the diode element, but the ratio of forward current and reverse current is similar regardless of size.

  Therefore, as shown in FIG. 15, the voltage V is applied to the row selection line of the selected memory cell, -V is applied to the column selection line, the voltage -V is applied to the row non-selection line, and the voltage V is applied to the column non-selection line. By setting the voltages at both ends to the same potential or reverse bias, almost no current flows through the non-selected memory cells, and the leakage current can be suppressed to a small level even if the cell size of the cross-point memory is large.

  In such a configuration using a unidirectional diode, the resistance change element 64 in the memory cell must have a change characteristic as shown in FIG. That is, it is necessary to be a unipolar variable resistance element that can change both to high resistance and to low resistance by controlling the voltage value of the unipolar applied voltage. In many cases, the unipolar variable resistance element has a characteristic that the time required for resetting is longer than the time required for setting.

  On the other hand, the resistance change element of the bipolar operation as used in Patent Document 2 and the present invention, that is, changes to a high resistance state by applying a voltage of one polarity of positive polarity and negative polarity, and by applying a voltage of the other polarity. A variable resistance element that changes to a low resistance state generally has the advantage of being capable of high-speed operation during reset as well as during set. However, in the case of using a variable resistance element with bipolar operation in a memory array having a cross-point structure using the above-described diode, the connected diode needs to be able to flow current bidirectionally (hereinafter also referred to as a bidirectional diode). There is.

  The forward current (a) and the reverse current (b) of the bidirectional diode of an example as shown in FIG. 17 are reversed in polarity but are almost equal in absolute value. The current flows about 1 mA (not shown).

  In this case, since it is not possible to use a method of applying a reverse bias to deselect a memory cell as shown in FIG. 15, the column selection line of the selected memory cell is set to the ground voltage GND as shown in FIG. Even when the row selection line is set to the read voltage Vr and both the row and column non-selection lines are opened to high impedance (HZ), not only the current path of the selected memory cell indicated by the solid line but also the memory cell through the shortest path There are very many leakage current paths (also referred to as leakage paths) indicated by dotted lines that pass through the three.

  Such a leak path causes problems such as deterioration in sensitivity during reading and an increase in current consumption.

To solve this problem, for example, a technique for dividing the area of the entire memory array at the cross point into smaller blocks with a transistor switch or the like as shown in Patent Document 3 is used to reduce the leak path to an allowable amount. It is possible.
“Highly Scalable Non-Volatile Resistive Memory Using Simple Binary Oxide Driven Asymmetric Unipolar Voltage Pulses” 0-7803-8684-4E / 4E4E / 4E4E4E JP 2005-182986 A JP 2004-185755 A Japanese Patent No. 3913258

  As described above, when a cross-point memory is configured using a memory cell (hereinafter referred to as a bidirectional memory cell) in which a variable resistance element and a bidirectional diode connected in bipolar operation are connected in series, the reverse bias of the diode is turned off. Since a method of deselecting a memory cell using a region cannot be adopted, the leakage current increases as the number of cross-point cells increases.

  FIG. 19 shows a cross-point memory array configuration using a bidirectional memory cell in which a variable resistance element for bipolar operation changes to 1 kΩ in a low resistance state, 10 kΩ in a high resistance state, and a general-purpose diode is bidirectionally connected thereto. A simple simulation is shown.

  In this simulation, a read voltage is applied to the row and column selection lines, and the read current flowing through the selection lines when the other non-selection lines are floating (open to high impedance) is calculated.

  In FIG. 19, I1 indicates that all the non-selected memory cells are in a low resistance state (hereinafter referred to as Rl), the selected memory cell is Rl, and all the memory cells are in Rl. This is a case where the leakage current is the largest in configuration. On the other hand, I2 indicates that all the non-selected memory cells are in a high resistance state (hereinafter referred to as Rh), the selected memory cell is Rh, and all the memory cells are in Rh. This is a case where the leak current is the smallest in terms of configuration.

  As shown in FIG. 19, in order to read a 1-bit selected memory cell, a current of 1 mA or more is required under the worst condition.

  In general, in order to read data from a memory device at high speed, multi-bit read is performed to read a plurality of bits in parallel. In this case, the leakage current increases as the parallel number increases. For example, if a 20-bit multi-bit read is performed, a current of 20 mA or more is required, and the demand for low current consumption cannot be satisfied.

  As a countermeasure against such a problem, as described above, it is conceivable to subdivide the cross-point memory array into small blocks.

  However, in order to take such a measure, a transistor switch or the like for separating the memory array into blocks is necessary, and the capacity density of the memory array is reduced due to the layout area.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to use a transistor for leakage current to a non-selected memory cell at a cross point using a memory cell composed of a resistance change element and a diode. In a semiconductor memory device having a cross-point type memory array using bidirectional memory cells composed of resistance change elements of bipolar operation without reducing the effective area size of the memory array It is in the point which aims at.

  In order to achieve this object, a nonvolatile memory device according to the present invention includes a plurality of first wirings extending in one direction, a plurality of second wirings extending in a direction different from the one direction, A resistance change element that changes between at least two resistance values in a high resistance state and a low resistance state, and a current limiting element that limits a current flowing through the resistance change element according to an applied voltage are connected in series, and A plurality of nonvolatile memory cells connected between the intersections of the first wiring and the second wiring and one of the plurality of first wirings are selected, and a first voltage is applied to the selected first wiring. Corresponding to each of the second wirings, a resistor for connecting the corresponding second wiring to a second voltage different from the first voltage, and corresponding to each of the second wirings The first voltage is being applied, and each of the second wirings is A comparator that compares a voltage appearing in the corresponding second wiring with a predetermined threshold voltage when connected to the second voltage via a resistor, and one of the plurality of second wirings. As the first calibration memory cell, the memory cell connected between each intersection of the first calibration line and each first wiring is the first in either the high resistance state or the low resistance state. When the comparison result by the comparator corresponding to the first calibration line is different from a value expected from the first resistance state, the first calibration line is fixed to the resistance state. A correction processing unit connected to a third voltage via a comparator, and each of the comparators corresponding to the second wirings excluding the first calibration line is further applying the first voltage, and A first calibration line is connected to the third voltage via the first correction resistor. When is, the voltage appearing at the corresponding second wiring compared with the predetermined threshold voltage.

  According to such a configuration, the resistor functions as a voltage dividing resistor together with the selected memory cell, and the voltage dividing resistor and the memory are applied during application of the first voltage and the second voltage. The resistance state of the memory cell can be read by comparing the voltage appearing in the second wiring as a divided voltage with the cell with the predetermined threshold voltage. Therefore, when reading the resistance state of the memory cell, a voltage is always applied through the voltage dividing resistor, so that current consumption is reduced according to the value of the voltage dividing resistor.

  Further, when a comparison result by the comparator corresponding to the first calibration line is different from a result expected from the first resistance state, the correction processing unit changes the first calibration line to the first correction line. By connecting to the third voltage via a resistor, the comparator can redo the comparison in a state where the divided voltage appearing in each second wiring is corrected to approach the third voltage.

  As a result, a non-volatile memory that achieves good low current consumption, increases the detection margin when reading data, increases the block size of the memory array, and improves the reliability of data reading Equipment can be provided.

  The acquisition of the comparison result for calibration and the application of the third voltage for correcting the divided voltage are both suppressed using the first calibration line and the first correction resistor. The effect of improving the reliability of data reading can be obtained with a circuit of a different scale.

  Here, all the memory cells connected between a specific one of the plurality of first wirings and each second wiring are fixed in a high resistance state as redundant memory cells, and each second wiring is connected to the first wiring. The driver may be used as a resistor connected to two voltages, and the driver may further apply the second voltage to the specific first wiring.

  According to this configuration, by using the redundant memory cell fixed in a high resistance state as the voltage dividing resistor, even if the high resistance value of the entire memory array is shifted due to lot variation, voltage dividing is performed accordingly. Since the same memory cell is used instead of the same memory cell, the resistance value is shifted in the same manner, so that variations in the divided voltage can be absorbed. Further, even if the manufacturing process proceeds to a finer structure and the range of the high resistance value is shifted, the same can be dealt with. That is, with this configuration, it is possible to appropriately form the voltage dividing resistors that can obtain a divided voltage with little variation in the memory array.

  In addition, the memory cell connected between the intersections of the second calibration line, which is one of the plurality of second wirings, which is different from the first calibration line, and the first wirings, The memory cell for calibration is fixed to a second resistance state that is different from the first resistance state in the high resistance state and the low resistance state, and the correction processing unit further includes the second calibration line. The second calibration line is connected to a fourth voltage via a second correction resistor when the result of the comparison by the comparator corresponding to is different from the value expected from the second resistance state, Each of the comparators corresponding to each second wiring excluding one calibration line and the second calibration line is further applying the first voltage, and the second calibration line is the second correction resistor. When connected to the fourth voltage via the corresponding second wiring. Voltage may be compared with the predetermined threshold voltage that.

  According to such a configuration, when the comparison result by the comparator corresponding to the second calibration line is different from the result expected from the second resistance state, the correction processing unit performs the second calibration line. Is connected to the fourth voltage via the second correction resistor, and the comparator is compared in a state where the divided voltage appearing in each second wiring is corrected to approach the fourth voltage. Can be redone.

  According to such a data reading method, when the high resistance state obtained from the calibration memory cell fixed in the high resistance state is erroneously determined as the low resistance state, and for the calibration fixed in the low resistance state In any case where the low resistance state obtained from the memory cell is mistakenly determined as the high resistance state, the comparison can be performed again after correcting the divided voltage appropriately. It is possible to provide a nonvolatile memory device in which the margin is further increased, the block size of the memory array can be further increased, and the reliability of data reading is improved.

  The nonvolatile memory device further performs a predetermined operation on data to be written to the memory cell, and sets a write data modulation unit that sets the memory cell in a resistance state corresponding to the data after the predetermined operation; You may provide the read data demodulation part which performs reverse calculation of the said predetermined calculation to the data corresponding to the resistance state read from the said memory cell.

  According to this configuration, the data is further modulated by biasing the word data to Rh or Rl of each memory cell, which causes a decrease in detection margin when the memory cell is determined to be in the high resistance state or the low resistance state. Can be suppressed.

  According to such a data writing and reading method, it is possible to suppress a decrease in detection margin when reading data, and further increase the capacity of the memory array block size and improve the reliability of data reading. A memory device can be provided.

  The present invention can be realized not only as the above-described nonvolatile memory device but also as a method for writing and reading data in the nonvolatile memory device.

  As described above, according to the nonvolatile memory device of the present invention, the voltage obtained by dividing the read voltage between the voltage dividing resistor and the selected memory cell to be read is detected by the comparator, Since the data held according to the resistance state of the selected memory cell is read, all current paths generated by the application of the read voltage pass through the voltage dividing resistor.

  As a result, it is possible to provide a nonvolatile memory device in which the leakage current is satisfactorily reduced and the increase in the leakage current is alleviated even when data is read from a plurality of memory cells simultaneously in parallel.

  This configuration is a cross-point type nonvolatile memory device using a resistance change element, and changes between a high resistance state and a low resistance state when the resistance change element is applied with a bipolar voltage. Therefore, particularly effective low current consumption can be realized when the leakage current cannot be cut off by inserting a diode having one-way characteristics.

  Furthermore, according to the nonvolatile memory device of the present invention, each of the memory cells connected to the calibration line which is one of the plurality of second wirings is used as a calibration memory cell having a fixed resistance state, and the calibration line is used. If the comparison result by the comparator corresponding to is different from the result expected from the fixed resistance state, the correction processing unit connects the calibration line to the third voltage via the correction resistor. The comparison by the comparator can be performed again in a state where the divided voltage of each second wiring is corrected so as to approach the third voltage.

  Thereby, a non-volatile memory device that suppresses a decrease in detection margin when reading data with an increase in memory array size, can further increase the capacity of the block size of the memory array, and also improves the reliability of data reading Can provide.

  An embodiment of a nonvolatile memory device according to the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram of the nonvolatile memory device 100 according to the first embodiment. In FIG. 1, a memory cell 1a, a memory cell 1b, and a memory cell 2 are provided at positions where word lines WL1 to WL5 and bit lines BL1 to BL4 arranged in a lattice intersect, and a cross-point type memory array. I am doing.

  The memory cell 1a, the memory cell 1b, and the memory cell 2 have a bipolar operation resistance change element 5 that changes between at least two resistance values in a high resistance state and a low resistance state by applying voltages having different polarities. And a bidirectional current limiting element 6 (for example, a bidirectional diode).

  The memory cell 1a is a memory cell that is a resistance for voltage division, which will be described later, and the resistance change element is fixed in a high resistance state. The memory cell 1b is a calibration memory cell to be described later, and the resistance change element is fixed in a high resistance state.

  The memory cell 2 is a data memory cell used for normal data storage, and is set to one of the resistance change elements corresponding to data stored in the low resistance state and the high resistance state.

  The row decoder and word line driver 3 (hereinafter abbreviated as word line driver) outputs the output of the driver connected to the word line to a predetermined voltage according to instructions from the system controller and data buffer 9 (hereinafter abbreviated as system controller). Or open to high impedance.

  The column decoder and bit line driver 4 (hereinafter abbreviated as a bit line driver) adjusts the output of the driver connected to the bit line to a predetermined voltage or opens it to high impedance according to an instruction from the system controller 9.

  Among the bit line drivers 4, in particular, the correction driver 20 opens the bit line BL1 to high impedance or pulls it down to the ground voltage with a resistor having a predetermined resistance value in accordance with an instruction from the system controller 9.

  The comparator (comparator) 7a and the comparator 7b compare the voltages of the bit lines BL1 to BL4 with a predetermined reference voltage (not shown), and read the comparison result as a digital signal of “H” or “L”. 8 operates as a voltage comparator that outputs to 8.

  The read word register 8 stores the input read data in an internal register, and outputs the stored data in accordance with an instruction from the system controller 9.

  The host interface 10 communicates data and control commands between the nonvolatile memory device 100 and an external device.

  The system controller 9 controls the word line driver 3 and the bit line driver 4 in accordance with commands and data given from the external device via the host interface 10 to write data into the memory array or from the memory array. The data is read out.

  The correction processing unit 21 controls the correction driver 20 to set the bit line BL1 to a predetermined resistance value when the comparison result by the comparator 7b is different from the value expected from the high resistance state, which is the resistance state of the memory cell 1b. By pulling down to the ground voltage with a resistor having the above, the detection level of data of other bit lines is corrected. The correction processing unit 21 can be realized as one of the program processes of the system controller 9 composed of, for example, a microprocessor.

  Although FIG. 1 illustrates a memory array having five word lines and four bit lines, the present invention is not limited to this number and aspect ratio.

  Next, a data write operation in the nonvolatile memory device 100 will be described.

  The system controller 9 stores the write data in the internal data buffer according to the write command and write data given from the host interface 10.

  Further, the system controller 9 applies a write pulse to the selected memory cell corresponding to the address for recording the write data.

  As described above, the resistance change element has a characteristic of changing between at least two resistance values of the high resistance state and the low resistance state by applying voltages of different polarities, and the low resistance voltage is expressed as Vrl. When the high resistance voltage is Vrh, Vrl and Vrh are applied to the memory cells so that their polarities are different from each other.

  For example, when the resistance change element of the selected memory cell is changed to the low resistance state (Rl), a word line and a bit line to which all the memory cells of the array are connected are applied in advance to a voltage of 1/2 Vrl ( Hereinafter, it is also referred to as a precharge operation). Thereafter, the bit line to which the selected memory cell is connected is changed to the ground voltage (GND), the word line to which the selected memory cell is connected is changed to the low resistance voltage Vrl, and the voltage amplitude of Vrl is applied to the selected memory cell. Thus, only the selected memory cell changes to the low resistance state.

  On the other hand, when changing the resistance change element of the selected memory cell to the high resistance state (Rh), after precharging the word line and the bit line to which all the memory cells of the array are connected to 1/2 Vrh, The word line to which the selected memory cell is connected is changed to the ground voltage, the bit line to which the selected memory cell is connected is changed to the high resistance voltage Vrh, and the voltage amplitude of Vrh is applied to the selected memory cell, and only the selected memory cell is applied. Changes to a high resistance state. In this way, precharging to each ½ voltage in advance may cause a voltage amplitude close to Vrl or Vrh to an unselected memory cell during a transient when a pulse of Vrl or Vrh is applied to the selected cell. This is to prevent erroneous writing.

  This write operation is an example of a general technique in a cross-point type memory device using bidirectional memory cells. For example, the voltage value used for precharge and the precharge method and order are limited to those described above. It is not what is done.

  In the nonvolatile memory device 100, the voltage for changing the resistance state of the connected memory cell 1b is not applied to the bit line BL1, and the memory cell 1b is fixed to the high resistance state.

  Next, a read operation in the nonvolatile memory device 100, which is a feature of the present invention, will be described.

  A major feature of the nonvolatile memory device 100 regarding the read operation is that each bit line is connected to a reference voltage via a memory cell 1a (hereinafter, abbreviated as a redundant memory cell) that is a voltage dividing resistor, and a specific bit All memory cells other than the redundant memory cells connected to the line are used as calibration memory cells (hereinafter abbreviated as calibration memory cells).

  Here, both the redundant memory cell and the calibration memory cell are memory cells in which the resistance change element of the memory cell is fixed to Rh and data is not stored. The redundant memory cell of each bit line may be connected to a voltage source that generates a reference voltage via, for example, a common word line for voltage division, and the reference voltage may be a ground voltage.

  In FIG. 1, the memory cell 1a is a redundant memory cell and is connected to the voltage dividing word line WL1, and the memory cell 1b is a calibration memory cell and is connected to the bit line BL1.

  The present inventors have disclosed a related patent application, Japanese Patent Application No. 2008-215725, regarding a configuration of a nonvolatile memory device having no calibration memory cell as a basic form of the above-described configuration, and an invention relating to a reading method using a redundant memory cell. Proposed in the specification. An object of the present invention is to reduce current consumption even when multi-bit reading is performed in which a plurality of bits are read in parallel in a cross-point type memory device using bidirectional memory cells.

  An object of the present invention is to improve a new problem by adding a calibration memory cell to the nonvolatile memory device of the related invention. Here, in order to facilitate understanding of the present invention, a reading method using redundant memory cells performed in a nonvolatile memory device having no calibration memory cell will be described.

  FIG. 2 is a schematic diagram showing only the memory array portion of FIG. 1 in a plan view and showing voltages and pulse voltages applied to each wiring for reading.

  In FIG. 2, the memory cell is indicated by a circle at the intersection of the bit line and the word line. A hatched circle connected to the word line WL1 represents a redundant memory cell. A thick circle represents a selected memory cell, and the other circles represent non-selected memory cells.

  As shown in FIG. 2, the ground voltage is applied to the word line WL1 to which the redundant memory cell is connected, and the read voltage Vr is applied to the word line WL4 to which the selected memory cell is connected. The output of the word line driver to the other non-selected word lines WL2, WL3, WL5... Is set to high impedance. As a result, a voltage obtained by dividing the applied read voltage Vr between the redundant memory cell and the selected memory cell appears on each bit line.

  3 and 4 are explanatory diagrams for explaining this more easily.

  3 and 4, the white rectangle represents the Rl data memory cell, and the black rectangle represents the Rh data memory cell. A hatched rectangle represents a redundant memory cell fixed to Rh. In addition, the selected memory cell is described in the first column, and the non-selected memory cell is described in the second column and thereafter.

  3 and 4, when a voltage pulse of the read voltage Vr is applied to the word line connected to the selected memory cell and a ground voltage is applied to the word line connected to the redundant memory cell, It will be understood that a voltage obtained by dividing the read voltage Vr appears between the selected memory cell and the redundant memory cell.

  Here, the voltage obtained by dividing the read voltage between the redundant memory cell and the selected cell Rh is Vdh, and the voltage obtained by dividing the read voltage between the redundant memory cell and the selected cell Rl is Vdl. Vdh is approximately ½ of Vr, and Vdl has a predetermined level greater than Vdh.

  That is, the voltage Vdet given by (Vdh + Vdl) / 2 is the center voltage of the voltage gap for distinguishing Rh and Rl of the memory cell. That is, | Vdl−Vdet | becomes a detection margin for determining the memory cell as Rl, and | Vdh−Vdet | becomes a detection margin for determining the memory cell as Rh.

  As long as these detection margins are ensured satisfactorily, the comparator 7a and the comparator 7b compare the bit line voltage with Vdet, so that the Rl memory cell is “1” and the Rh memory cell is “ Data “0” is read out.

  The leak current required for reading becomes maximum when all the selected memory cells are Rl, and becomes minimum when all the selected memory cells are Rh.

  Further, the voltage of each bit line is affected by the voltage of other bit lines through the non-selected memory cells. This effect is greatest when all unselected memory cells are Rl.

  For example, as shown in FIG. 3, when one of the selected memory cells is Rh and all of the remaining are Rl, the voltage of the bit line connected to the selected memory cell of one Rh is the selected memory of the other Rl. It is pushed up by the voltage of the bit line connected to the cell and becomes the maximum value of the voltage obtained for the selected memory cell of Rh.

  Also, as shown in FIG. 4, when one of the selected memory cells is Rl and all the remaining are Rh, the voltage of the bit line connected to the selected memory cell of one Rl is the selected memory of the other Rh. It is pushed down by the voltage of the bit line connected to the cell and becomes the minimum value of the voltage obtained for the selected memory cell of Rl.

  Here, for a memory array having a word length of 20 bits (that is, 20-bit multi-bit read is performed), the bit line voltage and the leakage current when the number of memory cells is increased are obtained by simulation. Here, the resistance value of the variable resistance element was 1 kΩ for Rl and 10 kΩ for Rh.

  FIG. 5 is a graph showing the transition of the bit line voltage with respect to the total number of memory cells constituting the memory array when a read pulse of 6 V is applied to the selected word line as the read voltage Vr. Here, all the non-selected memory cells are Rl.

  In FIG. 5, V1 indicates the voltage of the bit line connected to the selected memory cell of Rl when one selected memory cell is Rh and 19 selected memory cells are Rl.

  V2 indicates the voltage of the bit line connected to the selected memory cell of Rl when one selected memory cell is Rl and 19 selected memory cells are Rh. As described above, V2 is the minimum value of the voltage obtained for the selected memory cell of Rl.

  V3 indicates the voltage of the bit line connected to the selected memory cell of Rh when one selected memory cell is Rh and 19 selected memory cells are Rl. As described above, V3 is the maximum value of the voltage obtained for the selected memory cell of Rh.

  V4 indicates the voltage of the bit line connected to the selected memory cell of Rh when one selected memory cell is Rl and 19 selected memory cells are Rh.

  As long as V2 is larger than V3, the resistance state of each memory cell can be correctly determined using the threshold value (the aforementioned Vdet) provided between V2 and V3.

  From FIG. 5, it can be seen that good determination is possible even when the size of the memory array is 1 kbit or more.

  FIG. 6 is a graph showing the transition of the current value flowing through the memory array with respect to the total number of memory cells constituting the memory array.

  In FIG. 6, I1 indicates a current value when all the memory cells in the memory array are Rl.

  I2 indicates a current value when all the selected memory cells are Rh and all the non-selected memory cells are Rl.

  FIG. 6 shows that the current value is suppressed to 4 mA or less even in the case of 20-bit multi-bit reading.

  As described above, a small amount (for example, one word) of redundant memory cells fixed to Rh are provided in the memory array, and the word line connected to the redundant memory cell and the word connected to the selected memory cell to be read are connected. According to the configuration in which a predetermined read voltage is applied between the lines and a voltage obtained by dividing the read voltage between the redundant memory cell and the selected memory cell is read from the bit line to determine the resistance state of the selected memory cell. Since all the current paths pass through the redundant memory cell fixed at Rh, the leakage current is greatly reduced.

  Further, even when the size of the memory array is increased to 1 k bits or more, for example, a voltage that can distinguish the selected memory cell of Rh and the selected memory cell of Rl from each other is read from the bit line, and the resistance state of each memory cell is changed. It can be judged correctly.

  However, when the number of memory cells is increased with the aim of further increasing the capacity of the memory array, the following problems arise.

  7a and 7b show the same simulation results as in FIG. 5 for the case where the size of the memory array (number of memory cells) is further increased.

  FIG. 7a shows the voltage (V1) of the bit line to which the memory cell of Rl is connected and the memory cell of Rh when 19 of the 20 memory cells selected as one word are Rl and one is Rh. 6 is a graph showing the transition of the voltage (V3) of the bit line to which is connected, V1 and V3 of FIG. 5 being extended to the right.

  From FIG. 7a, it can be seen that the voltage of the bit line to which the Rh memory cells are connected when the memory cells in the word are biased to Rl increases significantly as the size of the memory array increases.

  FIG. 7b shows the voltage (V2) of the bit line to which the memory cell of Rl is connected and the memory cell of Rh when 19 of the 20 memory cells selected as one word are Rh and 1 is Rl. 6 is a graph showing the transition of the voltage (V4) of the bit line to which is connected and V2 and V4 in FIG. 5 extended rightward.

  From FIG. 7b, it can be seen that the voltage of the bit line to which the memory cells of Rl are connected when the memory cells in the word are biased to Rh decreases significantly as the size of the memory array increases.

  These facts indicate that when the memory cells in the word are biased to the resistance state of either Rl or Rh, the detection margin of a small number of resistance state memory cells is reduced.

  In one memory array, the word indicating the voltage transition in FIG. 7a and the word indicating the voltage transition in FIG. 7b can be mixed, so that when the number of memory cells constituting the memory array exceeds 5000, the selected memory cell It can be seen that there is no voltage gap for distinguishing between Rh and Rl, and the resistance state of the selected memory cell cannot be read correctly under the worst condition.

  7A and 7B, it can be seen that the voltage variation is more remarkable when the memory cells in the word are biased to Rl (FIG. 7a). This is because the Rl memory cell supplies more current than the Rh memory cell, and thus has a greater influence on the voltage of the bit line to which the Rh memory cell is connected.

  Therefore, when taking either one of the countermeasure when the memory cell in the word is biased to Rl and the countermeasure when the memory cell is biased to Rh, it is better to take the countermeasure when the memory cell in the word is biased to Rl. This means that the detection margin of the resistance state of the memory cell is greatly improved.

  Therefore, in the first embodiment of the present invention, a non-volatile memory device capable of correcting when a memory cell in a word is biased to Rl will be described. In the nonvolatile memory device according to the first embodiment of the present invention, a calibration memory cell is provided in addition to the redundant memory cell described above, and a detection margin is reduced with respect to an increase in memory array size by a correction process using the calibration memory cell. To compensate.

  Hereinafter, for convenience of explanation, the resistance state of the memory cell and the data stored in the memory cell are used synonymously.

  In the nonvolatile memory device 100 of FIG. 1, a redundant memory cell 1a that is always Rh is provided on the word line WL1, and a calibration memory cell 1b that is always Rh is provided on the bit line BL1.

  Therefore, it is expected that the determination result when the resistance state of the memory cell is Rh is always output from the comparator 7b that determines the voltage of the bit line BL1.

  That is, when the data (resistance state) of each memory cell of each selected word is read, the data read from the calibration memory cell in the corresponding selected word becomes the reference data for calibration, and the bias of the data in the selected word is determined. it can. If the reference data is judged to be different from the expected value, it can be seen that the memory cells in the selected word are biased to Rl.

  As described above, when the reference data is determined to be different from the expected value, the program processing of the correction processing unit 21 is activated, and the read word data with low reliability is discarded.

  The correction processing unit 21 sends a command to the correction driver 20, and pulls down the output of the correction driver 20 to the ground voltage with the resistance value Ro. The resistance value Ro is preferably set to a value substantially equal to the combined resistance of the resistance change element 5 and the bidirectional current limiting element 6 in the Rl state when Vr / 2 is applied to the memory cell. Therefore, an R1 spare cell may be provided separately from the memory array, and the spare cell may be used as a pull-down resistor. In the following, an example of pulling down using a spare cell of Rl will be described.

  In the state pulled down by the spare cell of Rl, the output of the comparator 7b is again taken into the read word register 8 and adopted as correct word data. Thereafter, the output of the correction driver 20 is returned to the normal high impedance state, and the next address reading process is continued.

  In order to show the correction effect of pull-down due to the resistance having the resistance value Ro as described above, the calibration memory cell 1b is connected by a method in which the read voltage is divided and read by the redundant memory cell 1a and the selected word cell as shown in FIG. The transition of the voltage of each bit line when the bit line BL1 is pulled down to the ground voltage via a pull-down resistor was simulated. This simulation result is shown in FIG. 9 in comparison with the case where correction by pull-down is not performed.

  In FIG. 9, as an example of the case where the memory cells in the selected word are biased to R1, assuming that one memory cell is Rh and 19 memory cells are R1, The case where the voltage of the connected bit line is not corrected by pull-down (V1) and the case where the correction is made (V1a) is shown, and the voltage of the bit line connected to the Rh memory cell is corrected by pull-down. The case where it is not performed (V3) and the case where correction is performed (V3a) are shown.

  As shown in FIG. 9, the rise (V3) of the voltage read from the memory cell of Rh that occurs when the memory cell in the selected word is biased to Rl is canceled by the pull-down resistor (V3a). As a result, it is understood that a sufficient voltage gap for distinguishing Rh and Rl of the memory cells can be ensured even if the number of memory cells constituting the memory array exceeds 5000.

  As described above, according to the nonvolatile memory device 100, a small amount (for example, one word) of redundant memory cells are provided in the memory array and calibration memory cells are provided in each word, and all of the redundant memory cells and the calibration memory cells are provided. The structure is not rewritten from the high resistance state. Then, a predetermined read voltage is applied between the word line connected to the redundant memory cell and the word line connected to the selected memory cell to be read, and the read is performed between the redundant memory cell and the selected memory cell. The resistance state of the selected memory cell is determined by reading the voltage obtained by dividing the voltage from the bit line.

  In this configuration, since all the current paths pass through the redundant memory cell fixed at Rh, the leakage current is greatly reduced.

  Further, if the read data obtained from the calibration memory cell is determined to be different from the expected value, it can be seen that the memory cell in the selected word is biased to Rl, and the detection level can be corrected based on this bias information. For this reason, a memory array composed of a large number of memory cells can be configured without being divided into a plurality of blocks, and a large-scale nonvolatile memory device with low current consumption can be provided.

  In the above description, an example of 6 V as Vr is shown, but the voltage value is not limited to this. Furthermore, the voltage divided by all the diodes on the path and the variable resistance element is applied to each variable resistance element. The divided voltage applied to this variable element is used for each variable resistance element. Needless to say, an appropriate value of Vr is set so that the resistance state does not change.

(Second Embodiment)
Next, a second embodiment of the apparatus of the present invention will be described.

  FIG. 10 is a block diagram of the nonvolatile memory device 200 according to the second embodiment. In FIG. 10, the same components as those of the nonvolatile memory device 100 of FIG.

  In the non-volatile memory device 200, as compared with the non-volatile memory device 100, the memory cell 1c connected to the bit line BL2 is fixed to the resistance state R1 as a new calibration memory cell, and the voltage of the bit line BL2 is determined. The comparator 7c is used for calibration, and a new correction driver 22 is provided.

  Since the comparator 7c is functionally equivalent to the comparator 7a and the comparator 7b, description of the operation is omitted. The second bit line potential correction driver 22 is a driver in which the correction driver 20 performs pull-down with the resistance value Ro, whereas the second bit line potential correction driver 22 pulls up to the read voltage Vr with the resistance of the resistance value Ro according to the instruction of the system controller 9. Or switching to open to high impedance is possible.

  Next, the correction operation in the second embodiment will be described. The redundant memory cell 1a which is always Rh is connected to the word line WL1, the calibration memory cell 1b which is always Rh is connected to the bit line BL1, and the calibration memory cell 1c which is always Rl is connected to the bit line BL2. ing.

  Therefore, the comparator 7b for determining the voltage of the bit line BL1 always outputs a determination result corresponding to the memory cell in the high resistance state (Rh), and the comparator 7c for determining the voltage of the bit line BL2 is always in the low resistance state. A determination result corresponding to the memory cell of (Rl) is expected to be output.

  That is, when reading the data of each memory cell of each selected word, the data read from the Rh calibration memory cell and the Rl calibration memory cell in the corresponding selected word becomes the calibration reference data, and the data in the selected word It is possible to determine both when the bias is biased toward Rl and when biased toward Rh.

  In the first embodiment, the correction method and the effect when the memory cell in the word is biased to Rl have been described. Therefore, the correction method and the effect when the memory cell is biased to Rh, which is the opposite, will be described.

  If the selected word data is biased to Rh, the voltage of the bit line connected to the Rl memory cell is pushed down by the influence of the voltage of the bit line connected to the Rh memory cell as shown in FIG. The detection margin for detecting Rl is reduced. In the first embodiment, since only error information in which Rh is mistaken for Rl can be obtained, it is not possible to compensate for a decrease in the detection margin of Rl.

  In the second embodiment, it is possible to detect that Rl is mistaken as Rh by providing the calibration memory cell 1c fixed to Rl. When this error is detected, the bit line BL2 is pulled up to the read voltage Vr by the correction driver 22 via the resistor having the resistance value Ro.

  Similar to the first embodiment, the resistance value Ro is preferably substantially equal to the combined resistance when Vr / 2 is applied to the memory cell in the Rl state, and a spare cell of Rl is provided separately from the memory array, The spare cell may be used as a pull-up resistor. Note that when the amount of correction is insufficient in the pull-up in the memory cell in the Rl state, an optimum design may be made to further reduce the resistance value.

  In order to show the correction effect of the pull-up due to the resistance having the resistance value Ro as described above, the transition of each bit line potential when the voltage is pulled up to 6 V via the correction pull-up Rl cell was simulated. This simulation result is shown in FIG. 11 in contrast to the case where correction by pull-up is not performed.

  In FIG. 11, as an example of the case where the memory cell in the selected word is biased to Rh, assuming that one memory cell is Rl and 19 memory cells are Rh, The case where the voltage of the connected bit line is not corrected by pull-down (V2) and the case where the correction is made (V2a) is shown, and the voltage of the bit line connected to the Rh memory cell is corrected by pull-down. The case where it is not performed (V4) and the case where correction is performed (V4a) are shown.

  As shown in FIG. 11, the voltage drop (V2) read from the memory cell of Rl that occurs when the memory cells in the selected word are biased to Rh is canceled by the pull-up resistor (V2a). As a result, in the second embodiment, both the case where the memory cells in the word are biased to Rl and the case where the memory cells are biased to Rh are corrected. Therefore, although 2 redundant bits are required in each word, The memory size can be greatly improved.

  In the example of FIG. 10, the number of redundant cells is larger than the number of memory cells that can be used for data storage, and the effect of the invention is not emphasized. However, in an actual device, the word length and the memory array size are increased. The effect of capacity reduction is small.

  As described above, according to the nonvolatile memory device 200, a small amount (for example, one word) of redundant memory cells are provided in the memory array and a calibration memory cell is provided in each word, and all of the redundant memory cell and the calibration memory cell are provided. The bit line potential is set to the redundant line by applying a read pulse so that a predetermined read voltage is applied between the word line of the redundant memory cell and the word line of the selected word. The read voltage is divided between the memory cell and the selected memory cell, the resistance state of each memory cell is judged, and all current paths pass through redundant memory cells fixed at Rh, so the leakage current is greatly reduced. can do.

  Further, the deviation of the read data obtained from the calibration memory cell fixed to Rh and the memory cell fixed to Rl from both 0 to 1 error information and 1 to 0 error information from the selected word cell to Rl or Rh The bias level information can be distinguished and the detection level can be corrected based on the bias information.

  Therefore, the size of the memory array can be further increased without being divided into blocks, and a large-scale nonvolatile memory device with low current consumption can be provided.

(Third embodiment)
Next, a non-volatile memory device according to a third embodiment of the present invention will be described with reference to FIG. In the nonvolatile memory device 300 shown in FIG. 12, the points newly added to FIG. 1 are that the data modulation / demodulation means 24 is provided in the system controller and that the external memory 25 such as SRAM is provided. It has been done.

  As described above, when the memory cells in each word are biased to Rl or Rh, the bit line voltage shifts due to the biased side effect and the detection margin decreases. For this reason, in the third embodiment, reduction in detection margin is prevented by performing data modulation so that the data bias is not more than a predetermined amount.

  The system controller 9 temporarily stores data in the external memory 25 in accordance with a write command and data input from the outside via the host interface 10. The data modulation means 24 in the system controller 9 reads out the data in the external memory 25 by a predetermined logic circuit, and modulates so that 0 or 1 does not continue for a predetermined length or longer according to the modulation coding rule, thereby Write data in This prevents the state of Rl or Rh from being extremely biased within one word data.

  Further, at the time of reading, data read from the selected memory cell is once stored in the external memory, and the data demodulating means 24 in the system controller 9 demodulates to the original data even when the reverse processing is performed at the time of modulation, and the host interface. To the outside via.

  Hereinafter, an example of such a modulation scheme will be described. Such a modulation system is known as a general technique for removing a DC component by a communication technique or a magnetic recording technique, and there are various systems depending on transmission characteristics of a communication path.

  As an example, an MFM modulation method is given. In this modulation, data of 1 is converted to 01, and 0 is converted to 00. This requires twice as many data bits, but the 0 or 1 bias is almost completely eliminated.

  However, this method is an extreme example for facilitating understanding, and half of the bits of the nonvolatile memory are made redundant, which is not practically preferable. Modulation schemes with low redundancy such as 8-9 modulation and 24-25 modulation are preferred.

  However, in this case, since suppression of bias may not be sufficient, it is preferably used together with the correction using the calibration memory cell already described. Many combinations and combinations of these methods and combinations can be easily considered, and they are optimally designed in consideration of the change characteristics and resistance ranges of the resistance change elements used, as well as the characteristics of the bidirectional diode and the size of the memory cell array. The

  In addition, although the memory element in the Rl state has been described as an element used for pull-up and pull-down, the resistance value and the element are not limited thereto.

  For example, a fixed resistance using polysilicon in a semiconductor process or an ON resistance of a transistor may be used. Also, the resistance value does not need to be equal to the resistance value of the memory cell in the Rl state, and is optimally designed according to the level to be corrected. The potential level to be pulled up or pulled down is optimally designed by combining convenient values on the circuit.

  That is, the non-volatile memory device of the present invention includes redundant memory cells that are not changed from the Rh state, and is based on error information obtained from calibration memory cells fixed in a known resistance state provided in each word. In many combinations from the design concept of determining the data bias state and correcting the voltage of each bit line, which is the result of dividing the read voltage between the redundant memory cell and the selected memory cell, to improve the detection margin Designed optimally.

  INDUSTRIAL APPLICABILITY The nonvolatile memory device of the present invention is useful as a cross-point nonvolatile memory device using a variable resistance element that operates in a bipolar manner, and has low power consumption such as a card-type memory of a portable device and a data storage memory of a microprocessor. It can be widely used for memory devices that are required to be integrated.

1 is a block diagram showing an example of a configuration of a nonvolatile memory device according to a first embodiment of the present invention. The figure which shows the structure of the memory array in the 1st Embodiment of this invention. The figure explaining the generation principle of the divided voltage read in the 1st Embodiment of this invention The figure explaining the generation principle of the divided voltage read in the 1st Embodiment of this invention The figure which shows the simulation result of the divided voltage read in the 1st Embodiment of this invention The figure which shows the simulation result of the consumption current at the time of read-out operation in the 1st Embodiment of this invention The figure explaining the reduction | decrease in a detection margin when the memory cell in a word is biased to Rl. The figure explaining the reduction | decrease of a detection margin when the memory cell in a word is biased to Rh The figure explaining the correction principle by the correction driver in the 1st Embodiment of this invention. The figure explaining the improvement effect of the detection margin in the 1st Embodiment of this invention The block diagram which shows an example of a structure of the non-volatile memory device in the 2nd Embodiment of this invention. The figure explaining the improvement effect of the detection margin in the 2nd Embodiment of this invention. The block diagram which shows an example of a structure of the non-volatile memory device in the 3rd Embodiment of this invention. Configuration diagram showing an example of a conventional cross-point memory Diagram showing a general example of voltage-current characteristics of a unidirectional diode The figure explaining the read-out operation of the conventional crosspoint memory Diagram showing an example of voltage-current characteristics of a unipolar variable resistance element Diagram showing a general example of voltage-current characteristics of a bidirectional diode The figure explaining the leak path of the read current in the conventional crosspoint memory The figure which shows the simulation result of the consumption current at the time of read-out operation in the conventional crosspoint memory

Explanation of symbols

1a Memory cell which is a resistor for voltage division (redundant memory cell)
1b, 1c Calibration memory cell (calibration memory cell)
2 Data memory cell used for data storage 3 Word line driver 4 Bit line driver 5 Resistance change element 6 Bidirectional current limiting element 7a, 7b, 7c Comparator 8 Read word register 9 System controller 10 Host interface 11 Redundant memory cell adjustment unit 20 , 22 Correction driver 60 Column selection line 61 Memory cell 62 Row selection line 64 Resistance change element 65 Crosspoint memory 66 Diode 100, 200, 300 Non-volatile memory device

Claims (4)

A plurality of first wires extending in one direction;
A plurality of second wires extending in a direction different from the one direction;
A resistance change element that changes between at least two resistance values in a high resistance state and a low resistance state, and a current limiting element that limits a current flowing through the resistance change element according to an applied voltage are connected in series, and A plurality of nonvolatile memory cells connected between the intersections of the first wiring and the second wiring;
A driver that selects one of the plurality of first wirings and applies a first voltage to the selected first wiring;
A resistor provided corresponding to each of the second wirings and connecting the corresponding second wiring to a second voltage different from the first voltage;
A second circuit provided corresponding to each second wiring and corresponding to the second voltage when the first voltage is being applied and the second wiring is connected to the second voltage via the resistor. A comparator that compares the voltage appearing on the wiring with a predetermined threshold voltage, and
The memory cell connected between the intersections of the first calibration line, which is one of the plurality of second wirings, and each of the first wirings is used as a first calibration memory cell in a high resistance state and a low resistance state. Fix to one of the resistance states in the first resistance state,
Furthermore, when the result of comparison by the comparator corresponding to the first calibration line is different from the value expected from the first resistance state, the first calibration line is connected to the third correction resistor via the first correction resistor. A correction processing unit connected to the voltage,
Each of the comparators corresponding to the second wirings excluding the first calibration line is further applying the first voltage, and the first calibration line passes through the first correction resistor. A non-volatile memory device that compares a voltage appearing in the corresponding second wiring with the predetermined threshold voltage when connected to a third voltage. The memory cell connected between the intersections of the second calibration line, which is one of the plurality of second wirings, which is different from the first calibration line, and the first wirings, is used for the second calibration. The memory cell is fixed to a second resistance state that is a resistance state different from the first resistance state of the high resistance state and the low resistance state,
The correction processing unit further sets the second calibration line to a second correction resistor when a result of comparison by the comparator corresponding to the second calibration line is different from a value expected from the second resistance state. Connected to the fourth voltage via the
Each of the comparators corresponding to each second wiring excluding the first calibration line and the second calibration line is further applying the first voltage, and the second calibration line is the second correction. The nonvolatile memory device according to claim 1, wherein when connected to the fourth voltage via a resistor, a voltage appearing in a corresponding second wiring is compared with the predetermined threshold voltage. further,
A write data modulation unit that performs a predetermined operation on data to be written to the memory cell and sets the memory cell to a resistance state corresponding to the data after the predetermined operation
3. The nonvolatile memory device according to claim 1, further comprising: a read data demodulating unit that performs inverse operation of the predetermined operation on data corresponding to the resistance state read from the memory cell. All memory cells connected between a specific one of the plurality of first wirings and each second wiring are fixed as a redundant memory cell in a high resistance state, and each second wiring is set to the second voltage. Used as a resistor to connect,
4. The nonvolatile memory device according to claim 1, wherein the driver further applies the second voltage to the specific first wiring. 5.

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