US20110058414A1 - Memory with multiple reference cells - Google Patents
Memory with multiple reference cells Download PDFInfo
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- US20110058414A1 US20110058414A1 US12/555,872 US55587209A US2011058414A1 US 20110058414 A1 US20110058414 A1 US 20110058414A1 US 55587209 A US55587209 A US 55587209A US 2011058414 A1 US2011058414 A1 US 2011058414A1
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- memory cell
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- 230000004044 response Effects 0.000 claims abstract description 6
- 238000009826 distribution Methods 0.000 description 18
- 230000002277 temperature effect Effects 0.000 description 13
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5642—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/563—Multilevel memory reading aspects
- G11C2211/5634—Reference cells
Definitions
- the invention relates in general to a memory, and more particularly to a memory capable of reducing sense window loss of sense currents due to temperature effect on threshold voltage of memory cells.
- the memory cells are the two-bit Nitride-based trapping storage flash cells
- Non-volatile memory such as flash memory
- the flash memory is a memory with multiple level cells (MLCS), which can be programmed to have four threshold voltage distributions shown as curves d 1 -d 4 corresponding to two bits of data stored in each of the MLC.
- MLCS multiple level cells
- the selected MLC has to be read with three different word line voltages to obtain three cell currents accordingly.
- the three different word line voltages have the respective levels V 1 , V 2 , and V 3 .
- the three cell currents will be compared with a reference current, so as to obtain the data stored in the MLC.
- the threshold voltages of MLCS will be varied due to temperature effect.
- the MLCS will suffer from descents of threshold voltage when the surrounding temperature is raised and the amounts of descents are proportional to the levels of the threshold voltage.
- the four threshold voltage distributions of MLCS in the memory can be shown as curves d 1 ′-d 4 ′.
- MLCS in the memory will suffer from read window loss due to the raised threshold voltages of the MLCS when the surrounding temperature is raised.
- the invention is directed to a memory with multiple level cells (MLCS).
- the memory employs a number of reference cells with reference threshold voltages having similar threshold voltage variations resulting from the temperature effect as a threshold voltage of a read memory cell.
- the reference currents and the read windows determined by the reference currents can be altered according to the threshold voltage variations due to the temperature effect. Consequently, in comparison with the conventional memory, the memory related to the invention can effectively prevent the read window loss due to the temperature effect.
- a memory includes a memory array, a sense amplifier, and a reference circuit.
- the memory array includes a memory cell.
- the sense amplifier includes a first terminal coupled to the memory cell and a second terminal.
- the reference circuit includes a first reference cell, a second reference cell, and a switch.
- the first reference cell has a first reference threshold voltage for providing a first reference current, based on a first reference word line voltage.
- the second reference cell has a second reference threshold voltage for providing a second reference current, based on a second reference word line voltage.
- the switch selectively provides one of the first and the second reference currents to the second terminal in response to a control signal.
- the first and the second reference word line voltages correspond to different voltage levels.
- a memory includes a memory array, a sense means, and a reference means.
- the memory array includes a memory cell.
- the sense means includes a first terminal, coupled to the memory cell, and a second terminal.
- the reference means comprises first current means, second current means, and a switch means.
- the first current means referring to a first reference threshold voltage, provides a first reference current based on a first reference word line voltage.
- the second current means referring to a second reference threshold voltage, provides a second reference current based on a second reference word line voltage.
- the switch means selectively provides one of the first and the second reference currents to the second terminal in response to a control signal.
- the first and the second reference word line voltages correspond to different voltage levels.
- FIG. 1 is an illustration of a programmed threshold voltages distributions of a memory
- FIG. 2 is a block diagram of the memory according to an embodiment of the invention.
- FIG. 3 is an illustration of a programmed threshold voltages distribution of a memory.
- FIG. 4 is a detailed block diagram of a sense amplifier in the sense unit 18 and the reference circuit 20 .
- the memory according to an embodiment of the invention employs a number of reference cells with reference threshold voltages having similar threshold voltage variations resulting from the temperature effect as the threshold voltage of the read memory cell.
- the memory 1 is a MLC memory including a row decoder 12 , Y multiplexers 14 a and 14 b , a memory cell array 16 , a sense unit 18 , a reference circuit 20 , and a controller 22 .
- the memory cell array 16 includes numerous memory cells arranged in an M ⁇ N matrix, wherein M and N are natural numbers greater than 1.
- each of the memory cells which initially has a first state, can be programmed to have three other threshold voltage states indicating the values of two bits of data stored in each of the memory cells.
- the memory cells with the first state and programmed with the three other states form the respective four threshold voltage distributions plotted as curves Ds 1 , Ds 2 , Ds 3 , and Ds 4 .
- the curves Ds 1 to Ds 4 indicate the threshold voltage distributions when the surrounding temperature of the memory 1 is at a first temperature.
- the row decoder 12 and the Y multiplexer 14 a provide the corresponding word line voltages and bias voltages to at least a selected memory cell, so as to drive the memory cells providing cell currents.
- the Y multiplexer 14 b provides the cell current of the selected memory cell to the sense unit 18 so as to sense the data stored in the selected memory cell.
- the selected memory cell is the memory cell T(i,j) with the coordinates (i,j) in the memory array 16 , wherein i and j are natural numbers less than or equal to M and N, respectively.
- the controller 22 controls the operation of the row decoder 12 and the Y multiplexers 14 a and 14 b to read the memory cell T(i,j) with a word line voltage Sw having different levels in different read operations.
- the word line voltage Sw respectively has the levels Vw 1 , Vw 2 , and Vw 3 in a first read operation, in a second read operation, and in a third read operation.
- the threshold voltage state of the memory cell T(i,j) and whether the threshold voltage of the memory cell T(i,j) is greater than the level Vw 1 , the level Vw 2 , and the level Vw 3 can be effectively determined.
- a sense amplifier SA included in the sense unit 18 is for sensing a cell current Icell provided by the memory cell T(i,j).
- the sense amplifier SA includes a first terminal coupled to the memory cell T(i,j) for receiving the cell current Icell and a second terminal coupled to the reference circuit 20 for receiving reference currents.
- the reference circuit 20 includes a switch 41 and reference cells RT 1 , RT 2 , and RT 3 .
- the reference cells RT 1 to RT 3 are respectively programmed to reference threshold voltages Vthr 1 , Vthr 2 , and Vthr 3 .
- the reference cells RT 1 -RT 3 respectively provide a reference current Iref 1 based on a reference word line voltage Swr 1 and the reference threshold voltage Vthr 1 , a reference current Iref 2 based on a reference word line voltage Swr 2 and the reference threshold voltage Vthr 2 , and a reference current Iref 3 based on a reference word line voltage Swr 3 and the reference threshold voltage Vthr 3 .
- the reference word line voltages Swr 1 to Swr 3 respectively have the levels Vw 1 to Vw 3 and the reference threshold voltages Vthr 1 to Vthr 3 respectively have the levels Vw 1 to Vw 3 .
- the switch 41 In response to a control signal Sc provided by the controller 22 , the switch 41 selectively provides one of the reference currents Iref 1 , Iref 2 , and Iref 3 to the second terminal of the sense amplifier SA, e.g., in the first to the third read operations respectively.
- reference currents Iref 1 to Iref 3 are employed by the sense amplifier SA as the reference current in the first to the third read operations, respectively.
- the switch 41 is controlled by the controller 22 to select the reference current Iref 1 as the reference current.
- the controller 22 controls the operation to determine whether the memory cell T(i,j) belongs to the distributions Ds 1 or Ds 2 , it is the reference current Iref 1 being selected.
- the switch 41 is controlled by the controller 22 to respectively select the reference currents Iref 2 and Iref 3 as the reference current.
- the reference currents Iref 2 and Iref 3 are respectively selected by the switch 41 when the controller 22 determines whether the memory cell T(i,j) belongs to the distributions Ds 2 or Ds 3 and belongs to the distributions Ds 3 or Ds 4 .
- the threshold voltage of the memory cell T(i,j) is programmed with threshold voltage less than the level Vw 2 (i.e. the memory cell T(i,j) has the threshold voltage distributions as indicated by the curves Ds 1 or Ds 2 in FIG. 3 )
- the level of threshold voltage of the memory cell T(i,j) is close to the level of the reference threshold voltage Vthr 1 (i.e. the level Vw 1 ).
- the threshold voltage variations of a memory cell due to the temperature effect are proportional to the threshold voltage level and threshold voltages with similar threshold voltage level correspond to similar threshold voltage variations.
- the reference threshold voltage Vthr 1 will have a similar threshold voltage variation and the reference current Iref 1 will have a similar variation as the cell current Icell.
- the curves Ds 1 and Ds 2 representing the threshold voltage distributions are shifted to the left as indicated by the curves Ds 1 ′ and Ds 2 ′.
- the reference threshold voltage Vthr 1 having the level Vw 1 at the first temperature will shift left to the level Vw 1 ′ at the second temperature.
- the reference threshold voltage Vthr 1 serves as the threshold condition between the threshold voltage distributions shown as the curves Ds 1 and Ds 2 . Consequently, the read window loss due to the temperature effect can be effectively recovered.
- threshold voltage of the memory cell T(i,j) When the threshold voltage of the memory cell T(i,j) is programmed with threshold voltage less than the level Vw 3 but greater than the level Vw 1 (i.e. the memory cell T(i,j) is in the threshold voltage distributions plotted as Ds 2 or Ds 3 ) and with threshold voltage greater than Vw 2 (i.e. the memory cell T(i,j) is in the threshold voltage distribution plotted as Ds 3 or Ds 4 ), similar threshold voltage variations will take place on the reference threshold voltages Vthr 2 and Vthr 3 for respectively varied as levels Vw 2 ′ and Vw 3 ′.
- the reference threshold voltages Vthr 2 and Vthr 3 which respectively have the levels Vw 2 and Vw 3 at the first temperature, will respectively shift left to the levels Vw 2 ′ and Vw 3 ′ at the second temperature.
- the reference threshold voltages Vthr 2 serves as the threshold condition between the threshold voltage distributions shown as the curves Ds 2 and Ds 3
- the reference threshold voltage Vthr 3 serves as the threshold condition between the threshold voltage distributions shown as the curves Ds 3 and Ds 4 . Consequently, the read window loss due to the temperature effect can be effectively recovered.
- the memory according to the present embodiment of the invention is a memory with MLCS.
- the memory employs a number of reference cells with reference threshold voltages having similar threshold voltage variations resulting from the temperature effect as the threshold voltage of the read memory cell.
- the reference currents and the read windows determined by the reference currents can be altered accordingly with the threshold voltage variations due to the temperature effect. Consequently, the memory according to the present embodiment of the invention is advantageously capable of effectively preventing the read window loss due to the temperature effect.
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Abstract
Description
- 1. Field of the Invention
- The invention relates in general to a memory, and more particularly to a memory capable of reducing sense window loss of sense currents due to temperature effect on threshold voltage of memory cells. The memory cells are the two-bit Nitride-based trapping storage flash cells
- 2. Description of the Related Art
- Non-volatile memory, such as flash memory, is widely used in various electronic products. Referring to
FIG. 1 , an illustration of a programmed threshold voltages distributions of a memory is shown. For example, the flash memory is a memory with multiple level cells (MLCS), which can be programmed to have four threshold voltage distributions shown as curves d1-d4 corresponding to two bits of data stored in each of the MLC. In a read operation of a selected MLC, the selected MLC has to be read with three different word line voltages to obtain three cell currents accordingly. For example, the three different word line voltages have the respective levels V1, V2, and V3. The three cell currents will be compared with a reference current, so as to obtain the data stored in the MLC. - In real cases, the threshold voltages of MLCS will be varied due to temperature effect. To be more specific, the MLCS will suffer from descents of threshold voltage when the surrounding temperature is raised and the amounts of descents are proportional to the levels of the threshold voltage. For example, the four threshold voltage distributions of MLCS in the memory can be shown as curves d1′-d4′. Thus, MLCS in the memory will suffer from read window loss due to the raised threshold voltages of the MLCS when the surrounding temperature is raised.
- The invention is directed to a memory with multiple level cells (MLCS). The memory employs a number of reference cells with reference threshold voltages having similar threshold voltage variations resulting from the temperature effect as a threshold voltage of a read memory cell. Thus, the reference currents and the read windows determined by the reference currents can be altered according to the threshold voltage variations due to the temperature effect. Consequently, in comparison with the conventional memory, the memory related to the invention can effectively prevent the read window loss due to the temperature effect.
- According to a first aspect of the present invention, a memory is provided. The memory includes a memory array, a sense amplifier, and a reference circuit. The memory array includes a memory cell. The sense amplifier includes a first terminal coupled to the memory cell and a second terminal. The reference circuit includes a first reference cell, a second reference cell, and a switch. The first reference cell has a first reference threshold voltage for providing a first reference current, based on a first reference word line voltage. The second reference cell has a second reference threshold voltage for providing a second reference current, based on a second reference word line voltage. The switch selectively provides one of the first and the second reference currents to the second terminal in response to a control signal. The first and the second reference word line voltages correspond to different voltage levels.
- According to a second aspect of the present invention, a memory is provided. The memory includes a memory array, a sense means, and a reference means. The memory array includes a memory cell. The sense means includes a first terminal, coupled to the memory cell, and a second terminal. The reference means comprises first current means, second current means, and a switch means. The first current means, referring to a first reference threshold voltage, provides a first reference current based on a first reference word line voltage. The second current means, referring to a second reference threshold voltage, provides a second reference current based on a second reference word line voltage. The switch means selectively provides one of the first and the second reference currents to the second terminal in response to a control signal. The first and the second reference word line voltages correspond to different voltage levels.
- The invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.
-
FIG. 1 (Prior art) is an illustration of a programmed threshold voltages distributions of a memory -
FIG. 2 is a block diagram of the memory according to an embodiment of the invention. -
FIG. 3 is an illustration of a programmed threshold voltages distribution of a memory. -
FIG. 4 is a detailed block diagram of a sense amplifier in thesense unit 18 and thereference circuit 20. - The memory according to an embodiment of the invention employs a number of reference cells with reference threshold voltages having similar threshold voltage variations resulting from the temperature effect as the threshold voltage of the read memory cell.
- Referring to
FIG. 2 , a block diagram of the memory according to the embodiment of the invention is shown. Thememory 1 is a MLC memory including arow decoder 12,Y multiplexers memory cell array 16, asense unit 18, areference circuit 20, and acontroller 22. Thememory cell array 16 includes numerous memory cells arranged in an M×N matrix, wherein M and N are natural numbers greater than 1. - Referring to
FIG. 3 , an illustration of a programmed threshold voltages distribution of a memory is shown. For example, each of the memory cells, which initially has a first state, can be programmed to have three other threshold voltage states indicating the values of two bits of data stored in each of the memory cells. Thus, the memory cells with the first state and programmed with the three other states form the respective four threshold voltage distributions plotted as curves Ds1, Ds2, Ds3, and Ds4. For example, the curves Ds1 to Ds4 indicate the threshold voltage distributions when the surrounding temperature of thememory 1 is at a first temperature. - The
row decoder 12 and theY multiplexer 14 a provide the corresponding word line voltages and bias voltages to at least a selected memory cell, so as to drive the memory cells providing cell currents. TheY multiplexer 14 b provides the cell current of the selected memory cell to thesense unit 18 so as to sense the data stored in the selected memory cell. For example, the selected memory cell is the memory cell T(i,j) with the coordinates (i,j) in thememory array 16, wherein i and j are natural numbers less than or equal to M and N, respectively. - Because the threshold voltages of memory cells can be programmed with more than two states, it can be obtained that more than one sense operations must be applied in a read operation to effectively obtain the threshold voltage state of a read memory cell and the data stored therein. For example, in order to obtain the data stored in the memory cell, the
controller 22 controls the operation of therow decoder 12 and theY multiplexers - In an example, the word line voltage Sw respectively has the levels Vw1, Vw2, and Vw3 in a first read operation, in a second read operation, and in a third read operation. Thus, in the first to the third read operations, the threshold voltage state of the memory cell T(i,j) and whether the threshold voltage of the memory cell T(i,j) is greater than the level Vw1, the level Vw2, and the level Vw3 can be effectively determined.
- Referring to
FIG. 4 , a detailed block diagram of a sense amplifier in thesense unit 18 and thereference circuit 20 is shown. For example, a sense amplifier SA included in thesense unit 18 is for sensing a cell current Icell provided by the memory cell T(i,j). The sense amplifier SA includes a first terminal coupled to the memory cell T(i,j) for receiving the cell current Icell and a second terminal coupled to thereference circuit 20 for receiving reference currents. - The
reference circuit 20 includes aswitch 41 and reference cells RT1, RT2, and RT3. The reference cells RT1 to RT3 are respectively programmed to reference threshold voltages Vthr1, Vthr2, and Vthr3. The reference cells RT1-RT3 respectively provide a reference current Iref1 based on a reference word line voltage Swr1 and the reference threshold voltage Vthr1, a reference current Iref2 based on a reference word line voltage Swr2 and the reference threshold voltage Vthr2, and a reference current Iref3 based on a reference word line voltage Swr3 and the reference threshold voltage Vthr3. For example, the reference word line voltages Swr1 to Swr3 respectively have the levels Vw1 to Vw3 and the reference threshold voltages Vthr1 to Vthr3 respectively have the levels Vw1 to Vw3. - In response to a control signal Sc provided by the
controller 22, theswitch 41 selectively provides one of the reference currents Iref1, Iref2, and Iref3 to the second terminal of the sense amplifier SA, e.g., in the first to the third read operations respectively. In other words, reference currents Iref1 to Iref3 are employed by the sense amplifier SA as the reference current in the first to the third read operations, respectively. For example, when thecontroller 22 controls the operation to read the memory cell T(i,j) with the word line voltage having the level Vw1, theswitch 41 is controlled by thecontroller 22 to select the reference current Iref1 as the reference current. In other words, when thecontroller 22 controls the operation to determine whether the memory cell T(i,j) belongs to the distributions Ds1 or Ds2, it is the reference current Iref1 being selected. - When the
controller 22 controls the operation to read the memory cell T(i,j) with the word line voltage having the levels Vw2 and Vw3, theswitch 41 is controlled by thecontroller 22 to respectively select the reference currents Iref2 and Iref3 as the reference current. In other words, the reference currents Iref2 and Iref3 are respectively selected by theswitch 41 when thecontroller 22 determines whether the memory cell T(i,j) belongs to the distributions Ds2 or Ds3 and belongs to the distributions Ds3 or Ds4. - When the threshold voltage of the memory cell T(i,j) is programmed with threshold voltage less than the level Vw2 (i.e. the memory cell T(i,j) has the threshold voltage distributions as indicated by the curves Ds1 or Ds2 in
FIG. 3 ), the level of threshold voltage of the memory cell T(i,j) is close to the level of the reference threshold voltage Vthr1 (i.e. the level Vw1). In addition, the threshold voltage variations of a memory cell due to the temperature effect are proportional to the threshold voltage level and threshold voltages with similar threshold voltage level correspond to similar threshold voltage variations. Thus, when the threshold voltage of the memory cell T(i,j) varies due to the temperature effect, the reference threshold voltage Vthr1 will have a similar threshold voltage variation and the reference current Iref1 will have a similar variation as the cell current Icell. - For example, when the reference threshold voltage Vthr1 is varied from the level of Vw1 to Vw1′ at a second temperature, the curves Ds1 and Ds2 representing the threshold voltage distributions are shifted to the left as indicated by the curves Ds1′ and Ds2′. The reference threshold voltage Vthr1 having the level Vw1 at the first temperature will shift left to the level Vw1′ at the second temperature. In addition, the reference threshold voltage Vthr1 serves as the threshold condition between the threshold voltage distributions shown as the curves Ds1 and Ds2. Consequently, the read window loss due to the temperature effect can be effectively recovered.
- When the threshold voltage of the memory cell T(i,j) is programmed with threshold voltage less than the level Vw3 but greater than the level Vw1 (i.e. the memory cell T(i,j) is in the threshold voltage distributions plotted as Ds2 or Ds3) and with threshold voltage greater than Vw2 (i.e. the memory cell T(i,j) is in the threshold voltage distribution plotted as Ds3 or Ds4), similar threshold voltage variations will take place on the reference threshold voltages Vthr2 and Vthr3 for respectively varied as levels Vw2′ and Vw3′. The reference threshold voltages Vthr2 and Vthr3, which respectively have the levels Vw2 and Vw3 at the first temperature, will respectively shift left to the levels Vw2′ and Vw3′ at the second temperature. In addition, the reference threshold voltages Vthr2 serves as the threshold condition between the threshold voltage distributions shown as the curves Ds2 and Ds3, and the reference threshold voltage Vthr3 serves as the threshold condition between the threshold voltage distributions shown as the curves Ds3 and Ds4. Consequently, the read window loss due to the temperature effect can be effectively recovered.
- The memory according to the present embodiment of the invention is a memory with MLCS. The memory employs a number of reference cells with reference threshold voltages having similar threshold voltage variations resulting from the temperature effect as the threshold voltage of the read memory cell. Thus, the reference currents and the read windows determined by the reference currents can be altered accordingly with the threshold voltage variations due to the temperature effect. Consequently, the memory according to the present embodiment of the invention is advantageously capable of effectively preventing the read window loss due to the temperature effect.
- While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
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US11011230B1 (en) * | 2020-03-26 | 2021-05-18 | Winbond Electronics Corp. | Memory device and operation method thereof |
CN113012739A (en) * | 2019-12-20 | 2021-06-22 | 华邦电子股份有限公司 | Memory device and operation method thereof |
CN113113062A (en) * | 2021-04-25 | 2021-07-13 | 中国电子科技集团公司第五十八研究所 | Magnetic random access memory based on 3T-3MTJ storage unit and reading method thereof |
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KR20170143125A (en) | 2016-06-20 | 2017-12-29 | 삼성전자주식회사 | Memory device including memory cell for generating reference voltage |
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US20070236999A1 (en) * | 2005-04-12 | 2007-10-11 | Yosuhiko Honda | Reference current generating circuit of nonvolatile semiconductor memory device |
US7639542B2 (en) * | 2006-05-15 | 2009-12-29 | Apple Inc. | Maintenance operations for multi-level data storage cells |
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CN113012739A (en) * | 2019-12-20 | 2021-06-22 | 华邦电子股份有限公司 | Memory device and operation method thereof |
US11011230B1 (en) * | 2020-03-26 | 2021-05-18 | Winbond Electronics Corp. | Memory device and operation method thereof |
CN113113062A (en) * | 2021-04-25 | 2021-07-13 | 中国电子科技集团公司第五十八研究所 | Magnetic random access memory based on 3T-3MTJ storage unit and reading method thereof |
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