CN113010106A - Bus multiplexing FLASH read-write system based on FPGA - Google Patents
Bus multiplexing FLASH read-write system based on FPGA Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
Abstract
A bus multiplexing FLASH read-write system based on FPGA comprises an FPGA read-write module, a DSP module and a FLASH module, wherein pins of the FPGA read-write module are respectively connected with an EMIF bus and a FLASH module of the DSP module, the FPGA read-write module receives an instruction sent by the DSP module and converts the instruction into an input signal of the FLASH module, and the FLASH module stores the input signal and supplies the input signal to the DSP module for reading.
Description
Technical Field
The invention relates to a bus multiplexing FLASH read-write system based on an FPGA, belonging to the field of data read-write control.
Background
The MT29F series FLASH of MICRO company adopts a data bus and address bus multiplexing design, cannot be controlled by the EMIF bus or other communication buses of DSP, needs DSP software to control pins to realize read-write time sequence, and only one byte is read and written at a time, so that the read-write efficiency is low, and the machine occupation time is long.
Disclosure of Invention
The technical problem solved by the invention is as follows: aiming at the problem that the prior art can not be controlled by an EMIF bus or other communication buses of a DSP and needs DSP software to control pins to realize read-write time sequence, the bus multiplexing type FLASH read-write system based on the FPGA is provided.
The technical scheme for solving the technical problems is as follows:
a bus multiplexing FLASH read-write system based on FPGA comprises an FPGA read-write module, a DSP module and a FLASH module, wherein pins of the FPGA read-write module are respectively connected with an EMIF bus of the DSP module and the FLASH module, the FPGA read-write module receives an instruction sent by the DSP module and converts the instruction into an input signal of the FLASH module, and the FLASH module stores the input signal and supplies the input signal to the DSP module for reading.
The DSP module comprises an EMIF bus, an address bus is more than 4 bits, and a data bus is 32 bits;
the point number of the FPGA read-write module is more than 100, and the built-in logic gate circuit is more than 1000;
the FLASH module is a model meeting the MT29F time sequence requirement.
The FPGA read-write module can automatically recognize read instructions and write instructions, and when the DSP module inputs the write instructions, the specific flow is as follows:
(1) receiving a write instruction written in by the DSP module;
(2) clearing the cs port;
(3) inputting 16-23 bit data in a write instruction into a data bus, writing 27bit data into a CLE port, writing 26bit data into an ALE port, and writing 24bit data into a we port line;
(4) pulling up the we port line after 10ns, and clearing the CLE port, the ALE port and the data bus after the next 10 ns;
(5) inputting 7-0 bit data of a write instruction into a data bus, writing 11bit data into a CLE port, writing 10bit data into an ALE port, and writing 8bit data into a we port line;
(6) pulling up the we port line after 10ns, and clearing the CLE port, the ALE port and the data bus after the next 10 ns;
(7) pulling up the cs port;
(8) the flow is terminated.
When the DSP module inputs a read instruction, the specific process is as follows:
(1) receiving a read instruction written by the DSP module, and determining the number of read instruction operations;
(2) judging whether the number of a reading counter of the FPGA reading and writing module is not less than the number of reading instruction operations, if not, entering a step (16), and if so, resetting the reading counter of the FPGA reading and writing module;
(3) resetting the re port count;
(4) pulling down the cs port and the re port;
(5) setting a re port as 1 after 10 ns;
(6) reading data in a data bus in the FLASH module, storing the data in an 8-bit register reg1, and adding 1 to a reading counter;
(7) pulling down the re port after 10 ns;
(8) setting the re port to be 1 after 10ns, reading data in a data bus in the FLASH module, storing the data in an 8-bit register reg2, and adding 1 to a reading counter;
(9) pulling down the re port after 10 ns;
(10) setting the re port to be 1 after 10ns, reading data in a data bus in the FLASH module, storing the data in an 8-bit register reg3, and adding 1 to a reading counter;
(11) pulling down the re port after 10 ns;
(12) setting the re port to be 1 after 10ns, reading data in a data bus in the FLASH module, storing the data in an 8-bit register reg4, and adding 1 to a reading counter;
(13) the cs port is pulled high;
(14) simultaneously writing the data in the registers reg1, reg2, reg3 and reg4 into a read register of the FPGA read-write module;
(15) reading the data of the read register through the DSP module, and returning to the step (2);
(16) the flow is terminated.
And adjusting the low level time lengths of signals of the we port line and the re port to be not less than 10ns according to the input clock period of the FPGA read-write module, and writing data into the ALE port and the CLE port for not less than 20 ns.
Compared with the prior art, the invention has the advantages that:
according to the bus multiplexing type FLASH read-write system based on the FPGA, 2-byte effective data can be written into FLASH through single DSP write operation, 4-byte data in the FLASH can be read through single DSP read operation, a new read-write system design and a new flow design are provided aiming at the defects of the prior art about MT29F series FLASH read design, the problem that the read-write time sequence cannot be realized by using an EMIF bus or other communication bus control of a DSP and a DSP software control pin is needed is solved, and the read-write efficiency is greatly improved.
Drawings
FIG. 1 is a schematic view of the read-write flow of the FLASH read-write system provided by the present invention;
FIG. 2 is a schematic structural diagram of a FLASH read-write system provided by the present invention;
Detailed Description
A bus multiplexing FLASH read-write system based on FPGA, aiming at the problem that MT29F series FLASH adopts the multiplexing design of data bus and address bus, cannot be controlled by the EMIF bus or other communication bus of DSP, needs DSP software to control pin to realize read-write time sequence in the prior art, realizes the purpose of improving read-write efficiency by the read-write system structure comprising FPGA read-write module, DSP module and FLASH module, the whole read-write system structure specifically comprises:
including FPGA read-write module, DSP module, FLASH module, FPGA read-write module pin is connected with EMIF bus, the FLASH module of DSP module respectively, and FPGA read-write module receives the instruction that the DSP module sent and converts FLASH module input signal into, and FLASH module stores and supplies the DSP module to read according to input signal, wherein:
the DSP module comprises an EMIF bus, an address bus is more than 4 bits, and a data bus is 32 bits; the point number of the FPGA read-write module is more than 100, and the built-in logic gate circuit is more than 1000; the FLASH module is a model satisfying the MT29F timing sequence requirement.
The read-write system comprises two working modes, namely a read mode and a write mode, wherein the overall working procedures of the read-write system are different in different working modes, and specifically, the read-write system comprises the following steps:
when the DSP module inputs a write instruction, the specific flow is as follows:
(1) receiving a write instruction written in by the DSP module;
(2) clearing the cs port;
(3) inputting 16-23 bit data in a write instruction into a data bus, writing 27bit data into a CLE port, writing 26bit data into an ALE port, and writing 24bit data into a we port line;
(4) pulling up the we port line after 10ns, and clearing the CLE port, the ALE port and the data bus after the next 10 ns;
(5) inputting 7-0 bit data of a write instruction into a data bus, writing 11bit data into a CLE port, writing 10bit data into an ALE port, and writing 8bit data into a we port line;
(6) pulling up the we port line after 10ns, and clearing the CLE port, the ALE port and the data bus after the next 10 ns;
(7) pulling up the cs port;
(8) the flow is terminated.
When the DSP module inputs a read instruction, the specific process is as follows:
(1) receiving a read instruction written by the DSP module, and determining the number of read instruction operations;
(2) judging whether the number of a reading counter of the FPGA reading and writing module is not less than the number of reading instruction operations, if not, entering a step (16), and if so, resetting the reading counter of the FPGA reading and writing module;
(3) resetting the re port count;
(4) pulling down the cs port and the re port;
(5) setting a re port as 1 after 10 ns;
(6) reading data in a data bus in the FLASH module, storing the data in an 8-bit register reg1, and adding 1 to a reading counter;
(7) pulling down the re port after 10 ns;
(8) setting the re port to be 1 after 10ns, reading data in a data bus in the FLASH module, storing the data in an 8-bit register reg2, and adding 1 to a reading counter;
(9) pulling down the re port after 10 ns;
(10) setting the re port to be 1 after 10ns, reading data in a data bus in the FLASH module, storing the data in an 8-bit register reg3, and adding 1 to a reading counter;
(11) pulling down the re port after 10 ns;
(12) setting the re port to be 1 after 10ns, reading data in a data bus in the FLASH module, storing the data in an 8-bit register reg4, and adding 1 to a reading counter;
(13) the cs port is pulled high;
(14) simultaneously writing the data in the registers reg1, reg2, reg3 and reg4 into a read register of the FPGA read-write module;
(15) reading the data of the read register through the DSP module, and returning to the step (2);
(16) the flow is terminated.
And adjusting the low level time lengths of signals of the we port line and the re port to be not less than 10ns according to the input clock period of the FPGA read-write module, and writing data into the ALE port and the CLE port for not less than 20 ns.
The following is further illustrated with reference to specific examples:
in this embodiment, a schematic diagram of the overall structure of the read-write system is shown in fig. 2, and in the FPGA connected as shown in fig. 2, the DSP writes read operation or write operation into the FLASH module, and the module writes information into the FLASH or reads information from the FLASH.
First, the DSP writes an instruction into FLASH. When the instruction bit31 is 1, the instruction is a write instruction, and the read-write module writes 2 bytes into the FLASH according to the instruction; when bit31 is 0, it is a read instruction, and the read-write module will read the data of the quantity for the DSP to read, and the whole flow is shown in FIG. 1;
when the read-write module identifies a write instruction, the module writes 16-23 bits of the write instruction (32 bits) into a data bus, 27 bits into CLE, 26 bits into ALE, and 24 bits into we line. After 10ns, the we line is pulled high, and after 10ns, CLE and ALE are carried out, and the data bus is cleared; the module puts 7-0 bits of the register into a data bus, 11 bits are written into CLE, 10 bits are written into ALE, and 8 bits are written into we line. After 10ns, the we line is pulled high, and after 10ns, CLE and ALE are carried out, the data bus is cleared, and the write operation is completed.
When the read-write module identifies a read instruction, a read counter of the read-write module is cleared, a re line is set to be at a low level, the re line is set to be at a high level after 10ns, and a reg1 register reads and latches FLASH data bus data; setting the re line to be at a low level after 10ns, setting the re line to be at a high level after 10ns, and reading FLASH data bus data by a reg2 register and latching; setting the re line to be at a low level after 10ns, setting the re line to be at a high level after 10ns, and reading FLASH data bus data by a reg3 register and latching; setting the re line to be at a low level after 10ns, setting the re line to be at a high level after 10ns, and reading FLASH data bus data by a reg4 register and latching; at the moment, the reading and writing module suspends the reading of the FLASH, and splices the contents of reg1, reg2, reg3 and reg4 into a 32-bit register; after the DSP reads the register, the read-write module continues to read the data in the FLASH until the read counter is greater than or equal to the value of the read instruction.
The module can reduce the number of DSP read-write machines, and leads the DSP to carry out data read-write while the DSP normally runs satellite positioning.
The above description is only for the best mode of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
The invention is not described in detail and is within the knowledge of a person skilled in the art.
Claims (5)
1. A bus multiplexing FLASH read-write system based on FPGA is characterized in that: the FPGA read-write module receives an instruction sent by the DSP module and converts the instruction into an input signal of the FLASH module, and the FLASH module stores the input signal and is read by the DSP module.
2. The FPGA-based bus multiplexing-type FLASH read-write system according to claim 1, characterized in that:
the DSP module comprises an EMIF bus, an address bus is more than 4 bits, and a data bus is 32 bits;
the point number of the FPGA read-write module is more than 100, and the built-in logic gate circuit is more than 1000;
the FLASH module is a model meeting the MT29F time sequence requirement.
3. The FPGA-based bus multiplexing-type FLASH read-write system according to claim 1, characterized in that:
the FPGA read-write module can automatically recognize read instructions and write instructions, and when the DSP module inputs the write instructions, the specific flow is as follows:
(1) receiving a write instruction written in by the DSP module;
(2) clearing the cs port;
(3) inputting 16-23 bit data in a write instruction into a data bus, writing 27bit data into a CLE port, writing 26bit data into an ALE port, and writing 24bit data into a we port line;
(4) pulling up the we port line after 10ns, and clearing the CLE port, the ALE port and the data bus after the next 10 ns;
(5) inputting 7-0 bit data of a write instruction into a data bus, writing 11bit data into a CLE port, writing 10bit data into an ALE port, and writing 8bit data into a we port line;
(6) pulling up the we port line after 10ns, and clearing the CLE port, the ALE port and the data bus after the next 10 ns;
(7) pulling up the cs port;
(8) the flow is terminated.
4. The FPGA-based bus multiplexing-type FLASH read-write system according to claim 3, characterized in that:
when the DSP module inputs a read instruction, the specific process is as follows:
(1) receiving a read instruction written by the DSP module, and determining the number of read instruction operations;
(2) judging whether the number of a reading counter of the FPGA reading and writing module is not less than the number of reading instruction operations, if not, entering a step (16), and if so, resetting the reading counter of the FPGA reading and writing module;
(3) resetting the re port count;
(4) pulling down the cs port and the re port;
(5) setting a re port as 1 after 10 ns;
(6) reading data in a data bus in the FLASH module, storing the data in an 8-bit register reg1, and adding 1 to a reading counter;
(7) pulling down the re port after 10 ns;
(8) setting the re port to be 1 after 10ns, reading data in a data bus in the FLASH module, storing the data in an 8-bit register reg2, and adding 1 to a reading counter;
(9) pulling down the re port after 10 ns;
(10) setting the re port to be 1 after 10ns, reading data in a data bus in the FLASH module, storing the data in an 8-bit register reg3, and adding 1 to a reading counter;
(11) pulling down the re port after 10 ns;
(12) setting the re port to be 1 after 10ns, reading data in a data bus in the FLASH module, storing the data in an 8-bit register reg4, and adding 1 to a reading counter;
(13) the cs port is pulled high;
(14) simultaneously writing the data in the registers reg1, reg2, reg3 and reg4 into a read register of the FPGA read-write module;
(15) reading the data of the read register through the DSP module, and returning to the step (2);
(16) the flow is terminated.
5. The FPGA-based bus multiplexing-type FLASH read-write system according to claim 1, characterized in that:
and adjusting the low level time lengths of signals of the we port line and the re port to be not less than 10ns according to the input clock period of the FPGA read-write module, and writing data into the ALE port and the CLE port for not less than 20 ns.
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