CN113760813A - Method for starting and controlling digital signal processor - Google Patents
Method for starting and controlling digital signal processor Download PDFInfo
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- CN113760813A CN113760813A CN202111008346.2A CN202111008346A CN113760813A CN 113760813 A CN113760813 A CN 113760813A CN 202111008346 A CN202111008346 A CN 202111008346A CN 113760813 A CN113760813 A CN 113760813A
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- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000013500 data storage Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000001960 triggered effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
Abstract
A method for starting and controlling a digital signal processor relates to the technical field of digital signal processing systems and comprises a DSP, an FPGA and a FLASH memory for storing external data, wherein the DSP is correspondingly communicated and connected with the FPGA through an EMIF interface, the FPGA is correspondingly data-connected with the FLASH memory through a memory bus, and the FPGA is integrated with a writing module, a reading module, a resetting module, a memory writing module, a memory reading module and a memory erasing module; the invention is realized by adopting the FPGA, and has strong universality and good portability; under the condition of not changing the DSP bootstrap startup time sequence, the data read-write control of the DSP to the FLASH memory is realized, and the bus interface of the memory can be flexibly changed.
Description
Technical Field
The invention relates to the technical field of digital signal processing systems, in particular to a method for starting and controlling a digital signal processor.
Background
Usually, a Digital Signal Processor (DSP) of a digital signal processing system is started in a bootstrap mode, namely, the DSP automatically loads data from a FLASH memory for starting through an external storage bus interface (EMIF) according to a fixed interface and a time sequence designed by a device manufacturer; the EMIF interface is a parallel bus interface, so that the interface and data are limited more, and the type selection and expansion of devices are not facilitated.
Disclosure of Invention
In order to overcome the defects in the background art, the invention discloses a method for starting control of a digital signal processor.
In order to achieve the purpose, the invention adopts the following technical scheme:
a method for starting and controlling a digital signal processor comprises a DSP, an FPGA and a FLASH memory for storing external data, wherein the DSP is correspondingly communicated and connected with the FPGA through an EMIF interface, the FPGA is correspondingly connected with the FLASH memory through a memory bus, the FPGA is integrated with a writing module, a reading module, a resetting module, a memory writing module, a memory reading module and a memory erasing module, and the DSP comprises the following operations for the FLASH memory:
data erasure:
the DSP sends a data erasing command containing address information through an EMIF interface, the FPGA writing module receives and analyzes the command and the address information, drives the memory erasing module and erases the FLASH memory;
data writing:
the DSP sends a data writing command containing address information through an EMIF interface, the FPGA writing module receives and analyzes the command and the address information, drives the memory erasing module and executes writing into the FLASH memory;
data reading is divided into two modes:
the first one is a bootstrap starting mode of the DSP, the system is powered on, the FPGA adopts a pre-reading mode, data is pre-fetched into a dual-port RAM cache arranged in the FPGA from external data storage corresponding to an address 0, the cache is realized by using a block RAM of the FPGA, meanwhile, before the RAM cache prepares the data, a reset module controls a reset pin of the DSP to enable the DSP not to be started, and after a feedback signal of a reading module is received, the reset state of the DSP is immediately released to trigger the DSP bootstrap driving;
the second is an application program data reading mode, when the user program runs, the user program controls the data reading time sequence, the DSP firstly sends a data reading command to the reading module, the data reading command comprises the initial address and the length information of the data to be read, after the reading module analyzes the command, a packet of data is taken out from the FLASH memory according to the command and stored in an FIFO buffer arranged in the reading module, before the data in the FIFO is ready, the reading module feeds back an rd _ ready signal to the DSP through a flag bit, and the DSP inserts the waiting time or continuously reads the data according to the feedback signal.
Preferably, the EMIF interface includes a data bus ED, an address bus EA, a chip select signal/CE, a write enable signal/WR, a read enable signal/RE, an output enable signal/OE, an EMIF clock output CLKOUT, and a status signal READY; the EMIF interface comprises a data bus ED, an address bus EA, a chip selection signal/CE, a write enable signal/WR, a read enable signal/RE, an output enable signal/OE, an EMIF clock output CLKOUT and a status signal READY; the data bus ED is used for transmitting address and data information to the FPGA functional module; the chip selection signal/CE and the write enable signal/WR are combined to trigger the write module; chip selection signal/CE, read enable signal/RE, output enable signal/OE combination to trigger the read module; CLKOUT is used for synchronizing clock domains between the DSP and the FPGA interface; the READY signal is used for transmitting data state information of the DSP and the FPGA.
Preferably, when the data is erased, the memory erasing module monitors the state of the FLASH memory in the erasing process, before the erasing operation is not completed, a wr _ ready signal is fed back to the FPGA writing module through the flag bit and is transmitted to the DSP, and the DSP inserts the waiting time or performs the next operation according to the feedback signal.
Preferably, during data writing operation, the memory erasing module comprises a data cache for solving the problem of speed mismatching between the DSP and the FLASH memory, and is realized by using a block RAM of the FPGA.
Preferably, in the DSP boot-strap start mode, the timing for reading data by the DSP is performed according to the timing for solidifying the device manufacturer, the start address starts from 0 address, and the length of the read data is 1k to 64 k.
Preferably, the FLASH memory is a parallel port data memory, an SPI interface data memory or an I2C interface data memory, and the FPGA is integrated with a parallel bus interface in data connection with the parallel port data memory, an SPI bus interface in data connection with the SPI interface data memory, and an I2C bus interface in data connection with the I2C interface data memory.
Due to the adoption of the technical scheme, the invention has the following beneficial effects:
the method for starting and controlling the digital signal processor is realized by adopting the FPGA, and has strong universality and good portability; under the condition of not changing the DSP bootstrap startup time sequence, the data read-write control of the DSP to the FLASH memory is realized, and the bus interface of the memory can be flexibly changed.
Drawings
FIG. 1 is a functional block diagram of the present invention;
FIG. 2 is a diagram of the interface connection between the DSP and the FPGA;
FIG. 3 is a diagram of the interface connection between the FPGA and the FLASH memory.
Detailed Description
The present invention will be explained in detail by the following embodiments, and the purpose of disclosing the invention is to protect all technical improvements within the scope of the present invention, in the description of the present invention, it should be understood that if there is an orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "left", "right", etc., it is only corresponding to the drawings of the present application, and it is convenient to describe the present invention, and it is not intended to indicate or imply that the referred device or element must have a specific orientation.
With reference to fig. 1 to 3, a method for starting control of a digital signal processor comprises a DSP, an FPGA and a FLASH memory for storing external data, wherein the DSP is in corresponding communication connection with the FPGA through an EMIF interface, the FPGA is in corresponding data connection with the FLASH memory through a memory bus, and the FPGA is integrated with a write module, a read module, a reset module, a memory write module, a memory read module and a memory erase module; the write module is used for realizing the analysis of the write operation time sequence of the DSP data bus, caching data and enabling the memory erasing module or the memory write module; the reading module is used for realizing the analysis of the DSP data bus reading operation time sequence, caching data and enabling the memory erasing module or the memory reading module; the reset module is used for resetting and controlling the DSP after the FPGA prepares DSP starting program data after the system is powered on; the memory writing module is used for writing the DSP bus data cached by the writing module according to the control mode of the memory bus; the memory reading module is used for analyzing the DSP bus address information according to the reading module, reading corresponding data from the FLASH memory and sending the data to the reading module; the memory erasing module is used for realizing erasing control on FLASH memory data; the EMIF interface comprises a data bus ED, an address bus EA, a chip selection signal/CE, a write enable signal/WR, a read enable signal/RE, an output enable signal/OE, an EMIF clock output CLKOUT and a status signal READY; the data bus ED is used for transmitting address and data information to the FPGA functional module; the chip selection signal/CE and the write enable signal/WR are combined to trigger the write module; chip selection signal/CE, read enable signal/RE, output enable signal/OE combination to trigger the read module; CLKOUT is used for synchronizing clock domains between the DSP and the FPGA interface; the READY signal is used for transmitting data state information of the DSP and the FPGA;
the DSP to FLASH memory comprises the following operations:
data erasure:
before the DSP writes data into the FLASH memory, the data in the corresponding area must be erased; the DSP sends a data erasing command containing address information through an EMIF interface; the FPGA writing module receives and analyzes the command and the address information, drives the memory erasing module to erase the FLASH memory, the memory erasing module monitors the state of the FLASH memory in the erasing process, before the erasing operation is not completed, a wr _ ready signal is fed back to the FPGA writing module through a flag bit and is transmitted to the DSP, and the DSP inserts the waiting time or carries out the next operation according to the feedback signal;
data writing:
when the DSP is about to write data into the FLASH memory, the DSP sends a data writing command containing address information through an EMIF interface; the FPGA writing module receives and analyzes the command and the address information, drives the memory erasing module and executes the writing of the FLASH memory; the memory erasing module comprises a data cache, is realized by using a block RAM of the FPGA, and can solve the problem of the speed mismatching of the DSP and the FLASH memory through the data cache;
data reading is divided into two modes:
the first is a bootstrap starting mode of the DSP, the system is powered on, the FPGA adopts a pre-reading mode, data is pre-fetched into a dual-port RAM cache arranged in the FPGA from an external data storage corresponding to an address 0, the cache is realized by using a block RAM of the FPGA, the DSP can be ensured to read correct and complete data, meanwhile, before the RAM cache prepares the data, a reset module controls a reset pin of the DSP to enable the DSP not to be started, and after a feedback signal of a reading module is received, the reset state of the DSP is immediately released, and the DSP bootstrap drive is triggered; when the DSP bootstrap starting mode is adopted, the time sequence of reading data by the DSP is carried out according to the time sequence solidified by a device manufacturer, the initial address starts from 0 address, and the length of the read data is 1 k-64 k;
the second is an application program data reading mode, when the user program runs, the user program controls the data reading time sequence, the address and the length of the read data are burst and uncertain, the starting is arbitrary, and the length of the read data is also arbitrary; the DSP sends a data reading command to the reading module, the data reading command comprises a data starting address to be read and length information, the reading module analyzes the command, then takes out a packet of data from the FLASH memory according to the command and stores the packet of data in an FIFO buffer arranged in the reading module, before the data in the FIFO is ready, the reading module feeds back rd _ ready signals to the DSP through a zone bit, and the DSP inserts waiting time or continuously reads data according to the feedback signals.
The method for starting and controlling the digital signal processor comprises the steps that when a system is powered on, an FPGA adopts a pre-reading mode, data are pre-fetched into a dual-port RAM cache arranged in the FPGA from an external data storage corresponding to a 0 address, the cache is realized by using a block RAM of the FPGA, the DSP can be guaranteed to be read correctly and completely, meanwhile, before the RAM cache prepares the data, a reset module controls a reset pin of the DSP to enable the DSP not to be started, and after a feedback signal of a reading module is received, the reset state of the DSP is immediately released, and the DSP bootstrap drive is triggered; the user program controls the data reading time sequence, the DSP sends a data reading command to the reading module, the data reading command comprises a data starting address to be read and length information, the reading module analyzes the command and then takes out a packet of data from the FLASH memory according to the command and stores the packet of data in an FIFO buffer arranged in the reading module, the reading module feeds an rd _ ready signal back to the DSP through a flag bit before the data in the FIFO buffer is ready, and the DSP inserts waiting time or continuously reads data according to the feedback signal.
The invention is not described in detail in the prior art, and it is apparent to a person skilled in the art that the invention is not limited to details of the above-described exemplary embodiments, but that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics thereof; the present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein, and any reference signs in the claims are not intended to be construed as limiting the claim concerned.
Claims (6)
1. A method for starting and controlling a digital signal processor comprises a DSP, an FPGA and a FLASH memory for storing external data, wherein the DSP is correspondingly communicated and connected with the FPGA through an EMIF interface, the FPGA is correspondingly connected with the FLASH memory through a memory bus, and the FPGA is integrated with a writing module, a reading module, a resetting module, a memory writing module, a memory reading module and a memory erasing module, and is characterized in that: the DSP to FLASH memory comprises the following operations:
data erasure:
the DSP sends a data erasing command containing address information through an EMIF interface, the FPGA writing module receives and analyzes the command and the address information, drives the memory erasing module and erases the FLASH memory;
data writing:
the DSP sends a data writing command containing address information through an EMIF interface, the FPGA writing module receives and analyzes the command and the address information, drives the memory erasing module and executes writing into the FLASH memory;
data reading is divided into two modes:
the first one is a bootstrap starting mode of the DSP, the system is powered on, the FPGA adopts a pre-reading mode, data is pre-fetched into a dual-port RAM cache arranged in the FPGA from external data storage corresponding to an address 0, the cache is realized by using a block RAM of the FPGA, meanwhile, before the RAM cache prepares the data, a reset module controls a reset pin of the DSP to enable the DSP not to be started, and after a feedback signal of a reading module is received, the reset state of the DSP is immediately released to trigger the DSP bootstrap driving;
the second is an application program data reading mode, when the user program runs, the user program controls the data reading time sequence, the DSP firstly sends a data reading command to the reading module, the data reading command comprises the initial address and the length information of the data to be read, after the reading module analyzes the command, a packet of data is taken out from the FLASH memory according to the command and stored in an FIFO buffer arranged in the reading module, before the data in the FIFO is ready, the reading module feeds back an rd _ ready signal to the DSP through a flag bit, and the DSP inserts the waiting time or continuously reads the data according to the feedback signal.
2. The method of digital signal processor startup control of claim 1, characterized by: the EMIF interface comprises a data bus ED, an address bus EA, a chip selection signal/CE, a write enable signal/WR, a read enable signal/RE, an output enable signal/OE, an EMIF clock output CLKOUT and a status signal READY; the EMIF interface comprises a data bus ED, an address bus EA, a chip selection signal/CE, a write enable signal/WR, a read enable signal/RE, an output enable signal/OE, an EMIF clock output CLKOUT and a status signal READY; the data bus ED is used for transmitting address and data information to the FPGA functional module; the chip selection signal/CE and the write enable signal/WR are combined to trigger the write module; chip selection signal/CE, read enable signal/RE, output enable signal/OE combination to trigger the read module; CLKOUT is used for synchronizing clock domains between the DSP and the FPGA interface; the READY signal is used for transmitting data state information of the DSP and the FPGA.
3. The method of digital signal processor startup control of claim 1, characterized by: when data is erased, the memory erasing module monitors the state of the FLASH memory in the erasing process, before the erasing operation is not completed, a wr _ ready signal is fed back to the FPGA writing module through the flag bit and is transmitted to the DSP, and the DSP inserts waiting time or carries out the next operation according to the feedback signal.
4. The method of digital signal processor startup control of claim 1, characterized by: when data is written in, the memory erasing module comprises a data cache for solving the problem of mismatching of the speeds of the DSP and the FLASH memory, and is realized by using a block RAM of the FPGA.
5. The method of digital signal processor startup control of claim 1, characterized by: when the DSP bootstrap starts the mode, the time sequence of reading data by the DSP is carried out according to the time sequence solidified by a device manufacturer, the initial address starts from 0 address, and the length of the read data is 1 k-64 k.
6. The method of digital signal processor startup control of claim 1, characterized by: the FLASH memory is a parallel port data memory, an SPI interface data memory or an I2C interface data memory, the FPGA is integrated with a parallel bus interface in data connection with the parallel port data memory, an SPI bus interface in data connection with the SPI interface data memory and an I2C bus interface in data connection with the I2C interface data memory.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117591454A (en) * | 2024-01-19 | 2024-02-23 | 成都谐盈科技有限公司 | System and method for realizing mocb on EMif bus FPGA |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0901081A2 (en) * | 1997-07-08 | 1999-03-10 | Texas Instruments Inc. | A digital signal processor with peripheral devices and external interfaces |
| CN103678728A (en) * | 2013-11-25 | 2014-03-26 | 北京航空航天大学 | High-speed data recording system based on FPGA+DSP framework and establishment method thereof |
| CN104298634A (en) * | 2014-09-24 | 2015-01-21 | 四川九洲电器集团有限责任公司 | Data transmission system based on FPGA and DSP |
| CN104750644A (en) * | 2015-04-20 | 2015-07-01 | 哈尔滨工业大学 | DSP EMIF reading-writing time sequence and FPGA AVALON reading-writing time sequence conversion method |
| CN109446126A (en) * | 2018-10-17 | 2019-03-08 | 天津津航计算技术研究所 | DSP and FPGA high-speed communication system and method based on EMIF bus |
| CN113010106A (en) * | 2021-02-25 | 2021-06-22 | 北京遥测技术研究所 | Bus multiplexing FLASH read-write system based on FPGA |
-
2021
- 2021-08-30 CN CN202111008346.2A patent/CN113760813A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0901081A2 (en) * | 1997-07-08 | 1999-03-10 | Texas Instruments Inc. | A digital signal processor with peripheral devices and external interfaces |
| CN103678728A (en) * | 2013-11-25 | 2014-03-26 | 北京航空航天大学 | High-speed data recording system based on FPGA+DSP framework and establishment method thereof |
| CN104298634A (en) * | 2014-09-24 | 2015-01-21 | 四川九洲电器集团有限责任公司 | Data transmission system based on FPGA and DSP |
| CN104750644A (en) * | 2015-04-20 | 2015-07-01 | 哈尔滨工业大学 | DSP EMIF reading-writing time sequence and FPGA AVALON reading-writing time sequence conversion method |
| CN109446126A (en) * | 2018-10-17 | 2019-03-08 | 天津津航计算技术研究所 | DSP and FPGA high-speed communication system and method based on EMIF bus |
| CN113010106A (en) * | 2021-02-25 | 2021-06-22 | 北京遥测技术研究所 | Bus multiplexing FLASH read-write system based on FPGA |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117591454A (en) * | 2024-01-19 | 2024-02-23 | 成都谐盈科技有限公司 | System and method for realizing mocb on EMif bus FPGA |
| CN117591454B (en) * | 2024-01-19 | 2024-04-23 | 成都谐盈科技有限公司 | Mocb implementation system and method based on emif bus FPGA |
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