CN104834619B - A kind of I2C bus circuit, implementation method and electronic equipment - Google Patents
A kind of I2C bus circuit, implementation method and electronic equipment Download PDFInfo
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- CN104834619B CN104834619B CN201510214495.2A CN201510214495A CN104834619B CN 104834619 B CN104834619 B CN 104834619B CN 201510214495 A CN201510214495 A CN 201510214495A CN 104834619 B CN104834619 B CN 104834619B
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Abstract
The invention discloses a kind of I2C bus circuit, implementation method and electronic equipment, which includes: as the first host of main equipment and the second host and as the slave from equipment；It is equipped between I2C bus first interface I2C1, the I2C1 of the first host, the I2C1 of the second host and a slave I2C1 and connects on first host and the second host and a slave；I2C bus second interface I2C2 is further respectively had on first host and the second host, is connected between the I2C2 of the first host and the I2C2 of the second host；I2C2 of first host through the first host sends control instruction to the I2C2 of the second host, to realize the I2C1 of the first host and one slave of the second host time-sharing multiplex.This I2C bus circuit through the invention realizes time-sharing multiplex mechanism, and the transimission and storage of data is realized in effective management of data flow, while facilitating the debugging and upgrading in system later period.
Description
Technical field
The present invention relates to electronic circuit technology fields, and in particular to a kind of I2C bus circuit, implementation method and electronics are set
It is standby.
Background technique
In the circuit of the prior art, the configuration information of system and debugging upgrade procedure are all offline burning modes, it is this from
Line burning mode needs a large amount of tool equipment cooperation to complete burning, and needs to power off after the completion of information burning and read again with data
Equipment etc. is taken to connect, complicated for operation, higher cost；And online burning mode is at low cost compared to offline burning mode, does not need to break
Electrical connection, it is easy to operate, but there is data storage and the data collision read and later period debugging in online burning mode
Upgrade inconvenient problem, therefore needs one kind and be able to solve data collision and debugging upgrading inconvenience in online burning mode
The technical solution of problem.
Summary of the invention
The present invention provides a kind of I2C bus circuit, implementation method and electronic equipments to solve online burning pattern count
According to the problem that conflict and debugging upgrading are inconvenient.
In order to achieve the above objectives, the technical scheme is that being achieved:
According to an aspect of the present invention, a kind of I2C bus circuit is provided, which includes: as main equipment
The first host and the second host and as the slave from equipment；
I2C bus first interface I2C1 is equipped on first host and the second host and a slave, the first host
It is connected between I2C1, the I2C1 of the second host and the I2C1 of a slave；
I2C bus second interface I2C2, the I2C2 of the first host and are further respectively had on first host and the second host
It is connected between the I2C2 of two hosts；
I2C2 of first host through the first host to the I2C2 of the second host send control instruction, with realize the first host and
The I2C1 of second host time-sharing multiplex, one slave.
Optionally, I2C bus circuit further includes third host；
Third host is equipped with I2C bus first interface I2C1, the I2C1 and slave of the I2C1 of the first host, third host
I2C1 between connect；
Be additionally provided with I2C bus second interface I2C2 on third host, the I2C2 of the I2C2 of the first host and third host it
Between connect；
I2C2 of first host through the first host sends control instruction to the I2C2 of the I2C2 of the second host, third host,
To realize the I2C1 of the first host, the second host, one slave of third host time-sharing multiplex.
Optionally, the USB interface for connecting USB connector is additionally provided on the first host；
First host, for by USB interface receive USB connector transmission come debugging upgrade command and debugging upgrade journey
Sequence, and will be debugged in upgrade procedure write-in slave according to debugging upgrade command.
Optionally, the first host is micro-control unit MCU；
Second host is mobile terminal high-definition audio and video standard interface MHL receiver；
One slave is Electrically Erasable Programmable Read-Only Memory EEPROM.
Optionally, the first host MCU, the I2C2 interface through the first host is main to second after detecting debugging upgrade command
The I2C2 interface of machine MHL receiver sends control instruction, so that the second host MHL receiver pause access slave EEPROM；With
And
The I2C1 interface of the first host MCU is hung up after detecting the instruction that debugging upgrade procedure is completed, it is main by first
The I2C2 interface of machine MCU is configured to I2C mouthfuls, while sending and controlling to the I2C2 interface of the second host MHL receiver through I2C2 interface
System instruction restores access slave EEPROM so that the I2C1 interface of the second host MHL receiver is configured to I2C mouthfuls.
Optionally, the first host MCU is for being written configuration information into slave EEPROM；
Slave EEPROM is used for storage configuration information；
Second host MHL receiver is for reading configuration information from slave EEPROM.
Optionally, the configuration information stored in slave EEPROM includes: audio-video source format information；
Second host MHL receiver, for receiving the audio-video source of external transmission and reading sound from slave EEPROM
Video source format information, using in slave EEPROM read audio-video source format information received audio-video source is judged,
And it is handled accordingly according to judging result.
According to another aspect of the present invention, a kind of electronic equipment is additionally provided, which includes: such as the present invention one
The I2C bus circuit of a aspect.
According to another aspect of the invention, a kind of implementation method of I2C bus circuit is provided, this method comprises:
It is chosen in circuit as the first host of main equipment and the second host and as from one slave of equipment；
I2C bus first interface I2C1 is set on the first host and the second host and a slave respectively, it is main by first
It is connected between the I2C1 of machine, the I2C1 of the second host and the I2C1 of a slave；
I2C bus second interface I2C2 is set on the first host and the second host respectively, the first host and second is main
The I2C2 of machine is connected；I2C2 using the first host through the first host sends control instruction to the I2C2 of the second host, with
Realize the I2C1 of one slave of the first host and the second host time-sharing multiplex.
Optionally, this method further include: the USB interface for connecting USB connector is additionally provided on the first host；
Using the first host USB interface receive USB connector transmit come debugging upgrade command and debug upgrade procedure,
And it will be debugged in upgrade procedure write-in slave according to debugging upgrade command；And micro-control unit MCU is chosen as the first master
Machine；
Mobile terminal high-definition audio and video standard interface MHL receiver is chosen as the second host；
Electrically Erasable Programmable Read-Only Memory EEPROM is chosen as a slave.
The beneficial effects of the present invention are: technical solution of the present invention as the first host of main equipment and second by that will lead
It machine and is connected as the slave from equipment by I2C bus first interface I2C1, while by as main equipment
One host and the second host are connected by I2C bus second interface I2C2, are sent and are controlled from the first host to the second host
The mode of instruction realizes the I2C1 bus interface of two one slaves of host time-sharing multiplex, solves number when program online burning
According to collision problem, the first host or the second host can communicate the transimission and storage for realizing data with slave, in addition, online burn
Record also omits the recording device of offline burning, saves cost, enhances the stability of system.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of I2C bus circuit of one embodiment of the invention；
Fig. 2 is a kind of structural schematic diagram of I2C bus circuit of another embodiment of the invention；
Fig. 3 is a kind of I2C bus circuit implementation method flow chart of one embodiment of the invention；
Fig. 4 is the block diagram of a kind of electronic equipment of one embodiment of the invention.
Specific embodiment
Core of the invention thought is: aiming at the problems existing in the prior art, utilizing I2C (Inter-Integrated
Circuit) the characteristics of bus, a kind of time-sharing multiplex mechanism based on I2C bus is proposed, two main one is solved and exists from system
Reading data and storage collision problem, data flow is effectively managed, at the same facilitate the system later period upgrade and debugging.
I2C bus is a kind of universal serial bus of twin wire, for connecting microcontroller and its peripheral equipment.It is one kind of synchronous communication
The advantages that special shape has interface line few, and control mode is simple, and device packing forms are small, and traffic rate is higher.I2C bus
Information is transmitted between the device for being connected to bus by serial data (SDA) line and serial clock (SCL) line.The embodiment of the present invention
In time-sharing multiplex refer to the first moment by the first host access a slave carry out data write-in work, the second moment is by second
Host accesses the read work that a slave carries out data, two same slaves of host time-sharing multiplex, so as to avoid data collision
Problem.Realization access switching can be controlled when specific implementation by the first host.
Fig. 1 is a kind of structural schematic diagram of I2C bus circuit of one embodiment of the invention, referring to Fig. 1, of the invention this
Planting I2C bus circuit includes:
As the first host 101 of main equipment and the second host 102 and as the slave 103 from equipment；
It is equipped with I2C bus first interface I2C1 on first host 101 and the second host 102 and a slave 103, first
It is connected between the I2C1 of host 101, the I2C1 of the second host 102 and the I2C1 of a slave 103；
I2C bus second interface I2C2 is further respectively had on first host 101 and the second host 102, the first host 101
It is connected between I2C2 and the I2C2 of the second host 102；
I2C2 of first host 101 through the first host 101 sends control instruction to the I2C2 of the second host 102, to realize
The I2C1 of one slave 103 of first host 101 and 102 time-sharing multiplex of the second host.
In the present embodiment, the first host 101 is micro-control unit MCU, and the second host 102 is mobile terminal high-definition audio and video
Standard interface MHL receiver, a slave 103 are Electrically Erasable Programmable Read-Only Memory EEPROM.Wherein, MHL is a kind of connection
The audio-visual standard interface of portable consumer electronic device can receive the audio-video number of external audio-video source transmission by the interface
According to the second host MHL receiver has the advantages that required transmission line is few and stability is good, but the second host MHL receiver
Chip do not have fixed storage function, when power-off, can lose data, and the second host MHL receiver passes through one slave of access
EEPROM obtains configuration information.Slave EEPROM in the present embodiment is the storage medium that data are not lost after a kind of power down,
EEPROM can wipe existing information on computers or on special equipment, reprogram.It should be noted that the selection of slave needs
The size of data for considering host and configuration information upgrading ascending order, due to the configuration of MHL receiver needs in the present embodiment
The data such as information and MCU system debugging upgrade procedure are less big, so selecting EEPROM as slave, in other of the invention
Slave can be erasable programmable EPROM or other ROM memories in embodiment.
In addition, in one embodiment of the invention, I2C bus circuit includes the first host and the second host is used as from setting
It is standby, and the second host is MHL receiver, for receiving audio/video information.But in other embodiments of the invention, I2C
Bus circuit can also include third host, third host be equipped with I2C bus first interface I2C1, the I2C1 of the first host,
It is connected between the I2C1 of third host and the I2C1 of slave；
Be additionally provided with I2C bus second interface I2C2 on third host, the I2C2 of the I2C2 of the first host and third host it
Between connect；
I2C2 of first host through the first host sends control instruction to the I2C2 of the I2C2 of the second host, third host,
To realize the I2C1 of the first host, second host, one slave of third host time-sharing multiplex.
Third host is used to receive the information of other types data, and under the control of the first host, time-sharing multiplex one from
The I2C1 bus interface of machine, at this point, the I2C1 interface of one the first host, the second host and third host time-sharing multiplex slave,
First host is responsible for writing data to slave, when the first host writes data, other two hosts (the second host and third host)
All pause access slaves.After the write operation is completed, the first host controls one of host (the second host or third host) and visits
Ask that slave reads data, another host (the second host or third host) pause access slave.Specific second or third master
Machine access slave can be determined by the application that the second host or third host are realized, when the second host or third host need to carry out
Read data operation when, the second host or third host are specifically controlled by the first host and access slave.
In circuit shown in Fig. 1, the first host MCU passes through I2C1 bus for system configuration information programming to slave
In EEPROM, the second host MHL receiver reads the system configuration in memory by I2C1 bus access slave EEPROM
Information, the first host MCU control the I2C2 of the second host MHL receiver by I2C2 to realize that two hosts pass through I2C1 bus point
Shi Fuyong accesses the function of the I2C1 bus interface of slave EEPROM, solves the first host and the second host while accessing slave
Data collision problem, also save hardware cost and improve the stability of system.
Fig. 2 is a kind of structural schematic diagram of I2C bus circuit of another embodiment of the invention；On first host 101 also
Equipped with the USB interface for connecting USB connector；
First host 101 be used for by USB interface receive USB connector transmission come debugging upgrade command and debugging upgrading
Program, and will be debugged in upgrade procedure write-in slave 103 according to debugging upgrade command.
First host MCU101, the I2C2 interface through the first host MCU101 is to second after receiving debugging upgrade command
The I2C2 interface of host MHL receiver 102 sends control instruction, so that the pause access of the second host MHL receiver 102
EEPROM103；And hang up the I2C1 interface of MCU101 after detecting the instruction that debugging upgrade procedure is completed, by first
The I2C2 interface of host MCU101 is configured to I2C mouthfuls, while connecing through I2C2 interface to the I2C2 of the second host MHL receiver 102
Mouth sends control instruction, so that the I2C1 interface of the second host MHL receiver is configured to I2C mouthfuls, restores access EEPROM103.
In the present embodiment, the first host MCU101 is for configuration information to be written into EEPROM103；Slave EEPROM103
For storage configuration information；Second host MHL receiver 102 is for reading configuration information from slave EEPROM103.Slave
The configuration information stored in EEPROM103 includes: audio-video source format information；Second host MHL receiver 102 is also used to receive
The audio-video source and the reading audio-video source format information from slave EEPROM103 of outside transmission, utilize slave EEPROM103
Middle reading audio-video source format information judges received audio-video source, and is handled accordingly according to judging result.Specifically
The course of work be that, when I2C circuit works normally, the second host MHL receiver is by detecting the input of external audio-video source
And after input format, by I2C1 bus access slave EEPROM, the format of the externally input video source of matching judgment with from
Whether the configuration information stored in machine EEPROM is consistent.If consistent, the second host MHL receiver continues audio-video source
Transmission is further handled to the back-end with doing；If inconsistent, the second host MHL receiver cuts off video source not backward
End transmission.Here only in an embodiment of the invention, when having chosen MHL receiver as a host by read from
The configuration information stored in machine carries out judgement treatment process, when choosing one as I2C bus circuit of the present invention of other devices
It may not be the judgement to audio-video source format when host, should be deposited according in the function and slave that other devices can be realized
The configuration information of storage does specific processing, without limitation.
Work as the later period, when system needs DFU (Device Firmware Upgrade) to debug and upgrade, the first host MCU is logical
It is main to second by I2C2 bus interface after crossing the DFU debugging and upgrade command that USB interface detects that USB connector transmission comes
Machine MHL receiver sends control instruction, and the I2C1 interface of MHL receiver is made to be configured to input high-impedance state, and MHL receiver is hung up
I2C1 bus；After the completion of above-mentioned configuration, the first host MCU is by I2C1 bus access slave EEPROM, by USB transmission channel
The debugging and upgrade procedure that transmission comes pass through I2C1 channel transfer to slave EEPROM；When the first host MCU detects program tune
After instruction is completed in examination and upgrading, the I2C1 interface of the first host MCU is configured input high-impedance state by the first host MCU, by the
The I2C2 interface of one host MCU is configured to I2C interface, sends control instruction to the second host MHL receiver by I2C bus,
The I2C1 interface of the second host MHL receiver is set to be also configured as I2C mouthfuls, the second host MHL receiver discharges I2C1 bus, makes
I2C1 bus restores the function of its bus, guarantees that the second host MHL receiver can be communicated with slave EEPROM.Of the invention
In embodiment, I2C interface is a kind of general data transmission interface, it, which can be used as common data transmission interface, to make
For the I2C interface for transmitting I2C bus data, I2C interface is configured by the I2C2 interface of the first host MCU here and is led second
The I2C1 interface of machine MHL receiver is also configured as I2C mouthfuls it is to be understood that by the I2C and the second host of the first host MCU
The I2C1 interface of MHL receiver is arranged for carrying out I2C bus functionality.To realize two hosts, (the first host MCU and second is main
Machine MHL receiver) pass through the I2C1 bus interface function of I2C1 bus time-sharing multiplexing access slave EEPROM.
Corresponding with above-mentioned I2C bus circuit, the present invention also provides a kind of implementation method of I2C bus circuit, Fig. 3
Be one embodiment of the invention a kind of I2C bus circuit implementation method flow chart referring to Fig. 3, this method comprises:
Step S301, in circuit choose as the first host of main equipment and the second host and as from equipment one from
Machine；
I2C bus first interface I2C1 is arranged in step S302 on the first host and the second host and a slave respectively,
It will be connected between the I2C1 of first host, the I2C1 of the second host and the I2C1 of a slave；
I2C bus second interface I2C2 is arranged, by the first host in step S303 on the first host and the second host respectively
It is connected with the I2C2 of the second host；I2C2 using the first host through the first host is sent to the I2C2 of the second host to be controlled
Instruction, to realize the I2C1 of the first host and one slave of the second host time-sharing multiplex.
In the present embodiment, this method further include: be additionally provided with the USB for connecting USB connector on the first host and connect
Mouthful；
Using the first host USB interface receive USB connector transmit come debugging upgrade command and debug upgrade procedure,
And it will be debugged in upgrade procedure write-in slave according to debugging upgrade command；And micro-control unit MCU is chosen as the first master
Machine；
Mobile terminal high-definition audio and video standard interface MHL receiver is chosen as the second host；
Electrically Erasable Programmable Read-Only Memory EEPROM is chosen as a slave.
It should be noted that the implementation method of this I2C bus circuit of the invention is and I2C bus circuit phase above-mentioned
It is corresponding, thus the implementation method of the I2C bus circuit realizes that step may refer to the specific of the part of aforementioned I2C bus circuit
Illustrate, details are not described herein.
In addition, Fig. 4 is a kind of electronic equipment of one embodiment of the invention the present invention also provides a kind of electronic equipment
Block diagram, referring to fig. 4, the electronic equipment 400 include: I2C bus circuit 100.Since this electronic equipment 400 of the invention is integrated
This spi bus circuit 100 of this hair invention, it is thus possible to online burning program and data collision is avoided, stability is strong,
It is at low cost.In one embodiment of the invention, electronic equipment 400 can be head-mounted display apparatus HMD (Head Mount
Display)。
In conclusion I2C bus circuit of the invention and its implementation by will as main equipment the first host with
It second host and is connected, while will set as master by I2C bus first interface I2C1 as the slave from equipment
Standby the first host and the second host is connected by I2C bus second interface I2C2, is sent out from the first host to the second host
The mode of control instruction is sent to realize the I2C1 bus interface of two one slaves of host time-sharing multiplex, solves program online burning
When data collision problem, enhance the stability of system, also omit the recording device of offline burning, save cost.The
One host or the second host can communicate the transimission and storage for realizing data with slave.The present invention also provides one kind comprising upper
The electronic equipment for stating I2C bus circuit, since the I2C bus circuit has the above advantages, it is integrated with the I2C bus electricity
The problem of electronic equipment on road also has stability strong, at low cost, data collision when avoiding online burning program, improves
The competitiveness of electronic equipment.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the scope of the present invention.It is all
Any modification, equivalent replacement, improvement and so within the spirit and principles in the present invention, are all contained in protection scope of the present invention
It is interior.
Claims (9)
1. a kind of I2C bus circuit, which is characterized in that the I2C bus circuit includes: the first host and as main equipment
Two hosts and as the slave from equipment；
It is equipped with I2C bus first interface I2C1 on first host and the second host and a slave, described first
It is directly connected between the I2C1 of host, the I2C1 of second host and the I2C1 of a slave；
I2C bus second interface I2C2, the I2C2 of first host are further respectively had on first host and the second host
It is directly connected between the I2C2 of the second host；
The I2C2 of first host through the first host sends control instruction to the I2C2 of second host, to realize described the
The I2C1 of a slave described in one host and the second host time-sharing multiplex；
First host, the I2C2 interface through the first host is to second host after detecting debugging upgrade command
I2C2 interface sends control instruction, so that second host pause accesses the slave；And detecting debugging upgrading journey
The I2C1 interface of the first host is hung up after the instruction that sequence is completed, I2C mouthfuls is configured by the I2C2 interface of the first host, passes through simultaneously
Described I2C mouthfuls sends control instruction to the I2C2 interface of second host, so that the I2C1 interface of second host configures
It is I2C mouthfuls, restores to access the slave.
2. I2C bus circuit as described in claim 1, which is characterized in that the I2C bus circuit further includes third host；
The third host is equipped with I2C bus first interface I2C1, the I2C1 of first host, the third host
It is connected between I2C1 and the I2C1 of the slave；
It is additionally provided with I2C2 on the third host, is connected between the I2C2 of first host and the I2C2 of third host；
The I2C2 of first host through the first host refers to the I2C2 transmission control of the I2C2, third host of second host
It enables, to realize the I2C1 of first host, second host, a slave described in third host time-sharing multiplex.
3. I2C bus circuit as claimed in claim 1 or 2, which is characterized in that be additionally provided on first host for connecting
The USB interface of USB connector；
First host, for by the USB interface receive USB connector transmission come debugging upgrade command and debugging liter
Grade program, and the debugging upgrade procedure is written in the slave according to the debugging upgrade command.
4. I2C bus circuit as claimed in claim 1 or 2, which is characterized in that first host is micro-control unit MCU；
Second host is mobile terminal high-definition audio and video standard interface MHL receiver；
One slave is Electrically Erasable Programmable Read-Only Memory EEPROM.
5. I2C bus circuit as claimed in claim 4, which is characterized in that the first host MCU is used for the slave
Configuration information is written in EEPROM；
The slave EEPROM is for storing the configuration information；
The second host MHL receiver is for reading the configuration information from the slave EEPROM.
6. I2C bus circuit as claimed in claim 4, which is characterized in that the configuration information stored in the slave EEPROM
It include: audio-video source format information；
The second host MHL receiver, for receiving the audio-video source of external transmission and being read from the slave EEPROM
Take audio-video source format information, using in the slave EEPROM read audio-video source format information to received audio-video source into
Row judgement, and handled accordingly according to judging result.
7. a kind of electronic equipment, which is characterized in that the electronic equipment includes: the I2C as described in any one of claims 1-6
Bus circuit.
8. a kind of implementation method of I2C bus circuit, which is characterized in that this method comprises:
It is chosen in circuit as the first host of main equipment and the second host and as from one slave of equipment；
I2C bus first interface I2C1 is set on first host and second host and a slave respectively,
It will be directly connected between the I2C1 of first host, the I2C1 of second host and the I2C1 of a slave；
I2C bus second interface I2C2 is set on first host and the second host respectively, by first host and the
The I2C2 of two hosts is directly connected to；
Control instruction is sent to the I2C2 of second host using the I2C2 of first host through the first host, to realize
The I2C1 of a slave described in the first host and the second host time-sharing multiplex is stated,
Specifically, enable first host, the I2C2 interface through the first host is to described the after detecting debugging upgrade command
The I2C2 interface of two hosts sends control instruction, so that second host pause accesses the slave；And it is adjusted detecting
The I2C1 interface of the first host is hung up after trying the instruction that upgrade procedure is completed, configures I2C for the I2C2 interface of the first host
Mouthful, while control instruction is sent to the I2C2 interface of second host through described I2C mouthfuls, so that the I2C1 of second host
Interface is configured to I2C mouthfuls, restores to access the slave.
9. method according to claim 8, which is characterized in that this method further include: be additionally provided with use on first host
In the USB interface of connection USB connector；
Using first host the USB interface receive USB connector transmit come debugging upgrade command and debugging upgrade
Program, and the debugging upgrade procedure is written in the slave according to the debugging upgrade command；And
Micro-control unit MCU is chosen as first host；
Mobile terminal high-definition audio and video standard interface MHL receiver is chosen as second host；
Electrically Erasable Programmable Read-Only Memory EEPROM is chosen as a slave.
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| CN108280041B (en) * | 2017-12-29 | 2020-03-10 | 武汉船舶通信研究所（中国船舶重工集团公司第七二二研究所） | Communication method and device for internal integrated circuit host |
| CN108763139A (en) * | 2018-04-20 | 2018-11-06 | 青岛海信电器股份有限公司 | A kind of control method and device of I2C communications |
| CN108920401B (en) * | 2018-06-04 | 2020-07-28 | 深圳柴火创客教育服务有限公司 | Multi-master multi-slave I2C communication method, system and node equipment |
| CN111352638B (en) * | 2020-03-05 | 2023-11-24 | 广州市星翼电子科技有限公司 | Multifunctional cascading offline burning method and system |
| CN113630186B (en) * | 2021-09-15 | 2022-09-16 | 青岛海信宽带多媒体技术有限公司 | Optical module and communication method |
| CN115033444B (en) * | 2022-08-10 | 2022-11-15 | 合肥健天电子有限公司 | 8051 core-based online debugging circuit control device |
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| US7398345B2 (en) * | 2003-06-12 | 2008-07-08 | Hewlett-Packard Development Company, L.P. | Inter-integrated circuit bus router for providing increased security |
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| CN2812115Y (en) * | 2005-07-29 | 2006-08-30 | 杭州华为三康技术有限公司 | On-line upgrading circuit for master equipment |
| CN103218336A (en) * | 2013-02-27 | 2013-07-24 | 珠海市杰理科技有限公司 | SD/MMC (Secure Digital Memory Card/Multimedia Card) and IIC (Inter-Integrated Circuit) slave control equipment, and control method and control system thereof |
| CN104035906A (en) * | 2014-07-03 | 2014-09-10 | 成都智科通信技术有限公司 | Method for achieving time division multiplexing of bus through SPI and application thereof |
| CN204706030U (en) * | 2015-04-29 | 2015-10-14 | 北京小鸟看看科技有限公司 | A kind of I2C bus circuit and electronic equipment |
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