CN204706030U - A kind of I2C bus circuit and electronic equipment - Google Patents
A kind of I2C bus circuit and electronic equipment Download PDFInfo
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- CN204706030U CN204706030U CN201520270410.8U CN201520270410U CN204706030U CN 204706030 U CN204706030 U CN 204706030U CN 201520270410 U CN201520270410 U CN 201520270410U CN 204706030 U CN204706030 U CN 204706030U
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Abstract
The utility model discloses a kind of I2C bus circuit and electronic equipment, this I2C bus circuit comprises: as the first main frame of main equipment and the second main frame and as from one of equipment from machine; First main frame and the second main frame and are equipped with I2C bus first interface I2C1 from machine, and the I2C1 of the first main frame, the I2C1 of the second main frame are connected between machine I2C1 with one; First main frame and the second main frame are also respectively equipped with I2C bus second interface I2C2, and the I2C2 of the first main frame is connected with between the I2C2 of the second main frame; First main frame through the I2C2 of the first main frame to the I2C2 sending controling instruction of the second main frame, to realize the first main frame and the second main frame time-sharing multiplex one I2C1 from machine.Achieve time-sharing multiplex mechanism by this I2C bus circuit of the present utility model, effective management of data flow, realize transmission and the storage of data, facilitate debugging and the upgrading in system later stage simultaneously.
Description
Technical field
The utility model relates to electronic circuit technology field, is specifically related to a kind of I2C bus circuit and electronic equipment.
Background technology
In the circuit of prior art, configuration information and the debugging ROMPaq of system are all off-line burning patterns, this off-line burning pattern needs a large amount of tool equipments to coordinate burning, and needs power-off after information burning completes to be connected with data fetch equipment etc. again, and complicated operation, cost are higher; And online burning pattern to compare off-line burning pattern cost low, power-off is not needed to connect, simple to operate, but there is data collision problem that data store and read and the inconvenient problem of later stage debugging upgrading in online burning pattern, therefore needs a kind of technical scheme that can solve data collision and the inconvenient problem of debugging upgrading in online burning pattern badly.
Utility model content
The utility model provides a kind of I2C bus circuit and electronic equipment conflicts to solve online burning mode data and debugs the inconvenient problem of upgrading.
For achieving the above object, technical solutions of the utility model are achieved in that
According to one side of the present utility model, provide a kind of I2C bus circuit, this I2C bus circuit comprises: as the first main frame of main equipment and the second main frame and as from one of equipment from machine;
First main frame and the second main frame and are equipped with I2C bus first interface I2C1 from machine, and the I2C1 of the first main frame, the I2C1 of the second main frame are connected between the I2C1 of machine with one;
First main frame and the second main frame are also respectively equipped with I2C bus second interface I2C2, and the I2C2 of the first main frame is connected with between the I2C2 of the second main frame;
First main frame through the I2C2 of the first main frame to the I2C2 sending controling instruction of the second main frame, to realize the first main frame and the second main frame time-sharing multiplex one I2C1 from machine.
Alternatively, I2C bus circuit also comprises the 3rd main frame;
3rd main frame is provided with I2C bus first interface I2C1, and the I2C1 of the first main frame, the I2C1 of the 3rd main frame are connected with between the I2C1 from machine;
3rd main frame is also provided with I2C bus second interface I2C2, the I2C2 of the first main frame is connected with between the I2C2 of the 3rd main frame;
First main frame through the I2C2 of I2C2 to the second main frame, the I2C2 sending controling instruction of the 3rd main frame of the first main frame, to realize the first main frame, the second main frame, the 3rd main frame time-sharing multiplex one from the I2C1 of machine.
Alternatively, the first main frame is also provided with the USB interface for connecting USB connector;
First main frame, for being received the next debugging upgrade of USB connector transmission and debugging ROMPaq by USB interface, and will debug ROMPaq write from machine according to debugging upgrade.
Alternatively, the first main frame is micro-control unit MCU;
Second main frame is mobile terminal high-definition audio and video standard interface MHL receiver;
One is EEPROM (Electrically Erasable Programmable Read Only Memo) EEPROM from machine.
Alternatively, the first main frame MCU, through the I2C2 interface sending controling instruction of the I2C2 interface of the first main frame to the second main frame MHL receiver after debugging upgrade being detected, makes the second main frame MHL receiver suspend access from machine EEPROM; And,
After the instruction that debugging ROMPaq completes being detected, the I2C1 interface of the first main frame MCU is hung up, be I2C mouth by the I2C2 interface configuration of the first main frame MCU, simultaneously through the I2C2 interface sending controling instruction of I2C2 interface to the second main frame MHL receiver, the I2C1 interface configuration making the second main frame MHL receiver is I2C mouth, recovers access from machine EEPROM.
Alternatively, the first main frame MCU is used for writing configuration information to from machine EEPROM;
Store configuration information is used for from machine EEPROM;
Second main frame MHL receiver is used for reading configuration information from from machine EEPROM.
Alternatively, the configuration information stored from machine EEPROM comprises: audio-video source format information;
Second main frame MHL receiver, for receiving the audio-video source of external transmission and reading audio-video source format information from from machine EEPROM, utilization is read audio-video source format information and is judged the audio-video source received from machine EEPROM, and handles accordingly according to judged result.
According to another aspect of the present utility model, additionally provide a kind of electronic equipment, this electronic equipment comprises: as the I2C bus circuit of the utility model aspect.
The beneficial effects of the utility model are: the technical solution of the utility model by using as main equipment the first main frame and the second main frame and coupled together by I2C bus first interface I2C1 as from one of equipment from machine, coupled together as the first main frame of main equipment and the second main frame by I2C bus second interface I2C2 simultaneously, the I2C1 bus interface of two main frame time-sharing multiplexs one from machine is realized to the mode of the second main frame sending controling instruction by the first main frame, solve data collision problem during program online burning, first main frame or the second main frame all can communicate with from machine the transmission and storage that realize data, in addition, online burning also omit the recording device of off-line burning, provide cost savings, enhance the stability of system.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of I2C bus circuit of the utility model embodiment;
Fig. 2 is the structural representation of a kind of I2C bus circuit of another embodiment of the utility model;
Fig. 3 is a kind of I2C bus circuit implementation method process flow diagram of the utility model embodiment;
Fig. 4 is the block diagram of a kind of electronic equipment of the utility model embodiment.
Embodiment
Core concept of the present utility model is: for problems of the prior art, utilize the feature of I2C (Inter-Integrated Circuit) bus, propose a kind of time-sharing multiplex based on I2C bus mechanism, solve the collision problem of two main one digital independent existed from system and storage, data flow is effectively managed, facilitates the system later stage to upgrade and debugging simultaneously.I2C bus is a kind of universal serial bus of twin wire, for connecting microcontroller and peripherals thereof.It is a kind of special shape of synchronous communication, has interface line few, and control mode is simple, and device package form is little, and traffic rate is advantages of higher comparatively.I2C bus is being connected to transmission of information between the device of bus by serial data (SDA) line and serial clock (SCL) line.Time-sharing multiplex in the utility model embodiment refers to that the first moment was carried out the write work of data from machine by the first host access one, second moment was carried out the read work of data from machine by the second host access one, two main frame time-sharing multiplexs are same as machine, thus avoid data collision problem.Control realization can be carried out by the first main frame during concrete enforcement and access switching.
Fig. 1 is the structural representation of a kind of I2C bus circuit of the utility model embodiment, and see Fig. 1, this I2C bus circuit of the present utility model comprises:
As the first main frame 101 of main equipment and the second main frame 102 and as from one of equipment from machine 103;
First main frame 101 and the second main frame 102 and are equipped with I2C bus first interface I2C1 from machine 103, and the I2C1 of the first main frame 101, the I2C1 of the second main frame 102 are connected between the I2C1 of machine 103 with one;
First main frame 101 and the second main frame 102 are also respectively equipped with I2C bus second interface I2C2, and the I2C2 of the first main frame 101 is connected with between the I2C2 of the second main frame 102;
First main frame 101 through the I2C2 of the first main frame 101 to the I2C2 sending controling instruction of the second main frame 102, to realize the first main frame 101 and the second main frame 102 time-sharing multiplex one I2C1 from machine 103.
In the present embodiment, the first main frame 101 is micro-control unit MCU, and the second main frame 102 is mobile terminal high-definition audio and video standard interface MHL receiver, and one is EEPROM (Electrically Erasable Programmable Read Only Memo) EEPROM from machine 103.Wherein, MHL is a kind of audio-visual standard interface connecting portable consumer electronic device, the audio, video data of outside audio-video source transmission can be received by this interface, second main frame MHL receiver has the few and advantage of good stability of required transmission line, but the chip of the second main frame MHL receiver does not have fixed storage function, meeting obliterated data during power-off, the second main frame MHL receiver obtains configuration information by access one from machine EEPROM.In the present embodiment be a kind of power down from machine EEPROM after the storage medium do not lost of data, EEPROM can the existing information of erasing on computers or on specialized equipment, reprogramming.It should be noted that, the size of data considering main frame and configuration information upgrading ascending order is needed from the selection of machine, the data such as configuration information and MCU system debug ROMPaq needed due to MHL receiver in the present embodiment are not too large, so select EEPROM as from machine, in other embodiments of the present utility model from machine can be erasable programmable EPROM or other ROM storeies.
In addition, in an embodiment of the present utility model, I2C bus circuit comprises the first main frame and the second main frame as from equipment, and the second main frame is MHL receiver, for receiving audio/video information.But in other embodiments of the present utility model, I2C bus circuit can also comprise the 3rd main frame, the 3rd main frame is provided with I2C bus first interface I2C1, and the I2C1 of the first main frame, the I2C1 of the 3rd main frame are connected with between the I2C1 from machine;
3rd main frame is also provided with I2C bus second interface I2C2, the I2C2 of the first main frame is connected with between the I2C2 of the 3rd main frame;
First main frame through the I2C2 of I2C2 to the second main frame, the I2C2 sending controling instruction of the 3rd main frame of the first main frame, to realize the first main frame, described second main frame, the 3rd main frame time-sharing multiplex one from the I2C1 of machine.
3rd main frame is for receiving the information of other types data, and under the control of the first main frame, time-sharing multiplex one is from the I2C1 bus interface of machine, now, first main frame, the second main frame and the 3rd main frame time-sharing multiplex one are from the I2C1 interface of machine, first main frame is responsible for writing data to from machine, and when data write by the first main frame, other two main frames (the second main frame and the 3rd main frame) all suspend access from machine.After the write operation is completed, one of them main frame of the first host computer control (the second main frame or the 3rd main frame) access is fetched data from machine-readable, and another main frame (the second main frame or the 3rd main frame) suspends access from machine.Concrete second or the 3rd the host access application that can be realized by the second main frame or the 3rd main frame from machine determine, when the second main frame or the 3rd main frame need to carry out read data operation, specifically control the second main frame or the 3rd host access from machine by the first main frame.
In the circuit shown in Fig. 1, first main frame MCU by I2C1 bus by system configuration information programming to from machine EEPROM, second main frame MHL receiver to read the system configuration information storer from machine EEPROM by I2C1 bus access, the I2C2 that first main frame MCU controls the second main frame MHL receiver by I2C2 realizes two main frames by the function of the multiplexing access of I2C1 bus time-sharing from the I2C1 bus interface of machine EEPROM, solve the first main frame and the second main frame and access data collision problem from machine simultaneously, also save hardware cost and improve the stability of system.
Fig. 2 is the structural representation of a kind of I2C bus circuit of another embodiment of the utility model; First main frame 101 is also provided with the USB interface for connecting USB connector;
First main frame 101 for being received the next debugging upgrade of USB connector transmission and debugging ROMPaq by USB interface, and will debug ROMPaq write from machine 103 according to debugging upgrade.
First main frame MCU101, through the I2C2 interface sending controling instruction of the I2C2 interface of the first main frame MCU101 to the second main frame MHL receiver 102 after receiving debugging upgrade, makes the second main frame MHL receiver 102 suspend access EEPROM103; And, after the instruction that debugging ROMPaq completes being detected, the I2C1 interface of MCU101 is hung up, be I2C mouth by the I2C2 interface configuration of the first main frame MCU101, simultaneously through the I2C2 interface sending controling instruction of I2C2 interface to the second main frame MHL receiver 102, the I2C1 interface configuration making the second main frame MHL receiver is I2C mouth, recovers access EEPROM103.
In the present embodiment, the first main frame MCU101 is used for writing configuration information in EEPROM103; Store configuration information is used for from machine EEPROM103; Second main frame MHL receiver 102 is for reading configuration information from from machine EEPROM103.The configuration information stored from machine EEPROM103 comprises: audio-video source format information; Second main frame MHL receiver 102 is also for receiving the audio-video source of external transmission and reading audio-video source format information from from machine EEPROM103, utilization is read audio-video source format information and is judged the audio-video source received from machine EEPROM103, and handles accordingly according to judged result.The concrete course of work is, when I2C circuit normally works, second main frame MHL receiver is by after detecting the input of outside audio-video source and input format, by I2C1 bus access from machine EEPROM, whether the form of the video source of matching judgment outside input is consistent with the configuration information stored from machine EEPROM.If consistent, audio-video source continues to transmit to the back-end to do to process further by the second main frame MHL receiver; If inconsistent, video source is cut off and is not transmitted to the back-end by the second main frame MHL receiver.Here just in the utility model embodiment, judgement processing procedure is carried out as during a main frame by reading the configuration information stored from machine when have chosen MHL receiver, when choosing the main frame of other devices as the utility model I2C bus circuit, it may not be the judgement to audio-video source form, the function that can should realize according to other devices and the configuration information stored from machine do concrete process, do not limit this.
Work as the later stage, when system needs DFU (Device Firmware Upgrade) to debug and upgrades, after first main frame MCU detects the DFU debugging that USB connector transmission comes and upgrade by USB interface, by I2C2 bus interface to the second main frame MHL receiver sending controling instruction, make the I2C1 interface configuration of MHL receiver for input high-impedance state, I2C1 bus hung up by MHL receiver; After above-mentioned configuration completes, the first main frame MCU is by I2C1 bus access from machine EEPROM, and the debugging come the transmission of USB transmission channel and ROMPaq pass through I2C1 channel transfer extremely from machine EEPROM; After the first main frame MCU detects that program debug and upgrading complete instruction, the I2C1 interface configuration of the first main frame MCU is input high-impedance state by the first main frame MCU, be I2C interface by the I2C2 interface configuration of the first main frame MCU, by I2C bus to the second main frame MHL receiver sending controling instruction, the I2C1 interface of the second main frame MHL receiver is made also to be configured to I2C mouth, second main frame MHL receiver release I2C1 bus, make the function of its bus of I2C1 bus recovery, ensure that the second main frame MHL receiver can communicate with from machine EEPROM.In an embodiment of the present invention, I2C interface is a kind of general data transmission interface, it can also can as the I2C interface of transmission I2C bus data as common data transmission interface, here be I2C interface by the I2C2 interface configuration of the first main frame MCU and the I2C1 interface of the second main frame MHL receiver is also configured to I2C mouth can be understood as, by the I2C1 interface configuration of the I2C of the first main frame MCU and the second main frame MHL receiver for realizing I2C bus functionality.Thus achieve two main frames (the first main frame MCU and the second main frame MHL receiver) by the I2C1 bus interface function of the multiplexing access of I2C1 bus time-sharing from machine EEPROM.Corresponding with above-mentioned I2C bus circuit, the utility model additionally provides a kind of implementation method of I2C bus circuit, Fig. 3 be a kind of I2C bus circuit implementation method process flow diagram of the utility model embodiment see Fig. 3, the method comprises:
Step S301, chooses as the first main frame of main equipment and the second main frame and as from equipment one from machine in circuit;
Step S302, arranges I2C bus first interface I2C1 at the first main frame and the second main frame and from machine respectively, is coupled together by the I2C1 and of the I2C1 of the first main frame, the second main frame between the I2C1 of machine;
Step S303, arranges I2C bus second interface I2C2 respectively, is coupled together by the I2C2 of the first main frame and the second main frame on the first main frame and the second main frame; Utilize the first main frame through the I2C2 of the first main frame to the I2C2 sending controling instruction of the second main frame, to realize the first main frame and the second main frame time-sharing multiplex one I2C1 from machine.
In the present embodiment, the method also comprises: on the first main frame, be also provided with the USB interface for connecting USB connector;
Utilize the USB interface of the first main frame to receive the next debugging upgrade of USB connector transmission and debugging ROMPaq, and ROMPaq write will be debugged from machine according to debugging upgrade; And, choose micro-control unit MCU as the first main frame;
Choose mobile terminal high-definition audio and video standard interface MHL receiver as the second main frame;
Choose EEPROM (Electrically Erasable Programmable Read Only Memo) EEPROM as one from machine.
It should be noted that, the implementation method of this I2C bus circuit of the present utility model is corresponding with aforesaid I2C bus circuit, thus the implementation method performing step of this I2C bus circuit can illustrating see the part of aforementioned I2C bus circuit, do not repeat them here.
In addition, the utility model additionally provides a kind of electronic equipment, and Fig. 4 is the block diagram of a kind of electronic equipment of the utility model embodiment, and see Fig. 4, this electronic equipment 400 comprises: I2C bus circuit 100.Because this electronic equipment 400 of the present utility model is integrated with this spi bus circuit 100 of this utility model, thus can online burning program and avoid data collision, stability is strong, and cost is low.In an embodiment of the present utility model, electronic equipment 400 can be head-mounted display apparatus HMD (Head Mount Display).
In sum, I2C bus circuit of the present utility model and its implementation by using as main equipment the first main frame and the second main frame and coupled together by I2C bus first interface I2C1 as from one of equipment from machine, coupled together as the first main frame of main equipment and the second main frame by I2C bus second interface I2C2 simultaneously, the I2C1 bus interface of two main frame time-sharing multiplexs one from machine is realized to the mode of the second main frame sending controling instruction by the first main frame, solve data collision problem during program online burning, enhance the stability of system, also omit the recording device of off-line burning, provide cost savings.First main frame or the second main frame all can communicate with from machine the transmission and storage that realize data.The utility model additionally provides a kind of electronic equipment comprising above-mentioned I2C bus circuit, because this I2C bus circuit has above-mentioned advantage, therefore, the electronic equipment being integrated with this I2C bus circuit also has that stability is strong, cost is low, the problem of data collision when avoiding online burning program, improves the competitive power of electronic equipment.
The foregoing is only preferred embodiment of the present utility model, be not intended to limit protection domain of the present utility model.All do within spirit of the present utility model and principle any amendment, equivalent replacement, improvement etc., be all included in protection domain of the present utility model.
Claims (8)
1. an I2C bus circuit, is characterized in that, described I2C bus circuit comprises: as the first main frame of main equipment and the second main frame and as from one of equipment from machine;
Described first main frame and the second main frame and described are equipped with I2C bus first interface I2C1 from machine, and the I2C1 of described first main frame, the I2C1 of described second main frame are connected between the I2C1 of machine with described one;
Described first main frame and the second main frame are also respectively equipped with I2C bus second interface I2C2, and the I2C2 of described first main frame is connected with between the I2C2 of the second main frame;
Described first main frame through the I2C2 of the first main frame to the I2C2 sending controling instruction of described second main frame, to realize described in described first main frame and described second main frame time-sharing multiplex one from the I2C1 of machine.
2. I2C bus circuit as claimed in claim 1, it is characterized in that, described I2C bus circuit also comprises the 3rd main frame;
Described 3rd main frame is provided with I2C bus first interface I2C1, and the I2C1 of described first main frame, the I2C1 of described 3rd main frame are connected between the I2C1 of machine with described;
Described 3rd main frame is also provided with I2C2, and the I2C2 of described first main frame is connected with between the I2C2 of the 3rd main frame;
Described first main frame through the I2C2 of I2C2 to described second main frame, the I2C2 sending controling instruction of the 3rd main frame of the first main frame, to realize described in described first main frame, described second main frame, the 3rd main frame time-sharing multiplex one from the I2C1 of machine.
3. I2C bus circuit as claimed in claim 1 or 2, is characterized in that, described first main frame being also provided with the USB interface for connecting USB connector;
Described first main frame, for receiving the next debugging upgrade of USB connector transmission and debugging ROMPaq, and according to described debugging upgrade by described from machine for described debugging ROMPaq write by described USB interface.
4. I2C bus circuit as claimed in claim 1 or 2, it is characterized in that, described first main frame is micro-control unit MCU;
Described second main frame is mobile terminal high-definition audio and video standard interface MHL receiver;
Described one is EEPROM (Electrically Erasable Programmable Read Only Memo) EEPROM from machine.
5. I2C bus circuit as claimed in claim 3, is characterized in that,
Described first main frame MCU, through the I2C2 interface sending controling instruction of the I2C2 interface of the first main frame to described second main frame MHL receiver after described debugging upgrade being detected, makes described second main frame MHL receiver suspend access described from machine EEPROM; And,
After the instruction that described debugging ROMPaq completes being detected, the I2C1 interface of the first main frame MCU is hung up, be I2C mouth by the I2C2 interface configuration of the first main frame MCU, simultaneously through the I2C2 interface sending controling instruction of described I2C mouth to described second main frame MHL receiver, the I2C1 interface configuration making described second main frame MHL receiver is I2C mouth, recovers described in access from machine EEPROM.
6. I2C bus circuit as claimed in claim 4, is characterized in that, described first main frame MCU is used for from machine EEPROM, writing configuration information to described;
Described from machine EEPROM for storing described configuration information;
Described second main frame MHL receiver is used for from machine EEPROM, reading described configuration information from described.
7. I2C bus circuit as claimed in claim 5, it is characterized in that, the described configuration information stored from machine EEPROM comprises: audio-video source format information;
Described second main frame MHL receiver, for receiving the audio-video source of external transmission and reading audio-video source format information from described from machine EEPROM, from machine EEPROM, read audio-video source format information described in utilizing judge the audio-video source received, and handle accordingly according to judged result.
8. an electronic equipment, is characterized in that, this electronic equipment comprises: the I2C bus circuit according to any one of claims 1-7.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104834619A (en) * | 2015-04-29 | 2015-08-12 | 小鸟科技有限公司 | I2C (Inter-Integrated Circuit) bus circuit, implementation method and electronic equipment |
| CN105740015A (en) * | 2016-01-27 | 2016-07-06 | 北京小鸟看看科技有限公司 | Upgrade method for firmware of HMD device |
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2015
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104834619A (en) * | 2015-04-29 | 2015-08-12 | 小鸟科技有限公司 | I2C (Inter-Integrated Circuit) bus circuit, implementation method and electronic equipment |
| CN104834619B (en) * | 2015-04-29 | 2018-12-18 | 北京小鸟看看科技有限公司 | A kind of I2C bus circuit, implementation method and electronic equipment |
| CN105740015A (en) * | 2016-01-27 | 2016-07-06 | 北京小鸟看看科技有限公司 | Upgrade method for firmware of HMD device |
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