CN112993756A - Preparation method of semiconductor laser chip - Google Patents
Preparation method of semiconductor laser chip Download PDFInfo
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- CN112993756A CN112993756A CN201911205144.XA CN201911205144A CN112993756A CN 112993756 A CN112993756 A CN 112993756A CN 201911205144 A CN201911205144 A CN 201911205144A CN 112993756 A CN112993756 A CN 112993756A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S2304/00—Special growth methods for semiconductor lasers
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Abstract
The invention discloses a preparation method of a semiconductor laser chip, wherein a P surface of the prepared chip is provided with a P-type depressed area and a P-type non-depressed area, the P-type depressed area and the P-type non-depressed area are sequentially arranged at intervals, an N surface of the chip is provided with an N-type non-depressed area and an N-type depressed area, and the N-type non-depressed area and the N-type depressed area are sequentially arranged at intervals; this chip structure can be with the chip cleavage one-tenth barre when follow-up cleavage coating film to piling up the barre each other, can mutually support through P type depressed area, N type non-depressed area between the adjacent barre and place, put the filler strip at both ends again, the pendulum strip degree of contact is higher during the coating film, can effectively improve the coating film homogeneity, improves the rete quality. The invention has reasonable process design, simple operation and reasonable chip structure design, not only reduces the production cost, but also improves the film coating efficiency, ensures the film coating quality, solves the technical problems of electrode pollution, scratch and the like in the film coating process, and improves the product yield.
Description
Technical Field
The invention relates to the field of semiconductor lasers, in particular to a preparation method of a semiconductor laser chip.
Background
The semiconductor laser works in excitation mode, and utilizes the transition luminescence of semiconductor material between energy bands, and uses the cleavage plane of semiconductor crystal to form two parallel reflecting mirror surfaces as reflecting mirrors to form resonant cavity, so as to make light oscillate, feed back and produce light radiation amplification and output laser. In the preparation process, the chip is firstly cleaved into bars to form the resonant cavity, but the light-emitting efficiency is low, and a reflecting film and an antireflection film need to be respectively evaporated on two sides of the cavity surface to improve the light-emitting efficiency.
In a conventional preparation process, in order to ensure the yield of the bars, when film layers of bar cavity surfaces are evaporated, a plurality of P/N surfaces of the bars need to be oppositely stacked, and two side cavity surfaces are exposed to facilitate film coating, and the process is generally called as bar swinging. When the swing strip is carried out, because the P/N surface metal electrodes of the adjacent bars are connected, the P/N surface electrodes of the bars are easy to generate abnormal friction scratch, and abnormal conditions such as uneven welding and the like are introduced to later-stage packaging, so that the reliability of a packaging device is influenced. And adjacent bar P/N metal electrodes are contacted, and are tightly contacted at high temperature for a long time, so that diffusion adhesion among metals is easily caused, and the bars cannot be detached after film coating.
In order to improve the defects of the process, a plurality of semiconductor laser manufacturers adopt a strip swinging process for separating the strips from each other by the non-metal high-flatness packing strips to carry out cavity surface coating, the method introduces the cost of 50% of the packing strips, and due to the addition of the packing strips, the number of the strip swinging strips is reduced by about 50%, and the productivity is reduced by about 50%.
In view of the above problems, a method for manufacturing a semiconductor laser chip is provided, which is one of the problems to be solved urgently.
Disclosure of Invention
The invention aims to provide a preparation method of a semiconductor laser chip, which aims to solve the problems in the prior art.
In order to achieve the purpose, the invention provides the following technical scheme:
a preparation method of a semiconductor laser chip comprises the following steps:
1) growing an epitaxial wafer;
2) preparing a P-type depressed area and a P-type non-depressed area on the P surface of the epitaxial wafer;
3) preparing a P electrode;
4) preparing an N-type depressed region and an N-type non-depressed region on the N surface of the epitaxial wafer;
5) preparing an N electrode;
6) and (4) alloying, and cleaving the plated film to obtain a finished product.
The invention discloses a preparation method of a semiconductor laser chip, wherein a P surface of the prepared chip is provided with a P-type depressed area and a P-type non-depressed area, the P-type depressed area and the P-type non-depressed area are sequentially arranged at intervals, an N surface of the chip is provided with an N-type non-depressed area and an N-type depressed area, and the N-type non-depressed area and the N-type depressed area are sequentially arranged at intervals; this chip structure can be with the chip cleavage one-tenth barre when follow-up cleavage coating film to piling up the barre each other, can mutually support through P type depressed area, N type non-depressed area between the adjacent barre and place, put the filler strip at both ends again, the pendulum strip degree of contact is higher during the coating film, can effectively improve the coating film homogeneity, improves the rete quality.
Preferably, the method comprises the following steps:
1) and (3) epitaxial wafer growth: taking a substrate, and growing an N-type lower cladding layer, an active region and a P-type upper cladding layer on the substrate in sequence to obtain an epitaxial wafer; preparing an epitaxial wafer in the step 1), wherein the substrate can be a GaAs substrate, and an N-type lower cladding layer, an active region and a P-type upper cladding layer are sequentially grown on the substrate to obtain the epitaxial wafer;
2) preparing a P-type depressed area and a P-type non-depressed area on the P surface of the epitaxial wafer;
a) taking the epitaxial wafer prepared in the step 1), placing the epitaxial wafer on a spin coater with the P surface upward, coating photoresist on the P-type upper cladding, and baking and curing;
b) exposing and developing, photoetching a target pattern on the mask layer, etching to form a plurality of P-type depressed areas, wherein the areas which are not etched are P-type non-depressed areas, and removing the photoresist on the surfaces of the P-type non-depressed areas; in the step 2), photoetching is carried out through photoresist to expose a target pattern, and etching is carried out to form a P-type depressed area, wherein the area outside the P-type depressed area is a P-type non-depressed area; wherein the number of the P-type depressed regions is not less than 1; when etching the P-type depressed area, dry etching or wet etching can be selected for operation; the photoresist can be removed by acetone and ethanol organic reagent by ultrasonic or rinsing;
c) etching a ridge structure on the P-type non-depressed area, wherein the ridge structure is deep into the upper cladding layer; then, etching a ridge structure on the P-type non-depressed area in the step 2), exposing a ridge groove area through a photoetching mask during etching, and then etching the ridge structure, wherein the etching method can be dry etching or wet etching;
d) preparing an insulating layer on the P surface of the epitaxial wafer, wherein the insulating layer covers the upper surface of the epitaxial layer and the side surface of the ridge-type structure; preparing an insulating layer on the epitaxial wafer in the step d), wherein the upper surface of the ridge structure on the P-type non-recessed area is not covered by the insulating layer (the surface of the ridge structure can be completely uncovered by the insulating layer in actual operation), so as to form a current injection area, and the rest areas are completely covered by the insulating layer; the surface of the P-type sunken area is also covered with an insulating layer completely;
3) taking the epitaxial wafer processed in the step 2), and preparing a P electrode on a P-type non-depressed area, wherein the P electrode covers the ridge-type structure to form a tube core structure, and N is more than or equal to 1 if the number of the tube core structures is N; preparing a P electrode in the step 3) to form a tube core structure, wherein N tube core structures can be designed in each P-type non-recessed area in actual operation, the N tube core structures are arranged periodically, and N is more than or equal to 1; in actual operation, the P electrode can be prepared by any one of evaporation, sputtering, stripping and corrosion processes;
4) preparing an N-type depressed region and an N-type non-depressed region on the N surface of the epitaxial wafer;
a) taking the epitaxial wafer treated in the step 3), grinding and polishing the substrate, placing the epitaxial wafer on a spin coater with the N surface upward, coating photoresist, and baking and curing;
b) exposing and developing, photoetching a target pattern, etching to form an N-type depressed area, wherein the area which is not etched is an N-type non-depressed area, and removing the photoresist on the surface of the N-type non-depressed area; thinning and polishing the substrate in the step 4), and removing a certain thickness to reduce the body resistance of the tube core and improve the photoelectric performance; then, exposing and developing through photoresist, and etching to form an N-type depressed area, wherein the part which is not etched is an N-type non-depressed area;
5) taking the epitaxial wafer processed in the step 4), and preparing an N electrode on the N surface of the epitaxial wafer, wherein the N electrode covers the N surface of the whole epitaxial wafer; preparing an N electrode in the step 5);
6) and (4) cleaving the plated film by adopting a rapid annealing furnace alloy to obtain a finished product. In the step 6), furnace tube alloy or a rapid annealing furnace can be adopted for alloying, and the cavity surface of the cleavage is coated with film to obtain a finished product.
In practical operation of the invention, when the P-side preparation of the epitaxial wafer is carried out in the step 2), the method can also be carried out according to the following steps:
a) etching a ridge structure on the P surface of the epitaxial wafer, wherein the ridge structure is deep into the upper cladding layer;
b) taking an epitaxial wafer with a ridge structure, placing the epitaxial wafer on a spin coater with the P surface upward, coating photoresist on a P-type upper cladding, and baking and curing;
c) exposing and developing, photoetching a target pattern on the mask layer, etching to form a plurality of P-type depressed areas, wherein the areas which are not etched are P-type non-depressed areas, and removing the photoresist on the surfaces of the P-type non-depressed areas; at the moment, the ridge structure is positioned on the surface of the P-type non-depressed area; preparing an insulating layer on the P surface of the epitaxial wafer, wherein the insulating layer covers the upper surface of the epitaxial layer and the side surface of the ridge structure;
preferably, the width of the P-type recessed region is dP1The width of the P-type non-recessed region is dP2The width of the N-type recessed region is dN1Then MdP2+(M-1)dP1＜dN1＜MdP2+MdP1，M≥1。
The width of the N-type concave region is limited in the invention, namely MdP is satisfied2+(M-1)dP1＜dN1＜MdP2+MdP1And M is more than or equal to 1, and in the actual processing process, the N-type concave regions can be in a periodic arrangement or a non-periodic arrangement.
Preferably, the depth of the N-type recessed region is hNThe depth of the P-shaped depressed region is hPThen h isN＞hP。
The invention is definedThe depth of the N-type depressed region and the P-type depressed region, i.e. hN＞hPWhen the design can guarantee that when the batten is stacked, when the N-type non-depressed area is embedded into the P-type depressed area, the P electrode on the P-type non-depressed area can not be in contact with the bottom surface of the N-type depressed area, scratch, damage and pollution caused by contact friction of the P electrode and the N electrode are effectively avoided, and the yield of chips is improved.
Preferably, in the step 2), the insulating layer is any one of SiO2, SiNx, and SiNO.
Preferably, the step 2) of preparing the insulating layer comprises the following specific steps:
A. taking an epitaxial wafer with a ridge structure, and growing an insulating layer on the surface of the epitaxial wafer by adopting a vapor deposition method;
B. placing the epitaxial wafer on a photoresist spinner, coating a layer of photoresist on the surface of the insulating layer, exposing and developing to expose a ridge structure region, and then corroding the insulating layer;
C. and removing the photoresist on the surface of the epitaxial wafer to finish the operation.
Preferably, the step 2) of preparing the insulating layer comprises the following specific steps:
a) taking an epitaxial wafer with a ridge structure, placing the epitaxial wafer on a spin coater, coating a layer of photoresist on the surface of the epitaxial wafer, exposing, developing and corroding, wherein the photoresist covers the surface of the ridge structure;
b) growing an insulating layer on the surface of the epitaxial wafer by adopting a vapor deposition method;
c) and removing the photoresist on the surface of the epitaxial wafer to finish the operation.
Preferably, the P-type recessed regions correspond to the N-type non-recessed regions.
Preferably, in step 3), the die structures are arranged periodically.
In actual operation, the P-type depressed area is not covered by the P electrode, so that the design can avoid the abnormal leakage current caused by step coverage difference and the abnormal diffusion adhesion caused by P/N electrode interface contact in the later-stage swinging strip coating process.
Compared with the prior art, the invention has the beneficial effects that:
the chip prepared by the invention can reduce the bending degree of the bars by adopting the P/N surface corresponding concave-convex structure, and when the bars are swung, the P surface pipe core of the bars is embedded into the N type concave area of the adjacent bars, and the P/N electrodes are not contacted, so that the scratch pollution, the damage and the inter-metal diffusion of the electrodes in the coating process are avoided, and the product performance is improved; meanwhile, the cushion strips are saved, the cost is reduced, and the productivity is improved.
After the chip is prepared and coated, the chip is cleaved into bars during coating, the bars are stacked mutually, adjacent bars can be placed in a mutually matched mode through a P-type depressed area and an N-type non-depressed area, and the two ends of the chip are provided with cushion strips for coating.
The invention discloses a preparation method of a semiconductor laser chip, which has the advantages of reasonable process design, simple operation and reasonable chip structure design, not only reduces the production cost, but also improves the film coating efficiency and ensures the film coating quality, and simultaneously solves the technical problems of electrode pollution, scratching and the like in the film coating process, improves the product yield and has higher practicability.
Drawings
In order that the present invention may be more readily and clearly understood, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments that are illustrated in the appended drawings.
FIG. 1 is a process flow diagram of a method for fabricating a semiconductor laser chip according to the present invention;
FIG. 2 is a schematic sectional view of a finished chip region of a method for fabricating a semiconductor laser chip according to the present invention;
fig. 3 is a schematic sectional view of a chip region after a ridge structure is fabricated according to a method for fabricating a semiconductor laser chip of the present invention;
FIG. 4 is a schematic cross-sectional view of a chip region after an insulating layer is formed according to a method for forming a semiconductor laser chip of the present invention;
FIG. 5 is a schematic cross-sectional view of a P-electrode fabricated chip region of a method for fabricating a semiconductor laser chip according to the present invention;
fig. 6 is a schematic sectional view of a chip region after N-side preparation of an epitaxial wafer according to a method for manufacturing a semiconductor laser chip of the present invention;
fig. 7 is a schematic sectional view of a chip region after an N electrode is fabricated according to a method for fabricating a semiconductor laser chip of the present invention;
fig. 8 is a schematic diagram of a bar stacking structure during chip coating according to a method for manufacturing a semiconductor laser chip of the present invention.
In the figure: the structure comprises a 1-P type non-depressed area, a 2-P type depressed area, a 3-N type depressed area, a 4-N type non-depressed area, a 5-ridge structure, a 6-insulating layer, a 7-P electrode, an 8-N electrode, a 9-P type upper cladding layer, a 10-active area, an 11-N type lower cladding layer, a 12-substrate, a 13-busbar and a 14-pad strip.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1:
s1: taking a substrate 12, and growing an N-type lower cladding layer 11, an active region 10 and a P-type upper cladding layer 9 on the substrate 12 in sequence to obtain an epitaxial wafer;
s2: taking the prepared epitaxial wafer, putting the P surface of the epitaxial wafer on a spin coater with the P surface upward, coating photoresist on the P-type upper cladding 9, and baking and curing; exposing and developing, photoetching a target pattern on the mask layer, etching to form a plurality of P-type depressed regions 2, wherein the regions which are not etched are P-type non-depressed regions 1, and removing the photoresist on the surface of the P-type non-depressed regions 1;
s3: etching a ridge structure 5 on the P-type non-depressed area 1, wherein the ridge structure 5 is deep into the upper cladding layer;
s4: taking an epitaxial wafer with a ridge structure 5, and growing an insulating layer 6 on the surface of the epitaxial wafer by adopting a vapor deposition method; placing the epitaxial wafer on a spin coater, coating a layer of photoresist on the surface of the insulating layer 6, exposing and developing to expose the ridge structure 5 region, etching off the insulating layer 6, and removing the photoresist on the surface of the epitaxial wafer; the insulating layer 6 covers the upper surface of the epitaxial layer and the side surface of the ridge-type structure 5;
s5: taking the epitaxial wafer processed in the step S4, preparing a P electrode 7 on the P-type non-recessed area 1, covering the P electrode 7 on the ridge-type structure 5 to form tube core structures, wherein N is more than or equal to 1 when the number of the tube core structures is N, and the tube core structures are arranged periodically;
s6: taking the epitaxial wafer processed in the step S5, grinding and polishing the substrate 12, placing the epitaxial wafer on a photoresist spinner with the N surface upward, coating photoresist, baking and curing; exposing and developing, photoetching a target pattern, etching to form an N-type depressed area 3, wherein the area which is not etched is an N-type non-depressed area 4, and removing the photoresist on the surface of the N-type non-depressed area 4;
s7: preparing an N electrode 8 on the N surface of the epitaxial wafer from the epitaxial wafer processed in the step S6, wherein the N electrode 8 covers the whole N surface of the epitaxial wafer; and (4) cleaving the plated film by adopting a rapid annealing furnace alloy to obtain a finished product.
In this embodiment, the positions of the P-type recessed region 2 and the N-type non-recessed region 4 correspond to each other; the insulating layer 6 is SiO2。
Example 2:
s1: taking a substrate 12, and growing an N-type lower cladding layer 11, an active region 10 and a P-type upper cladding layer 9 on the substrate 12 in sequence to obtain an epitaxial wafer;
s2: taking the prepared epitaxial wafer, putting the P surface of the epitaxial wafer on a spin coater with the P surface upward, coating photoresist on the P-type upper cladding 9, and baking and curing; exposing and developing, photoetching a target pattern on the mask layer, etching to form a plurality of P-type depressed regions 2, wherein the regions which are not etched are P-type non-depressed regions 1, and removing the photoresist on the surface of the P-type non-depressed regions 1;
s3: etching a ridge structure 5 on the P-type non-depressed area 1, wherein the ridge structure 5 is deep into the upper cladding layer;
s4: taking an epitaxial wafer with a ridge structure 5, and growing an insulating layer 6 on the surface of the epitaxial wafer by adopting a vapor deposition method; placing the epitaxial wafer on a spin coater, coating a layer of photoresist on the surface of the insulating layer 6, exposing and developing to expose the ridge structure 5 region, etching off the insulating layer 6, and removing the photoresist on the surface of the epitaxial wafer; the insulating layer 6 covers the upper surface of the epitaxial layer and the side surface of the ridge-type structure 5;
s5: taking the epitaxial wafer processed in the step S4, preparing a P electrode 7 on the P-type non-recessed area 1, covering the P electrode 7 on the ridge-type structure 5 to form tube core structures, wherein N is more than or equal to 1 when the number of the tube core structures is N, and the tube core structures are arranged periodically;
s6: taking the epitaxial wafer processed in the step S5, grinding and polishing the substrate 12, placing the epitaxial wafer on a photoresist spinner with the N surface upward, coating photoresist, baking and curing; exposing and developing, photoetching a target pattern, etching to form an N-type depressed area 3, wherein the area which is not etched is an N-type non-depressed area 4, and removing the photoresist on the surface of the N-type non-depressed area 4;
s7: preparing an N electrode 8 on the N surface of the epitaxial wafer from the epitaxial wafer processed in the step S6, wherein the N electrode 8 covers the whole N surface of the epitaxial wafer; and (4) cleaving the plated film by adopting a rapid annealing furnace alloy to obtain a finished product.
In this embodiment, the positions of the P-type recessed region 2 and the N-type non-recessed region 4 correspond to each other; the insulating layer 6 is SiNx.
Example 3:
s1: taking a substrate 12, and growing an N-type lower cladding layer 11, an active region 10 and a P-type upper cladding layer 9 on the substrate 12 in sequence to obtain an epitaxial wafer;
s2: taking the prepared epitaxial wafer, putting the P surface of the epitaxial wafer on a spin coater with the P surface upward, coating photoresist on the P-type upper cladding 9, and baking and curing; exposing and developing, photoetching a target pattern on the mask layer, etching to form a plurality of P-type depressed regions 2, wherein the regions which are not etched are P-type non-depressed regions 1, and removing the photoresist on the surface of the P-type non-depressed regions 1;
s3: etching a ridge structure 5 on the P-type non-depressed area 1, wherein the ridge structure 5 is deep into the upper cladding layer;
s4: taking an epitaxial wafer with a ridge structure 5, and growing an insulating layer 6 on the surface of the epitaxial wafer by adopting a vapor deposition method; placing the epitaxial wafer on a spin coater, coating a layer of photoresist on the surface of the insulating layer 6, exposing and developing to expose the ridge structure 5 region, etching off the insulating layer 6, and removing the photoresist on the surface of the epitaxial wafer; the insulating layer 6 covers the upper surface of the epitaxial layer and the side surface of the ridge-type structure 5;
s5: taking the epitaxial wafer processed in the step S4, preparing a P electrode 7 on the P-type non-recessed area 1, covering the P electrode 7 on the ridge-type structure 5 to form tube core structures, wherein N is more than or equal to 1 when the number of the tube core structures is N, and the tube core structures are arranged periodically;
s6: taking the epitaxial wafer processed in the step S5, grinding and polishing the substrate 12, placing the epitaxial wafer on a photoresist spinner with the N surface upward, coating photoresist, baking and curing; exposing and developing, photoetching a target pattern, etching to form an N-type depressed area 3, wherein the area which is not etched is an N-type non-depressed area 4, and removing the photoresist on the surface of the N-type non-depressed area 4;
s7: preparing an N electrode 8 on the N surface of the epitaxial wafer from the epitaxial wafer processed in the step S6, wherein the N electrode 8 covers the whole N surface of the epitaxial wafer; and (4) cleaving the plated film by adopting a rapid annealing furnace alloy to obtain a finished product.
In this embodiment, the positions of the P-type recessed region 2 and the N-type non-recessed region 4 correspond to each other; the insulating layer 6 is SiNO.
Example 4:
s1: taking a substrate 12, and growing an N-type lower cladding layer 11, an active region 10 and a P-type upper cladding layer 9 on the substrate 12 in sequence to obtain an epitaxial wafer;
s2: taking the prepared epitaxial wafer, putting the P surface of the epitaxial wafer on a spin coater with the P surface upward, coating photoresist on the P-type upper cladding 9, and baking and curing; exposing and developing, photoetching a target pattern on the mask layer, etching to form a plurality of P-type depressed regions 2, wherein the regions which are not etched are P-type non-depressed regions 1, and removing the photoresist on the surface of the P-type non-depressed regions 1;
s3: etching a ridge structure 5 on the P-type non-depressed area 1, wherein the ridge structure 5 is deep into the upper cladding layer;
s4: taking an epitaxial wafer with a ridge structure 5, placing the epitaxial wafer on a spin coater, coating a layer of photoresist on the surface of the epitaxial wafer, exposing, developing and corroding, wherein the photoresist covers the surface of the ridge structure 5; growing an insulating layer 6 on the surface of the epitaxial wafer by adopting a vapor deposition method, and then removing the photoresist on the surface of the epitaxial wafer; the insulating layer 6 covers the upper surface of the epitaxial layer and the side surface of the ridge-type structure 5;
s5: taking the epitaxial wafer processed in the step S4, preparing a P electrode 7 on the P-type non-recessed area 1, covering the P electrode 7 on the ridge-type structure 5 to form tube core structures, wherein N is more than or equal to 1 when the number of the tube core structures is N, and the tube core structures are arranged periodically;
s6: taking the epitaxial wafer processed in the step S5, grinding and polishing the substrate 12, placing the epitaxial wafer on a photoresist spinner with the N surface upward, coating photoresist, baking and curing; exposing and developing, photoetching a target pattern, etching to form an N-type depressed area 3, wherein the area which is not etched is an N-type non-depressed area 4, and removing the photoresist on the surface of the N-type non-depressed area 4;
s7: preparing an N electrode 8 on the N surface of the epitaxial wafer from the epitaxial wafer processed in the step S6, wherein the N electrode 8 covers the whole N surface of the epitaxial wafer; and (4) cleaving the plated film by adopting a rapid annealing furnace alloy to obtain a finished product.
In this embodiment, the positions of the P-type recessed region 2 and the N-type non-recessed region 4 correspond to each other; the insulating layer 6 is SiO2。
Example 5:
s1: taking a substrate 12, and growing an N-type lower cladding layer 11, an active region 10 and a P-type upper cladding layer 9 on the substrate 12 in sequence to obtain an epitaxial wafer;
s2: etching a ridge structure 5 on the P surface of the prepared epitaxial wafer, wherein the ridge structure 5 is deep into the upper cladding layer;
s3: taking an epitaxial wafer with a ridge structure 5, placing the epitaxial wafer on a photoresist spinner with the P surface facing upwards, coating photoresist on a P-type upper cladding 9, and baking and curing; exposing and developing, photoetching a target pattern on the mask layer, etching to form a plurality of P-type depressed regions 2, wherein the regions which are not etched are P-type non-depressed regions 1, removing the photoresist on the surface of the P-type non-depressed regions 1, and then positioning the ridge-shaped structures 5 on the P-type non-depressed regions 1;
s4: taking an epitaxial wafer with a ridge structure 5, placing the epitaxial wafer on a spin coater, coating a layer of photoresist on the surface of the epitaxial wafer, exposing, developing and corroding, wherein the photoresist covers the surface of the ridge structure 5; growing an insulating layer 6 on the surface of the epitaxial wafer by adopting a vapor deposition method, and then removing the photoresist on the surface of the epitaxial wafer; the insulating layer 6 covers the upper surface of the epitaxial layer and the side surface of the ridge-type structure 5;
s5: taking the epitaxial wafer processed in the step S4, preparing a P electrode 7 on the P-type non-recessed area 1, covering the P electrode 7 on the ridge-type structure 5 to form tube core structures, wherein N is more than or equal to 1 when the number of the tube core structures is N, and the tube core structures are arranged periodically;
s6: taking the epitaxial wafer processed in the step S5, grinding and polishing the substrate 12, placing the epitaxial wafer on a photoresist spinner with the N surface upward, coating photoresist, baking and curing; exposing and developing, photoetching a target pattern, etching to form an N-type depressed area 3, wherein the area which is not etched is an N-type non-depressed area 4, and removing the photoresist on the surface of the N-type non-depressed area 4;
s7: preparing an N electrode 8 on the N surface of the epitaxial wafer from the epitaxial wafer processed in the step S6, wherein the N electrode 8 covers the whole N surface of the epitaxial wafer; and (4) cleaving the plated film by adopting the furnace tube alloy to obtain a finished product.
In this embodiment, the positions of the P-type recessed region 2 and the N-type non-recessed region 4 correspond to each other; the insulating layer 6 is SiO2。
And (4) conclusion: after the chip is prepared and coated, the chip is cleaved into the bars 13 during coating, the bars 13 are mutually stacked, the adjacent bars 13 can be mutually matched and placed through the P-type depressed area 2 and the N-type non-depressed area 4, and the filler strips 14 are placed at two ends for coating.
The chip prepared by the invention can reduce the bending degree of the bars 13 by adopting the P/N surface corresponding concave-convex structure of the epitaxial wafer, when the bars are swung, the pipe core of the P surface of the bar 13 is embedded into the N-type concave area 3 of the adjacent bar 13, and the P/N electrodes are not contacted, thereby avoiding the scratch pollution, the damage and the mutual diffusion between metals in the coating process and improving the product performance; meanwhile, the cushion strips 14 are saved, the cost is reduced, and the productivity is improved.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (9)
1. A preparation method of a semiconductor laser chip is characterized by comprising the following steps: the method comprises the following steps:
1) growing an epitaxial wafer;
2) preparing a P-type depressed area (2) and a P-type non-depressed area (1) on the P surface of the epitaxial wafer;
3) preparing a P electrode (7);
4) preparing an N-type depressed region (3) and an N-type non-depressed region (4) on the N surface of the epitaxial wafer;
5) preparing an N electrode (8);
6) and (4) alloying, and cleaving the plated film to obtain a finished product.
2. A method of fabricating a semiconductor laser chip as claimed in claim 1, wherein: the method comprises the following steps:
1) and (3) epitaxial wafer growth: taking a substrate (12), and growing an N-type lower cladding layer (11), an active region (10) and a P-type upper cladding layer (9) on the substrate (12) in sequence to obtain an epitaxial wafer;
2) preparing a P-type depressed area (2) and a P-type non-depressed area (1) on the P surface of the epitaxial wafer;
a) taking the epitaxial wafer prepared in the step 1), placing the epitaxial wafer on a photoresist spinner with the P surface upward, coating photoresist on a P-type upper cladding (9), and baking and curing;
b) exposing and developing, photoetching a target pattern on the mask layer, etching to form a plurality of P-type depressed regions (2), wherein the regions which are not etched are P-type non-depressed regions (1), and removing the photoresist on the surface of the P-type non-depressed regions (1);
c) etching a ridge structure (5) on the P-type non-depressed area (1), wherein the ridge structure (5) is deep into the upper cladding layer;
d) preparing an insulating layer (6) on the P surface of the epitaxial wafer, wherein the insulating layer (6) covers the upper surface of the epitaxial layer and the side surface of the ridge-type structure (5);
3) taking the epitaxial wafer processed in the step 2), preparing a P electrode (7) on the P-type non-depressed area (1), wherein the P electrode (7) covers the ridge structure (5)
Forming tube core structures, wherein N is more than or equal to 1 if the number of the tube core structures is N;
4) preparing an N-type depressed region (3) and an N-type non-depressed region (4) on the N surface of the epitaxial wafer;
a) taking the epitaxial wafer processed in the step 3), grinding and polishing the substrate (12), placing the epitaxial wafer on a spin coater with the N surface facing upwards, coating photoresist, baking and curing;
b) exposing and developing, photoetching a target pattern, etching to form an N-type depressed region (3), wherein the region which is not etched is an N-type non-depressed region (4), and removing the photoresist on the surface of the N-type non-depressed region (4);
5) taking the epitaxial wafer processed in the step 4), and preparing an N electrode (8) on the N surface of the epitaxial wafer, wherein the N electrode (8) covers the whole N surface of the epitaxial wafer;
6) and (4) cleaving the plated film by adopting a rapid annealing furnace alloy to obtain a finished product.
3. A method of fabricating a semiconductor laser chip as claimed in claim 2, wherein: the width of the P-type depressed region (2) is dP1The width of the P-type non-depressed region (1) is dP2The width of the N-type concave region (3) is dN1Then MdP2+(M-1)dP1＜dN1＜MdP2+MdP1，M≥1。
4. A method of fabricating a semiconductor laser chip as claimed in claim 2, wherein: the depth of the N-shaped depressed region (3) is hNThe depth of the P-shaped depressed area (2) is hPThen h isN＞hP。
5. A method of fabricating a semiconductor laser chip as claimed in claim 2, wherein: in the step 2), the insulating layer (6) is any one of SiO2, SiNx and SiNO.
6. A method of fabricating a semiconductor laser chip as claimed in claim 2, wherein: step 2) preparing an insulating layer (6), which comprises the following specific steps:
A. taking an epitaxial wafer with a ridge structure (5), and growing an insulating layer (6) on the surface of the epitaxial wafer by adopting a vapor deposition method;
B. placing the epitaxial wafer on a photoresist spinner, coating a layer of photoresist on the surface of the insulating layer (6), exposing and developing to expose the ridge-shaped structure (5) area, and then corroding the insulating layer (6);
C. and removing the photoresist on the surface of the epitaxial wafer to finish the operation.
7. A method of fabricating a semiconductor laser chip as claimed in claim 2, wherein: step 2) preparing an insulating layer (6), which comprises the following specific steps:
A. taking an epitaxial wafer with a ridge structure (5), placing the epitaxial wafer on a spin coater, coating a layer of photoresist on the surface of the epitaxial wafer, exposing, developing and corroding,
at the moment, the surface of the ridge structure (5) is covered with photoresist;
B. growing an insulating layer (6) on the surface of the epitaxial wafer by adopting a vapor deposition method;
C. and removing the photoresist on the surface of the epitaxial wafer to finish the operation.
8. A method of fabricating a semiconductor laser chip as claimed in claim 2, wherein: the positions of the P-type sunken area (2) and the N-type non-sunken area (4) correspond.
9. A method of fabricating a semiconductor laser chip as claimed in claim 2, wherein: in step 3), the tube core structures are arranged periodically.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117498143A (en) * | 2023-11-07 | 2024-02-02 | 苏州镓锐芯光科技有限公司 | Semiconductor laser bar cleavage method |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1890782A (en) * | 2003-12-05 | 2007-01-03 | 昭和电工株式会社 | Method for production of semiconductor chip and semiconductor chip |
| US20090101927A1 (en) * | 2007-09-03 | 2009-04-23 | Rohm Co.,Ltd. | Method of manufacturing light emitting device |
| CN103138155A (en) * | 2011-12-02 | 2013-06-05 | 日亚化学工业株式会社 | Semiconductor laser element and method of manufacturing the same |
| CN205811271U (en) * | 2016-06-30 | 2016-12-14 | 西安立芯光电科技有限公司 | A kind of plating films on cavity surfaces of semiconductor lasers fixture assembling structure |
| CN106785920A (en) * | 2016-12-29 | 2017-05-31 | 西安炬光科技股份有限公司 | A kind of semiconductor laser stacks of mechanical connection type |
| CN108631153A (en) * | 2017-03-22 | 2018-10-09 | 山东华光光电子股份有限公司 | A kind of total reflection light waveguide semiconductor chip of laser and preparation method thereof |
-
2019
- 2019-11-29 CN CN201911205144.XA patent/CN112993756B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1890782A (en) * | 2003-12-05 | 2007-01-03 | 昭和电工株式会社 | Method for production of semiconductor chip and semiconductor chip |
| US20090101927A1 (en) * | 2007-09-03 | 2009-04-23 | Rohm Co.,Ltd. | Method of manufacturing light emitting device |
| CN103138155A (en) * | 2011-12-02 | 2013-06-05 | 日亚化学工业株式会社 | Semiconductor laser element and method of manufacturing the same |
| CN205811271U (en) * | 2016-06-30 | 2016-12-14 | 西安立芯光电科技有限公司 | A kind of plating films on cavity surfaces of semiconductor lasers fixture assembling structure |
| CN106785920A (en) * | 2016-12-29 | 2017-05-31 | 西安炬光科技股份有限公司 | A kind of semiconductor laser stacks of mechanical connection type |
| CN108631153A (en) * | 2017-03-22 | 2018-10-09 | 山东华光光电子股份有限公司 | A kind of total reflection light waveguide semiconductor chip of laser and preparation method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117498143A (en) * | 2023-11-07 | 2024-02-02 | 苏州镓锐芯光科技有限公司 | Semiconductor laser bar cleavage method |
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