CN112992890A - 一种高压静电防护器件和电路 - Google Patents
一种高压静电防护器件和电路 Download PDFInfo
- Publication number
- CN112992890A CN112992890A CN201911282991.6A CN201911282991A CN112992890A CN 112992890 A CN112992890 A CN 112992890A CN 201911282991 A CN201911282991 A CN 201911282991A CN 112992890 A CN112992890 A CN 112992890A
- Authority
- CN
- China
- Prior art keywords
- injection region
- well injection
- protection device
- voltage electrostatic
- well
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000002347 injection Methods 0.000 claims abstract description 113
- 239000007924 injection Substances 0.000 claims abstract description 113
- 238000002955 isolation Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 8
- 239000007943 implant Substances 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
本发明公开一种高压静电防护器件和电路,其中高压静电防护器件,包括P型衬底,所述P型衬底上设置有N型隔离层,所述N型隔离层上设置有N阱注入区和P阱注入区,所述N阱注入区和P阱注入区并排设置,所述N阱注入区顶部中间设置有N+注入区,所述P阱注入区顶部中间设置有P+注入区,N+注入区用于作为器件的阴极,P+注入区用于作为器件的阳极。方案结构简单,可以实现高压静电防护,同时能够提供负电位的保护,且具有较强的兼容性,能够用于不同的工艺和耐压。
Description
技术领域
本发明涉及半导体静电防护领域,尤其涉及一种高压静电防护器件和电路。
背景技术
静电防护(Electrostatic Discharge,ESD)是集成电路版图设计中的主要问题之一。现在集成电路发展迅速,工艺种类和芯片类型繁多,如何设计出一种通用的,简单的,有效的,小面积的高压ESD保护器件成为所有人关注的问题。
通常情况下,大家选择高压N金属氧化半导体(HVNMOS)晶体管或高压可控硅整流器(HVSCR)结构作为ESD保护器件,如图1和2所示。但是存在有如下问题:
1.如图1所示,HVNMOS作为ESD保护器件不能保护负电位(<0V)的PAD,且面积较大;隔离HVNMOS虽然可以用在负电位的PAD上,但大多数情况下需要添加层次,且版图所需面积更大。
2.HVSCR结构作为ESD保护器件虽然有较小的面积和较高的ESD能力,但结构复杂且对工艺的兼容性不高。
发明内容
为此,需要提供一种高压静电防护器件和电路,解决现有ESD保护器件结构复杂问题。
为实现上述目的,发明人提供了一种高压静电防护器件,包括P型衬底,所述P型衬底上设置有N型隔离层,所述N型隔离层上设置有N阱注入区和P阱注入区,所述N阱注入区和P阱注入区并排设置,所述N阱注入区顶部中间设置有N+注入区,所述P阱注入区顶部中间设置有P+注入区,N+注入区用于作为器件的阴极,P+注入区用于作为器件的阳极。
进一步地,所述N+注入区与P+注入区之间的所述N阱注入区和P阱注入区的尺寸与器件耐压值相关。
进一步地,所述N型隔离层被省去。
进一步地,所述N阱注入区和P阱注入区的数量为多个,所述N阱注入区和P阱注入区依次循环排列,相邻的所述N阱注入区之间设置有P阱注入区,相邻的所述P阱注入区之间设置有N阱注入区。
进一步地,所述器件表面覆盖有场氧化层,所述场氧化层上设置导电层,所述导电层分别与N+注入区、P+注入区连接。
进一步地,所述导电层为金属层。
本发明提供一种高压静电防护电路,所述电路包含有高压静电防护器件,所述高压静电防护器件为本发明任意一项实施例所述的高压静电防护器件,所述电路包含正电位点或者负电位点,所述高压静电防护器件的阳极、阴极分别与电路电源负极、正电位点连接或者所述高压静电防护器件的阳极、阴极分别与负电位点、电路电源正极连接。
区别于现有技术,上述技术方案结构简单,可以实现高压静电防护,同时能够提供负电位的保护,且具有较强的兼容性,能够用于不同的工艺和耐压。
附图说明
图1为背景技术所述一种简单结构的高压NMOS管剖面结构图;
图2为背景技术所述一种SCR静电防护器件结构图;
图3为本发明一种可选方案的剖面结构示意图;
图4为本发明一实施例的可靠性分析结果图;
图5是本发明另一种可选方案的器件剖面结构示意图;
图6是图5所示器件的俯视图。
附图标记说明:
1、N+注入区;
2、P+注入区;
3、N阱注入区;
4、P阱注入区;
5、N型隔离层;
6、P型衬底;
7、导电层。
具体实施方式
为详细说明技术方案的技术内容、构造特征、所实现目的及效果,以下结合具体实施例并配合附图详予说明。
请参阅图3到图6,本实施例提供一种高压静电防护器件,包括P型衬底6,所述P型衬底上设置有N型隔离层5,所述N型隔离层5上设置有N阱注入区3和P阱注入区4,所述N阱注入区3和P阱注入区4并排设置。所述N阱注入区3顶部中间设置有N+注入区1,即N阱注入区3的内部设置有N+注入区1。所述P阱注入区4顶部中间设置有P+注入区2,即P阱注入区4内部设置有P+注入区2。N+注入区1用于作为器件的阴极(Cathode),P+注入区2用于作为器件的阳极(Anode)。
上述静电防护器件阴极接防护电压点(正),阳极接地;或器件阳极接防护电压点(负),阴极接电源。当ESD器件工作在正向到导通时,通过正偏结将ESD电流泄放到电源或地上;当ESD器件工作在反向截止时,通过反偏结的反向击穿,使ESD电流泄放到地。通过可靠性试验,如图4所示,上述静电防护器件可以实现±2000V的静电防护,作为高压ESD防护是可行的。
反向击穿电压决定了ESD电流泄放的速度。根据不同的工艺和芯片耐压,可以通过调节X(N+注入区1与P+注入区2之间N阱注入区3)和Y(P+注入区2与N+注入区1之间P阱注入区4的)的尺寸选择合适的反向击穿电压,即所述N+注入区1与P+注入区2之间的所述N阱注入区3和P阱注入区4的尺寸与器件耐压值相关。这使上述静电防护器件具有很高的兼容性。
上述静电防护器件,所述N阱注入区3内包括有N+注入区1可用半导体工艺最小尺寸;所述P阱注入区4内包括P+注入区2可用半导体工艺最小尺寸。在一可选实施例中,若对地做ESD保护,阳极接电源负极VSS,即P阱注入区4中的P+注入区2接VSS,可将N型隔离层5省去。
为了加快器件电流泄放,所述N阱注入区3和P阱注入区4的数量为多个,所述N阱注入区3和P阱注入区4依次循环列,相邻的所述N阱注入区3之间设置有P阱注入区4,相邻的所述P阱注入区4之间设置有N阱注入区3。而后阳极应当与多个的N+注入区1进行连接,阴极应当与多个的P+注入区2连接。在某些实施例中,所述为高压器件,P型衬底6外侧包覆在N阱注入区3和P阱注入区4的四周,及N阱注入区3和P阱注入区4陷入在P型衬底6中,可使所述器件阴极与P型衬底之间承受高压差。
如图6所示,所述器件表面覆盖有场氧化层,所述场氧化层上设置导电层7,所述导电层分别与N+注入区1、P+注入区2连接。优选的,所述导电层为金属层。场氧化层用于起到绝缘的作用,导电层用于实现对N+注入区1的连接,不同的导电层还用于实现P+注入区2,从而通过连接导电层可以实现与N+注入区1或者P+注入区2的连接。
本发明提供一种高压静电防护电路,所述电路包含有高压静电防护器件,所述高压静电防护器件为本发明任意一项实施例所述的高压静电防护器件,即上述的静电防护器件可以应用于集成电路中。所述电路包含正电位点(正电位PAD)或者负电位点(负电位PAD),所述高压静电防护器件的阳极、阴极分别与电路电源负极、正电位点连接或者所述高压静电防护器件的阳极、阴极分别与负电位点、电路电源正极连接。其具体线路连接方式如下:1.当PAD电位为正电位时,Cathode端接PAD,即N阱注入区3中的N+注入区1接PAD;Anode接VSS,即P阱注入区4中的P+注入区2接VSS。2.当PAD电位出现负电位是,Cathode接电源正极VDD,即N阱注入区3中的N+注入区1接VDD;Anode接PAD,即P阱注入区4中的P+注入区2接PAD。从而实现电路的正电位点或者负电位点的高压静电防护。
需要说明的是,尽管在本文中已经对上述各实施例进行了描述,但并非因此限制本发明的专利保护范围。因此,基于本发明的创新理念,对本文所述实施例进行的变更和修改,或利用本发明说明书及附图内容所作的等效结构或等效流程变换,直接或间接地将以上技术方案运用在其他相关的技术领域,均包括在本发明的专利保护范围之内。
Claims (7)
1.一种高压静电防护器件,其特征在于:包括P型衬底(6),所述P型衬底上设置有N型隔离层(5),所述N型隔离层(5)上设置有N阱注入区(3)和P阱注入区(4),所述N阱注入区(3)和P阱注入区(4)并排设置,所述N阱注入区(3)顶部中间设置有N+注入区(1),所述P阱注入区(4)顶部中间设置有P+注入区(2),N+注入区(1)用于作为器件的阴极,P+注入区(2)用于作为器件的阳极。
2.根据权利要求1所述的一种高压静电防护器件,其特征在于:所述N+注入区(1)与P+注入区(2)之间的所述N阱注入区(3)和P阱注入区(4)的尺寸与器件耐压值相关。
3.根据权利要求1所述的一种高压静电防护器件,其特征在于:所述N型隔离层(5)被省去。
4.根据权利要求1所述的一种高压静电防护器件,其特征在于:所述N阱注入区(3)和P阱注入区(4)的数量为多个,所述N阱注入区(3)和P阱注入区(4)依次循环排列,相邻的所述N阱注入区(3)之间设置有P阱注入区(4),相邻的所述P阱注入区(4)之间设置有N阱注入区(3)。
5.根据权利要求1所述的一种高压静电防护器件,其特征在于:所述器件表面覆盖有场氧化层,所述场氧化层上设置导电层,所述导电层分别与N+注入区(1)、P+注入区(2)连接。
6.根据权利要求5所述的一种高压静电防护器件,其特征在于:所述导电层为金属层。
7.一种高压静电防护电路,其特征在于:所述电路包含有高压静电防护器件,所述高压静电防护器件为权利要求1到6任意一项所述的高压静电防护器件,所述电路包含正电位点或者负电位点,所述高压静电防护器件的阳极、阴极分别与电路电源负极、正电位点连接或者所述高压静电防护器件的阳极、阴极分别与负电位点、电路电源正极连接。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201911282991.6A CN112992890B (zh) | 2019-12-13 | 2019-12-13 | 一种高压静电防护器件和电路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201911282991.6A CN112992890B (zh) | 2019-12-13 | 2019-12-13 | 一种高压静电防护器件和电路 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN112992890A true CN112992890A (zh) | 2021-06-18 |
CN112992890B CN112992890B (zh) | 2024-06-25 |
Family
ID=76332442
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201911282991.6A Active CN112992890B (zh) | 2019-12-13 | 2019-12-13 | 一种高压静电防护器件和电路 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN112992890B (zh) |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR19990006106A (ko) * | 1997-06-30 | 1999-01-25 | 김영환 | 저전압 특성 개선을 위한 반도체 소자 |
CN102064173A (zh) * | 2009-11-17 | 2011-05-18 | 无锡华润矽科微电子有限公司 | 一种可控硅整流器静电防护器件 |
CN103094278A (zh) * | 2012-12-09 | 2013-05-08 | 辽宁大学 | Pmos嵌入的低压触发用于esd保护的scr器件 |
US20140225159A1 (en) * | 2013-02-08 | 2014-08-14 | Issc Technologies Corp. | Electrostatic discharge protection device and electronic apparatus thereof |
KR20150138938A (ko) * | 2014-05-30 | 2015-12-11 | 단국대학교 산학협력단 | 저전압용 정전기 방전 보호소자 |
CN210926016U (zh) * | 2019-12-13 | 2020-07-03 | 福建省福芯电子科技有限公司 | 一种高压静电防护器件和电路 |
-
2019
- 2019-12-13 CN CN201911282991.6A patent/CN112992890B/zh active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR19990006106A (ko) * | 1997-06-30 | 1999-01-25 | 김영환 | 저전압 특성 개선을 위한 반도체 소자 |
CN102064173A (zh) * | 2009-11-17 | 2011-05-18 | 无锡华润矽科微电子有限公司 | 一种可控硅整流器静电防护器件 |
CN103094278A (zh) * | 2012-12-09 | 2013-05-08 | 辽宁大学 | Pmos嵌入的低压触发用于esd保护的scr器件 |
US20140225159A1 (en) * | 2013-02-08 | 2014-08-14 | Issc Technologies Corp. | Electrostatic discharge protection device and electronic apparatus thereof |
KR20150138938A (ko) * | 2014-05-30 | 2015-12-11 | 단국대학교 산학협력단 | 저전압용 정전기 방전 보호소자 |
CN210926016U (zh) * | 2019-12-13 | 2020-07-03 | 福建省福芯电子科技有限公司 | 一种高压静电防护器件和电路 |
Also Published As
Publication number | Publication date |
---|---|
CN112992890B (zh) | 2024-06-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7786504B2 (en) | Bidirectional PNPN silicon-controlled rectifier | |
US7615826B2 (en) | Electrostatic discharge protection semiconductor structure | |
EP2140491B1 (en) | Stacked esd protection circuit having reduced trigger voltage | |
JP6215222B2 (ja) | 高保持電圧、混合電圧ドメイン静電気放電クランプ | |
US7763908B2 (en) | Design of silicon-controlled rectifier by considering electrostatic discharge robustness in human-body model and charged-device model devices | |
US9627372B2 (en) | Electrostatic discharge protection device | |
US10068893B2 (en) | Diode-based ESD concept for DEMOS protection | |
US20080048266A1 (en) | ESD protection device and method | |
US20070069310A1 (en) | Semiconductor controlled rectifiers for electrostatic discharge protection | |
US20130119433A1 (en) | Isolation structure for esd device | |
US6433979B1 (en) | Electrostatic discharge protection device using semiconductor controlled rectifier | |
US8703547B2 (en) | Thyristor comprising a special doped region characterized by an LDD region and a halo implant | |
US8610216B2 (en) | Structure for protecting an integrated circuit against electrostatic discharges | |
KR101043737B1 (ko) | 정전기 방전 보호 소자 | |
US20220310589A1 (en) | Integrated circuit device and method for esd protection | |
CN103165600A (zh) | 一种esd保护电路 | |
US7449751B2 (en) | High voltage operating electrostatic discharge protection device | |
US6455898B1 (en) | Electrostatic discharge input protection for reducing input resistance | |
US7023676B2 (en) | Low-voltage triggered PNP for ESD protection in mixed voltage I/O interface | |
CN210926016U (zh) | 一种高压静电防护器件和电路 | |
KR20100097420A (ko) | 정전기 방전 보호 소자 및 이를 포함하는 정전기 방전 보호회로 | |
US6466423B1 (en) | Electrostatic discharge protection device for mixed voltage application | |
TWI718611B (zh) | 高電壓電路裝置及其環形電路布局 | |
US7285837B2 (en) | Electrostatic discharge device integrated with pad | |
CN108780794B (zh) | 一种静电放电防护电路 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |