CN112992810B - Semiconductor packaging structure and manufacturing method thereof - Google Patents

Semiconductor packaging structure and manufacturing method thereof Download PDF

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Publication number
CN112992810B
CN112992810B CN202110473757.2A CN202110473757A CN112992810B CN 112992810 B CN112992810 B CN 112992810B CN 202110473757 A CN202110473757 A CN 202110473757A CN 112992810 B CN112992810 B CN 112992810B
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chip
substrate
bonding pad
pads
bonding
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CN112992810A (en
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张吉钦
何正鸿
张超
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Forehope Electronic Ningbo Co Ltd
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Forehope Electronic Ningbo Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A semiconductor packaging structure and a manufacturing method thereof relate to the technical field of semiconductor packaging. The manufacturing method comprises the steps of providing a substrate, wherein a first bonding pad, a second bonding pad and a plurality of third bonding pads which are arranged around the peripheries of the first bonding pad and the second bonding pad are formed on the substrate; the two opposite third bonding pads are connected in a metal routing mode to form a plurality of connecting lines; mounting a chip on a substrate, and electrically connecting the chip with a first bonding pad and a second bonding pad respectively in a metal routing manner, wherein a connecting wire is positioned between the bottom of the chip and the substrate; forming a plastic packaging layer on the substrate, wherein the plastic packaging layer covers the chip, the connecting wire, the first bonding pad and the second bonding pad to form a plastic packaging body; and forming a solder ball on the surface of the substrate far away from the chip by a ball planting process. The manufacturing method of the semiconductor packaging structure can improve the heat dissipation effect of the packaged product.

Description

Semiconductor packaging structure and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging structure and a manufacturing method thereof.
Background
With the rapid development of integrated circuits, the volume of a semiconductor package structure is smaller and smaller, and at the same time, the power of a chip in the semiconductor package structure is larger and larger, so that the heat flux density (i.e., the amount of heat passing through per unit time in a cross section of a unit area) in the semiconductor package structure is increased. With the increasing heat flux density, failure to effectively dissipate heat can easily result in the chip or system being out of service due to excessive temperatures.
In the conventional packaging process, heat dissipation is generally performed by two methods, the first method is to design a copper layer on a substrate, so that heat at the bottom of a chip is conducted to the substrate through the copper layer to improve heat conduction performance. However, the heat dissipation method will lead to the increase of the residual copper ratio inside the substrate, and the expansion and shrinkage problems caused by the mismatch of the thermal expansion coefficients of the substrate and the chip are brought along with the increase and shrinkage of the residual copper ratio; the second method is to mount a heat sink metal on the substrate to dissipate heat by conducting heat from the bottom of the chip to the heat sink metal, but this heat dissipation method will result in an increase in the overall volume of the semiconductor package structure.
Disclosure of Invention
The invention aims to provide a semiconductor packaging structure and a manufacturing method thereof, which can improve the heat dissipation effect of a packaged product.
The embodiment of the invention is realized by the following steps:
in one aspect of the invention, a method for manufacturing a semiconductor packaging structure is provided, the method includes providing a substrate, on which a first bonding pad, a second bonding pad and a plurality of third bonding pads surrounding the peripheries of the first bonding pad and the second bonding pad are formed; the two opposite third bonding pads are connected in a metal routing mode to form a plurality of connecting lines; mounting a chip on a substrate, and electrically connecting the chip with a first bonding pad and a second bonding pad respectively in a metal routing manner, wherein a connecting wire is positioned between the bottom of the chip and the substrate; forming a plastic packaging layer on the substrate, wherein the plastic packaging layer covers the chip, the connecting wire, the first bonding pad and the second bonding pad to form a plastic packaging body; and forming a solder ball on the surface of the substrate far away from the chip by a ball planting process. The manufacturing method of the semiconductor packaging structure can improve the heat dissipation effect of the packaged product.
Optionally, the plurality of third pads are all disposed on the scribe line of the substrate.
Optionally, after forming the solder balls on the side of the substrate away from the chip by the ball mounting process, the method further includes: and cutting the substrate and the plastic package body along the cutting path to expose the connecting lines from the side wall of the plastic package body.
Optionally, the substrate is a baseplate; paste dress chip on the substrate to with the chip respectively with first pad and second pad through the mode electricity of metal routing connect, wherein, the connecting wire is located between the bottom of chip and the substrate, include: the chip is attached to the substrate through the heat conduction layer, and the connecting wire is positioned between the chip and the substrate; curing the heat conduction layer by baking so as to fix the chip on the substrate; and electrically connecting the chip with the first bonding pad and the second bonding pad respectively in a metal routing mode.
Optionally, the substrate is a lead frame, a hollow area is formed in a central area of the lead frame through etching, and the plurality of third pads are arranged around the hollow area.
Optionally, before the two third pads are connected by metal wire bonding to form a plurality of connecting lines, the method further includes: and forming a back adhesive film on one surface of the lead frame far away from the third bonding pad.
Optionally, mounting a chip on the substrate, and electrically connecting the chip with the first pad and the second pad by metal wire bonding, wherein the connecting line is located between the bottom of the chip and the substrate, and includes: the chip is attached to one surface, close to the lead frame, of the back adhesive film through the heat conduction layer, wherein the orthographic projection of the chip on the back adhesive film is located in the hollow area, and the connecting line is located between the chip and the back adhesive film; curing the heat conduction layer by baking so as to fix the chip on the back adhesive film; and electrically connecting the chip with the first bonding pad and the second bonding pad respectively in a metal routing mode.
Optionally, after a plastic package layer is formed on the substrate and covers the chip, the connection line, the first pad and the second pad to form a plastic package body, the method further includes: and removing the back sticking film.
Optionally, the heat conducting layer is a heat conducting glue layer or a heat conducting film.
In another aspect of the present invention, a semiconductor package structure is provided, which is manufactured by the above manufacturing method of the semiconductor package structure.
The beneficial effects of the invention include:
the embodiment provides a manufacturing method of a semiconductor packaging structure, which comprises the following steps: providing a substrate, wherein a first bonding pad, a second bonding pad and a plurality of third bonding pads surrounding the peripheries of the first bonding pad and the second bonding pad are formed on the substrate; the two opposite third bonding pads are connected in a metal routing mode to form a plurality of connecting lines; mounting a chip on a substrate, and electrically connecting the chip with a first bonding pad and a second bonding pad respectively in a metal routing manner, wherein a connecting wire is positioned between the bottom of the chip and the substrate; forming a plastic packaging layer on the substrate, wherein the plastic packaging layer covers the chip, the connecting wire, the first bonding pad and the second bonding pad to form a plastic packaging body; and forming a solder ball on the surface of the substrate far away from the chip by a ball planting process. Like this, this application establishes wherein third pad through forming a plurality ofly enclosing first pad and second pad on the substrate to connecting through the mode of metal routing between two relative third pads, and then formed many connecting wires, so, many connecting wires alright constitute the metal support network structure jointly, then paste the chip on the substrate, and locate the metal support network structure between chip and the substrate, like this, the heat of chip bottom alright conduct to the substrate through the metal support network structure, and then spread the heat through the substrate back and carry out effective heat dissipation. Meanwhile, compared with the prior art that a radiating fin or a ceramic chip is pasted on a substrate, the volume of a packaged product can be effectively reduced; compared with the prior art that the copper layer is arranged in the substrate, the problem of expansion and shrinkage caused by mismatching of thermal expansion coefficients of the substrate and the chip can be avoided.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a flowchart illustrating a method for fabricating a semiconductor package structure according to an embodiment of the invention;
fig. 2 is a second schematic flowchart illustrating a manufacturing method of a semiconductor package structure according to an embodiment of the invention;
fig. 3 is a third schematic flow chart illustrating a manufacturing method of a semiconductor package structure according to an embodiment of the present invention;
fig. 4 is a state diagram of a semiconductor package structure according to a first embodiment of the present invention;
fig. 5 is a second state diagram of the semiconductor package structure according to the first embodiment of the present invention;
fig. 6 is a third schematic view illustrating a state of the semiconductor package structure according to the first embodiment of the present invention;
fig. 7 is a fourth state diagram of the semiconductor package structure according to the first embodiment of the present invention;
fig. 8 is a schematic structural diagram of a semiconductor package structure according to a first embodiment of the present invention;
fig. 9 is a second schematic structural diagram of a semiconductor package structure according to the first embodiment of the present invention;
fig. 10 is a schematic structural diagram of a semiconductor package structure according to a second embodiment of the present invention;
fig. 11 is a fourth schematic flowchart illustrating a method for fabricating a semiconductor package structure according to an embodiment of the present invention;
fig. 12 is a fifth flowchart illustrating a method for fabricating a semiconductor package structure according to an embodiment of the present invention;
fig. 13 is a diagram illustrating a semiconductor package structure according to a third embodiment of the present invention;
fig. 14 is a second state diagram of a semiconductor package structure according to a third embodiment of the invention;
fig. 15 is a third schematic view illustrating a semiconductor package structure according to a third embodiment of the present invention;
fig. 16 is a fourth state diagram illustrating a semiconductor package structure according to a third embodiment of the present invention;
fig. 17 is a fifth state diagram illustrating a semiconductor package according to a third embodiment of the present invention;
fig. 18 is a schematic structural diagram of a semiconductor package structure according to a third embodiment of the present invention;
fig. 19 is a schematic structural diagram of a semiconductor package structure according to a fourth embodiment of the invention.
Icon: 10A-a substrate; 10B-a lead frame; 11-a first pad; 12-a second pad; 13-a third pad; 14-connecting lines; 15-a hollowed-out area; 20-chip; 30-plastic package body; 40-solder ball; 50-a thermally conductive layer; 60-back sticking film.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or the orientations or positional relationships that the products of the present invention are usually placed in when used, and are only used for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the devices or elements referred to must have specific orientations, be constructed in specific orientations, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
First embodiment
Referring to fig. 1, the present embodiment provides a method for manufacturing a semiconductor package structure, including:
s100, providing a substrate, on which a first pad 11, a second pad 12 and a plurality of third pads 13 surrounding the first pad 11 and the second pad 12 are formed.
The first bonding pad 11 and the second bonding pad 12 are both chip 20 functional routing bonding pads for realizing functional connection of the chip 20. It should be understood that the first pads 11 and the second pads 12 should be electrically connected to corresponding functional pads on the chip 20 in a one-to-one correspondence, respectively.
In addition, it should be noted that the number of the first pads 11 and the second pads 12 should be the same as the number of the corresponding functional pads on the chip 20, and correspond to each other.
The third pad 13 is provided around the outer peripheries of the first pad 11 and the second pad 12, and the third pad 13 includes a plurality of pads, as shown in fig. 4 and 9, and fig. 4 shows a product before cutting.
Note that, in order to facilitate connection of the functional pads on the chip 20 to the first pads 11 and the second pads 12, the first pads 11 and the second pads 12 are disposed around the chip 20, respectively. In addition, the plurality of third pads 13 provided in this embodiment only surround the first pads 11 and the second pads 12, specifically, the third pads 13 are disposed on two opposite sides of the chip 20, or disposed around the chip 20, which is not limited in this application.
S200, the two opposite third bonding pads 13 are connected in a metal routing mode to form a plurality of connecting lines 14.
As shown in fig. 4 and 9, for example, the third pads 13 on two opposite sides of the chip 20 are correspondingly connected by metal wire bonding. In this way, a metal supporting mesh structure as shown in fig. 9 can be formed.
S300, mounting the chip 20 on the substrate, and electrically connecting the chip 20 with the first bonding pad 11 and the second bonding pad 12 respectively in a metal wire bonding manner, wherein the connecting wire 14 is located between the bottom of the chip 20 and the substrate, as shown in FIG. 5.
That is, the chip 20 is attached to the metal supporting mesh structure formed in step S200, so that the chip 20 is connected and fixed to the substrate and the supporting mesh structure on the substrate. The reason for electrically connecting the chip 20 to the first bonding pad 11 and the second bonding pad 12 by metal wire bonding is to realize the function of the chip 20, which is well known to those skilled in the art and will not be described in detail herein.
In this embodiment, the substrate 10A is used as the substrate.
Thus, referring to fig. 2, the step S300 of mounting the chip 20 on the substrate and electrically connecting the chip 20 with the first pad 11 and the second pad 12 by metal wire bonding, wherein the connecting line 14 is located between the bottom of the chip 20 and the substrate, specifically includes the following steps:
s311, the chip 20 is mounted on the substrate 10A through the heat conductive layer 50, and the connection line 14 is located between the chip 20 and the substrate 10A.
In the present embodiment, the chip 20 is mounted on the substrate 10A by using the heat conduction layer 50, and therefore, the mounting of the chip 20 on the substrate 10A can be realized; secondly, the heat conduction layer 50 of the chip 20 can be beneficial to conduct the heat at the bottom of the chip 20 to the substrate 10A, so as to perform effective heat dissipation.
Here, when the chip 20 is mounted on the substrate 10A through the heat conductive layer 50, the chip 20 is positioned above the connection line 14, and therefore the heat conductive layer 50 also fixes the connection line 14 between the chip 20 and the substrate 10A.
Alternatively, the heat conductive layer 50 may be a silver paste layer, a heat conductive adhesive layer, a heat conductive film, or the like. Of course, the heat conducting layer 50 made of other materials can be selected by those skilled in the art, and the application is not limited as long as the heat conducting layer 50 can attach the chip 20 to the substrate 10A, and the heat conduction from the bottom of the chip 20 to the substrate 10A can be realized through the heat conducting layer 50.
S312, the heat conductive layer 50 is cured by baking, so that the chip 20 is fixed on the substrate 10A.
After the baking process, the connecting wires 14 can also be fixed in the heat conducting layer 50, so that the wire bonding mode at the bottom of the chip 20 (i.e. the connecting wires 14 at the bottom of the chip 20) can play a role in conducting heat and also play a role in buffering; after the heat conduction layer 50 is cured, the connection strength of the connection line 14, the chip 20 and the substrate 10A can be enhanced, so that the overall bonding force of the package structure can be improved, and the heat dissipation effect can be effectively improved.
And S313, electrically connecting the chip 20 with the first bonding pad 11 and the second bonding pad 12 respectively in a metal wire bonding mode.
That is, the first pads 11 and the second pads 12 on the substrate 10A are respectively connected to the functional pads on the chip 20, so that the chip 20 and the substrate 10A are electrically connected.
After step S300 is executed (specifically, after step S313 is executed), the method for manufacturing a semiconductor package structure provided by the present application further includes:
and S400, forming a plastic package layer on the substrate, wherein the plastic package layer covers the chip 20, the connecting line 14, the first bonding pad 11 and the second bonding pad 12 to form a plastic package body 30.
That is, as shown in fig. 6, the molding layer covers the front surface of the substrate 10A to mold and protect all of the chip 20, the connection line 14, the first pad 11, and the second pad 12.
S500, forming the solder ball 40 on the surface of the substrate far away from the chip 20 through a ball mounting process.
As shown in fig. 7, the solder ball 40 is located on the back surface of the substrate 10A (i.e., the surface of the substrate 10A facing away from the chip 20), and it should be understood that the solder ball 40 is used for electrical connection with external devices.
In addition, if the semiconductor package structure is fabricated simultaneously, the method for fabricating a semiconductor package structure according to this embodiment may further include the following steps after the fabrication is completed:
the substrate and the plastic package 30 are cut to form a single product. As shown in fig. 7, fig. 7 is a schematic view of a state where a plurality of products are simultaneously manufactured and after the ball is mounted, and in this embodiment, after the structure shown in fig. 7 is cut, a single product as shown in fig. 8 can be obtained.
Of course, if a single product is produced, no cutting step is required.
In summary, the present embodiment provides a method for manufacturing a semiconductor package structure, including: providing a substrate, wherein a first bonding pad 11, a second bonding pad 12 and a plurality of third bonding pads 13 which are arranged around the peripheries of the first bonding pad 11 and the second bonding pad 12 are formed on the substrate; the two opposite third bonding pads 13 are connected in a metal routing manner to form a plurality of connecting lines 14; mounting a chip 20 on a substrate, and electrically connecting the chip 20 with a first bonding pad 11 and a second bonding pad 12 respectively in a metal routing manner, wherein a connecting wire 14 is positioned between the bottom of the chip 20 and the substrate; forming a plastic package layer on the substrate, wherein the plastic package layer covers the chip 20, the connecting line 14, the first bonding pad 11 and the second bonding pad 12 to form a plastic package body 30; solder balls 40 are formed on the surface of the substrate away from the chip 20 by a ball-mounting process. Thus, the third bonding pads 13 surrounding the first bonding pads 11 and the second bonding pads 12 are formed on the substrate, and the two opposite third bonding pads 13 are connected by the metal routing, so that the connecting wires 14 are formed, the connecting wires 14 can jointly form a metal supporting net structure, then the chip 20 is attached to the substrate, and the metal supporting net structure is arranged between the chip 20 and the substrate, so that the heat at the bottom of the chip 20 can be conducted to the substrate through the metal supporting net structure, and further the heat is conducted out through the back of the substrate to be effectively dissipated. Meanwhile, compared with the prior art that a radiating fin or a ceramic chip is pasted on a substrate, the volume of a packaged product can be effectively reduced; compared with the prior art in which a copper layer is disposed in the substrate, the problem of expansion and shrinkage caused by the mismatch of the thermal expansion coefficients of the substrate 10A and the chip 20 can be avoided.
Second embodiment
The present embodiment is different from the first embodiment in that, in the present embodiment, the plurality of third pads 13 are all disposed on the scribe line of the substrate (specifically, the substrate 10A).
Thus, referring to fig. 3, optionally, after forming the solder balls 40 on the side of the substrate away from the chip 20 by the ball-mounting process, the method further includes:
and S600, cutting the substrate and the plastic package body 30 along the cutting path to expose the connecting lines 14 from the side wall of the plastic package body 30.
As shown in fig. 7, after the substrate and the plastic package 30 are cut along the cutting path, the structure shown in fig. 10 can be obtained, in which the plurality of connecting wires 14 are exposed from the side wall of the plastic package 30, so that the connecting wires 14 are exposed on the outer peripheral wall of the single product, and thus, the heat at the bottom of the chip 20 can be conducted to the outside through the plastic package 30 via the connecting wires 14, thereby achieving heat dissipation of the outer peripheral wall of the package structure.
It should be noted that, in this embodiment, compared with the first embodiment, the connecting wires 14 of the first embodiment do not expose the plastic package body 30, and therefore, in the first embodiment, the connecting wires 14 conduct the heat of the chip 20 to the substrate 10A, and further dissipate the heat through the bottom of the substrate 10A; the heat of the chip 20 is dissipated from the sidewall of the plastic package 30 in this embodiment.
In addition, in the present embodiment, reference may be made to the related description of the first embodiment where the same method for manufacturing the semiconductor package structure is provided in the first embodiment, and the description of the present embodiment is not repeated.
Of course, it should be understood that the chip 20 is attached to the substrate 10A with the heat conductive layer 50 employed in the first embodiment, and the connection lines 14 are located between the chip 20 and the substrate 10A. Thus, the first embodiment can realize the bottom heat dissipation of the substrate 10A through the heat conductive layer 50. Similarly, this embodiment is also applicable to the embodiment, so that the embodiment still has the function of bottom heat dissipation while realizing the heat dissipation of the sidewall of the plastic package body 30.
Third embodiment
The present embodiment is different from the first embodiment in the lead frame 10B used for the substrate in the present embodiment (the base plate 10A is used as the substrate in the first embodiment).
In this embodiment, the substrate is a lead frame 10B, a hollow area 15 is formed in a central area of the lead frame 10B by etching, and the plurality of third pads 13 are disposed around the hollow area 15. Referring to fig. 13, fig. 13 is a schematic structural diagram of the lead frame 10B.
It should be noted that the hollow area 15 is formed in the central area of the lead frame 10B by etching, and the lead frame 10B without the base island may be formed by etching the base island of the existing lead frame (the area generated after the base island is etched away is the hollow area 15).
Referring to fig. 11, before connecting the two opposite third pads 13 by metal wire bonding to form a plurality of connecting lines 14, the method further includes:
s700, a back film 60 is formed on the surface of the lead frame 10B remote from the third pad 13. Please refer to fig. 14.
After step S700 is executed, the following steps S200, S300, and S400 are executed in order.
Namely, the two third pads 13 on the two opposite sides of the hollow area 15 are connected by metal wire bonding, as shown in fig. 15; mounting a chip 20 on the lead frame 10B, and connecting the chip 20 with the first bonding pad 11 and the second bonding pad 12 by metal wire bonding, wherein the connecting wire 14 is located between the bottom of the chip 20 and the substrate, as shown in fig. 16; a molding compound layer is formed on the front surface of the lead frame 10B and covers the chip 20, the connection lines 14, the first pads 11 and the second pads 12 to form a molding compound body 30, as shown in fig. 17.
After forming a molding compound layer on the substrate at the above step S400, the molding compound layer covering the chip 20, the connection line 14, the first pad 11 and the second pad 12 to form the molding compound 30, the method further includes:
s800, removing the back film 60, as shown in FIG. 18.
After step S800 is performed, S500 is continuously performed to perform the ball mounting process.
In addition, it should be noted that, in general, the semiconductor package structure is fabricated by simultaneously fabricating a plurality of semiconductor package structures, and the method for fabricating a semiconductor package structure according to this embodiment may further include the following steps after the fabrication is completed:
the substrate and the plastic package 30 are cut to form a single product. As shown in fig. 18, in the present embodiment, after the structure shown in fig. 18 is cut, a single product as shown in fig. 18 can be obtained.
Referring to fig. 12, when the substrate is a lead frame 10B, in this embodiment, the step S300 mounts the chip 20 on the substrate, and electrically connects the chip 20 to the first pad 11 and the second pad 12 by metal wire bonding, wherein the connection line 14 is located between the bottom of the chip 20 and the substrate, and specifically includes the following steps:
s321, attaching the chip 20 to a surface of the back film 60 close to the lead frame 10B through the heat conductive layer 50, wherein an orthographic projection of the chip 20 on the back film 60 is located in the hollow area 15, and the connection line 14 is located between the chip 20 and the back film 60.
And S322, curing the heat conduction layer 50 through baking so as to fix the chip 20 on the back adhesive film 60.
Thus, after the heat conductive layer 50 is cured, the connection wires 14 can be fixed in the heat conductive layer 50, and the chip 20 can be firmly attached to the back adhesive film 60.
And S323, electrically connecting the chip 20 with the first bonding pad 11 and the second bonding pad 12 respectively in a metal wire bonding mode.
The basic principle of the steps S321 to S323 is similar to that of the first embodiment, and therefore, a person skilled in the art can reasonably derive the beneficial effects of the steps with reference to the related description in the first embodiment, and therefore, the description of the same parts in this embodiment is omitted.
It should be noted that, in the embodiment, the lead frame 10B is used as the substrate, and the hollow area 15 is disposed in the center of the lead frame 10B (that is, the lead frame 10B without the base island is used as the substrate), so that the plurality of connecting lines 14 connecting the two opposite third pads 13 are formed by routing on two sides of the hollow area 15, and the plurality of connecting lines 14 form the metal supporting mesh structure together. Then, the chip 20 is mounted on the metal supporting mesh structure, so that the effect of supporting the chip 20 is achieved through the metal supporting mesh structure, and meanwhile, the heat at the bottom of the chip 20 is conducted to the lead frame 10B through the metal supporting mesh structure, so that a high heat conduction effect is achieved (on the basis that the hollow area 15 is arranged on the lead frame 10B to achieve heat dissipation, the heat at the bottom of the chip 20 is further conducted to the bottom of the lead frame 10B through the metal supporting mesh structure to dissipate heat).
In the embodiment, the lead frame 10B is designed to be a non-base island, so that the residual copper rate on the lead frame 10B can be greatly reduced, and the cost for manufacturing the lead frame 10B can be reduced; meanwhile, the base island-free design can better realize the bottom heat dissipation function, and the heat dissipation effect of the package adopting the lead frame 10B product is greatly improved.
In addition, in the present embodiment, reference may be made to the related description of the first embodiment where the same method for manufacturing the semiconductor package structure is provided in the first embodiment, and the description of the present embodiment is not repeated.
Fourth embodiment
The present embodiment is different from the third embodiment in that, in the present embodiment, the plurality of third pads 13 are all provided on the dicing streets of the substrate (specifically, the lead frame 10B).
Thus, referring to fig. 11, in step S500, after forming the solder balls 40 on the surface of the substrate away from the chip 20 by the ball mounting process, the method further includes:
and S600, cutting the substrate (the matrix is the lead frame 10B) and the plastic package body 30 along the cutting path to expose the connecting lines 14 from the side wall of the plastic package body 30.
After the substrate and the plastic package 30 are cut along the dicing streets, the structure shown in fig. 19 can be obtained, and at this time, the plurality of connecting wires 14 are exposed from the side walls of the plastic package 30, so that the connecting wires 14 are exposed on the outer peripheral wall of the single product, and thus, the heat at the bottom of the chip 20 can be conducted to the outside through the plastic package 30 through the connecting wires 14, and the heat dissipation of the outer peripheral wall of the package structure is realized.
In this embodiment, compared with the third embodiment, the connecting wires 14 of the third embodiment do not expose the plastic package body 30, so in the third embodiment, the connecting wires 14 conduct the heat of the chip 20 to the lead frame 10B, and further dissipate the heat through the bottom of the lead frame 10B; the connecting wires 14 in this embodiment function to dissipate the heat of the chip 20 from the side walls of the plastic package 30.
In addition, in the present embodiment, reference may be made to the related description of the third embodiment where the same method for manufacturing the semiconductor package structure is provided in the third embodiment, and the description of the present embodiment is not repeated.
Of course, it should be understood that the chip 20 is attached to the backing film 60 with the heat conductive layer 50 in the third embodiment, and the connection lines 14 are located between the chip 20 and the backing film 60. Thus, the first embodiment can realize the bottom heat dissipation of the chip 20 through the heat conductive layer 50. Similarly, this embodiment is also applicable to the embodiment, so that the embodiment still has the function of bottom heat dissipation while realizing the heat dissipation of the sidewall of the plastic package body 30.
The invention also provides a semiconductor packaging structure which is manufactured by the manufacturing method of the semiconductor packaging structure.
Since the specific steps and the advantageous effects of the manufacturing method of the semiconductor package structure have been described in detail in the foregoing, and since a person skilled in the art can deduce the specific structure of the semiconductor package structure through the manufacturing method of the semiconductor package structure, the detailed structure and the advantageous effects of the semiconductor package structure will not be described herein again.
The above description is only an alternative embodiment of the present invention and is not intended to limit the present invention, and various modifications and variations of the present invention may occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
It should be noted that the various technical features described in the above embodiments can be combined in any suitable manner without contradiction, and the invention is not described in any way for the possible combinations in order to avoid unnecessary repetition.

Claims (8)

1. A method for manufacturing a semiconductor packaging structure is characterized by comprising the following steps:
providing a substrate, wherein a first bonding pad, a second bonding pad and a plurality of third bonding pads surrounding the peripheries of the first bonding pad and the second bonding pad are formed on the substrate, and the plurality of third bonding pads are all arranged on a cutting path of the substrate;
the two opposite third bonding pads are connected in a metal routing mode to form a plurality of connecting lines;
mounting a chip on the substrate, and electrically connecting the chip with the first bonding pad and the second bonding pad in a metal routing manner respectively, wherein the connecting line is positioned between the bottom of the chip and the substrate;
forming a plastic package layer on the substrate, wherein the plastic package layer covers the chip, the connecting line, the first bonding pad and the second bonding pad to form a plastic package body;
forming a solder ball on one surface of the substrate far away from the chip by a ball mounting process;
and cutting the substrate and the plastic package body along the cutting path so as to expose the connecting line from the side wall of the plastic package body.
2. The method of manufacturing a semiconductor package structure according to claim 1, wherein the substrate is a base plate; the substrate is provided with a chip, the chip is electrically connected with the first bonding pad and the second bonding pad in a metal routing mode respectively, wherein the connecting wire is positioned between the bottom of the chip and the substrate, and the method comprises the following steps:
a chip is attached to the substrate through a heat conduction layer, and the connecting wire is positioned between the chip and the substrate;
curing the heat conduction layer by baking so as to fix the chip on the substrate;
and electrically connecting the chip with the first bonding pad and the second bonding pad respectively in a metal routing mode.
3. The method for manufacturing a semiconductor package structure according to claim 1, wherein the substrate is a lead frame, a hollow area is formed in a central area of the lead frame by etching, and the plurality of third pads are disposed around the hollow area.
4. The method for manufacturing a semiconductor package according to claim 3, wherein before the connecting between the two opposite third pads by means of metal wire bonding to form a plurality of connecting lines, the method further comprises:
and forming a back adhesive film on one surface of the lead frame, which is far away from the third bonding pad.
5. The method for manufacturing a semiconductor package structure according to claim 4, wherein the mounting a chip on the substrate and electrically connecting the chip to the first pad and the second pad by metal wire bonding, wherein the connecting line is located between the bottom of the chip and the substrate, comprises:
a chip is attached to one surface, close to the lead frame, of the back adhesive film through a heat conduction layer, wherein the orthographic projection of the chip on the back adhesive film is located in the hollow area, and the connecting line is located between the chip and the back adhesive film;
curing the heat conduction layer by baking so as to fix the chip on the back adhesive film;
and electrically connecting the chip with the first bonding pad and the second bonding pad respectively in a metal routing mode.
6. The method for manufacturing a semiconductor package structure according to claim 4 or 5, wherein after forming a plastic encapsulation layer on the substrate, the plastic encapsulation layer covering the chip, the connection lines, the first pads and the second pads to form a plastic encapsulation body, the method further comprises:
and removing the back sticking film.
7. The method of claim 5, wherein the thermal conductive layer is a thermal conductive adhesive layer or a thermal conductive film.
8. A semiconductor package structure, characterized by being manufactured by the method for manufacturing a semiconductor package structure according to any one of claims 1 to 7.
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CN1527370A (en) * 2002-11-15 2004-09-08 ��ʽ���������Ƽ� Method for producing semiconductor device
CN101685807A (en) * 2008-09-24 2010-03-31 晶致半导体股份有限公司 Heat radiating type semiconductor packaging element and manufacture method thereof
US20190081012A1 (en) * 2017-09-14 2019-03-14 Shenzhen GOODIX Technology Co., Ltd. Chip packaging structure and method, and electronic device

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Publication number Priority date Publication date Assignee Title
CN1527370A (en) * 2002-11-15 2004-09-08 ��ʽ���������Ƽ� Method for producing semiconductor device
CN101685807A (en) * 2008-09-24 2010-03-31 晶致半导体股份有限公司 Heat radiating type semiconductor packaging element and manufacture method thereof
US20190081012A1 (en) * 2017-09-14 2019-03-14 Shenzhen GOODIX Technology Co., Ltd. Chip packaging structure and method, and electronic device

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