CN112992777A - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

Info

Publication number
CN112992777A
CN112992777A CN201911296041.9A CN201911296041A CN112992777A CN 112992777 A CN112992777 A CN 112992777A CN 201911296041 A CN201911296041 A CN 201911296041A CN 112992777 A CN112992777 A CN 112992777A
Authority
CN
China
Prior art keywords
layer
forming
fin
region
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201911296041.9A
Other languages
Chinese (zh)
Inventor
王楠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201911296041.9A priority Critical patent/CN112992777A/en
Publication of CN112992777A publication Critical patent/CN112992777A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor device and a method of forming the same, comprising: providing a substrate, wherein the substrate comprises a first region, a second region and a third region which are adjacently arranged, the third region is positioned between the first region and the second region, and a first fin portion positioned in the first region and a second fin portion positioned in the second region are arranged in the substrate; forming an etching stop layer on the substrate, the side wall and the top of the first fin part and the side wall and the top of the second fin part; forming a dielectric layer on the etching stop layer; etching the dielectric layer in the first area to expose the etching stop layer and form a first groove; etching the dielectric layer in the second area to expose the etching stop layer and form a second groove; etching a first fin part at the bottom of the first groove, and forming a first sub-groove in the first fin part; and etching the second fin part at the bottom of the second groove to form a second sub-groove in the second fin part. The invention changes the limitation of the process, improves the flexibility of the graphic design and improves the performance of the semiconductor device.

Description

Semiconductor device and method of forming the same
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a forming method thereof.
Background
With the continuous development of semiconductor technology, memories have developed the trend of high integration, high speed and low power consumption.
The memories are functionally divided into Random Access Memories (RAMs) and Read Only Memories (ROMs). When the random access memory is in operation, data can be read from any one of the designated addresses at any time, and data can also be written into any one of the designated memory cells at any time. The random access memory is convenient to read and write and flexible to use.
Random access memories can be divided into Static Random Access Memories (SRAMs) and Dynamic Random Access Memories (DRAMs). The static random access memory uses a trigger with positive feedback to store data, and mainly relies on continuous power supply to maintain the integrity of the data. Static random access memories do not require refreshing during use. Static random access memories have been widely used in computer caching and frequent data processing.
However, the electrical performance of the prior art sram is poor.
Disclosure of Invention
The invention provides a semiconductor device and a forming method thereof, thereby improving the use performance of the semiconductor device.
In order to solve the above problems, the present invention provides a method for forming a semiconductor device, comprising the steps of: providing a substrate, wherein the substrate comprises a first region, a second region and a third region which are adjacently arranged, the third region is positioned between the first region and the second region, and a first fin portion positioned in the first region and a second fin portion positioned in the second region are arranged in the substrate; forming an etching stop layer on the substrate, the side wall and the top of the first fin part and the side wall and the top of the second fin part; forming a dielectric layer on the etching stop layer; etching the dielectric layer in the first area to expose the etching stop layer and form a first groove; etching the dielectric layer of the second area to expose the etching stop layer and form a second groove; etching the first fin part at the bottom of the first groove, and forming a first sub-groove in the first fin part; and etching the second fin part at the bottom of the second groove, and forming a second sub-groove in the second fin part.
Optionally, the method further includes: and forming a first doping layer in the first sub-groove, and forming a second doping layer in the second sub-groove.
Optionally, after the first doping layer and the second doping layer are formed, the method further includes: forming a first conductive structure in the first groove; and forming a second conductive structure in the second groove.
Optionally, the material of the etching stop layer is silicon nitride, silicon carbide, silicon oxycarbide, or silicon oxynitride.
Optionally, the process of forming the etching stop layer is a chemical vapor deposition process, an atomic layer deposition process, or a physical vapor deposition process.
Optionally, a process of forming the first doping layer and the second doping layer is an epitaxy process or an ion implantation process.
Optionally, an isolation layer is further disposed in the substrate, and the isolation layer covers a portion of sidewalls of the first fin portion and the second fin portion.
Optionally, the substrate further includes a first gate structure, the first gate structure is located in the first region, the second region and the third region of the substrate, the first gate structure spans the first fin portion and the second fin portion and covers part of sidewalls and top surfaces of the first fin portion and the second fin portion, the first doping layer is located in the first fin portion on two sides of the first gate structure, and the second doping layer is located in the second fin portion on two sides of the first gate structure.
Optionally, the method further includes: and forming a third conductive structure on the top surface of the first gate structure.
Accordingly, the present invention also provides a semiconductor device comprising: the substrate comprises a first area, a second area and a third area which are adjacently arranged, and the third area is positioned between the first area and the second area; a first fin portion located within the substrate of the first region; a second fin portion located within the substrate of the second region; the etching stop layer is positioned on the substrate, the side wall and the top of the first fin part and the side wall and the top of the second fin part; the dielectric layer is positioned on the etching stop layer; the first groove is positioned in the medium layer of the first area and exposes out of the etching stop layer; a first sub-trench located in the first fin portion and at a bottom of the first trench; the second groove is positioned in the medium layer of the second area and exposes out of the etching stop layer; a second sub-trench located within the second fin and at a bottom of the second trench.
Optionally, the method further includes: the first doping layer is located in the first sub-groove, and the second doping layer is located in the second sub-groove.
Optionally, the first doping layer is asymmetrically distributed with respect to a central axis of the first fin portion parallel to the substrate surface direction.
Optionally, the second doping layer is asymmetrically distributed with respect to a central axis of the second fin portion parallel to the substrate surface direction.
Compared with the prior art, the technical scheme of the invention has the following advantages:
after forming a dielectric layer on a substrate; etching the dielectric layer of the first area, and forming a first groove in the dielectric layer of the first area; etching the dielectric layer of the second area, and forming a second groove in the dielectric layer of the second area; continuously etching the first fin part at the bottom of the first groove along the first groove, and forming a first sub-groove in the first fin part; and continuously etching the second fin part at the bottom of the second groove along the second groove, and forming a second sub-groove in the second fin part. The method comprises the steps of directly forming a first groove and a second groove for filling a conductive structure in a dielectric layer, forming a first sub-groove at the bottom of the first groove, forming a second sub-groove at the bottom of the second groove, ensuring that when a first doping layer is formed in the first sub-groove and a second doping layer is formed in the second sub-groove in the following process, one side wall of the first doping layer is blocked by the dielectric layer and one side wall of the second doping layer is blocked by the dielectric layer when the first doping layer and the second doping layer are formed, so that the formed first doping layer is asymmetrically distributed about a central axis of the first fin part parallel to the surface of a substrate, and the second doping layer is asymmetrically distributed about a central axis of the second fin part parallel to the surface of the substrate, so that the position relationship between the fin part and the doping layers is changed, in the process of pattern design, when the position relation between the fin part and the doping layer is designed, the position of the fin part can be properly adjusted so as to improve the flexibility of pattern design, and the performance of a formed semiconductor device can be ensured at the same time, so that the forming method has wide applicability; in addition, the first doping layer is asymmetrically distributed about the central axis of the first fin portion, and the second doping layer is asymmetrically distributed about the central axis of the second fin portion, so that a conductive structure is formed on the first doping layer and the second doping layer, and the conductive structure is also asymmetrically distributed on two sides of the central axis of the fin portion, so that the volume of the conductive structure covering the fin portion is reduced, the process limitation is changed on the premise of ensuring the performance of the semiconductor device, and the quality and the reliability of the semiconductor device are improved.
Drawings
Fig. 1 to 2 are schematic structural views of an SRAM device;
fig. 3 to 14 are schematic structural views illustrating a semiconductor device forming process according to an embodiment of the present invention.
Detailed Description
The performance of the semiconductor devices formed at present is poor.
Fig. 1 to 2 are schematic structural views of an SRAM device.
Referring to fig. 1 and fig. 2, fig. 1 is a top view of a semiconductor device, fig. 2 is a schematic cross-sectional view along a cutting line a-a in fig. 1, a substrate 100, the substrate 100 including adjacent device regions I, the adjacent device regions I being connected in a mirror image along an axis S-S1, the surface of the substrate 100 of the device region I having fins 110 and an isolation layer 101, the isolation layer 101 covering a portion of sidewalls of the fins 110, and the fins 110 of the adjacent device regions I being adjacent to each other; a gate structure 120 spanning adjacent fins 110 of adjacent device regions I; a gate structure 111 spanning fin 110; the source-drain doping layers 130 are located in the fin portions 110 on two sides of the gate structure 120 of the device region I, and the source-drain doping layers 130 of the adjacent device region I are adjacent; the dielectric layer 140 is positioned on the surface of the substrate, and the dielectric layer 140 covers the top surfaces of the source-drain doping layer 130 of the device region I and the adjacent device region I, and the top and the side wall surfaces of the gate structure 120; the first conductive structure 150 crosses over the source-drain doping layer 130 to cover a part of the top and sidewall surfaces of the source-drain doping layer 130, and the third conductive structure 160 covers a part of the top surface of the gate structure 120.
N-n1 in FIG. 1 is the central axis of the fin parallel to the substrate surface.
The inventor analyzes and finds that the performance of the semiconductor device formed by the method is poor, particularly, on one hand, the residue of the pseudo gate structure is easily caused in a dotted line circle b in fig. 1, and when the metal gate structure is formed, the defects such as holes and the like are easily generated in the metal gate structure; meanwhile, referring to a dotted circle c in fig. 1, it can be seen that the distance between the first conductive structure 150 and the third conductive structure 160 is too small, and a short circuit is easily generated between the first conductive structure and the third conductive structure, thereby inhibiting the use of the semiconductor device; after the pseudo-gate structure is formed, doping layers are formed in the fin parts on two sides of the pseudo-gate structure, then a first conductive structure is formed on the doping layers, the doping layers are symmetrically distributed on two sides of the fin part about a central axis (n-n1) of the fin part, the position relation between the doping layers and the fin part cannot be adjusted, and on one hand, the size of a cutting mask is difficult to control and the pseudo-gate structure is difficult to remove when the pseudo-gate structure is cut between the adjacent fin parts due to the limitation of process conditions and the size of a semiconductor device; on the other hand, on the premise of ensuring the performance of the semiconductor device, the position relationship between the first conductive structure and the fin portion cannot be adjusted, so that the distance between the first conductive structure and the third conductive structure cannot be adjusted, and a short circuit phenomenon is easily caused.
The inventor researches and discovers that a mask layer is formed on the dielectric layer of the third area by forming the dielectric layer on the substrate; directly etching the dielectric layer in the first area by taking the mask layer as a mask, forming a first groove in the dielectric layer in the first area, continuously etching the first fin part along the first groove, and forming a first sub-groove in the first fin part; similarly, etching the dielectric layer of the second area, forming a second groove in the dielectric layer of the second area, continuously etching along the second groove, and forming a second sub-groove in the second fin portion; and then forming first doping layers in the first sub-trenches respectively, and forming second doping layers in the second sub-trenches, wherein the formed first doping layers are asymmetrically distributed about the central axis of the first fin part, and the similarly formed second doping layers are asymmetrically distributed about the central axis of the second fin part, so that the position relationship between the fin part and the doping layers is adjusted, and meanwhile, the position relationship between the conductive structure on the doping layers and the fin part is adjusted, thereby breaking through the limitation of a process window and improving the performance of the formed semiconductor device.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 14 are schematic structural views illustrating a semiconductor device forming process according to an embodiment of the present invention.
Referring to fig. 3 and 4, fig. 3 is a top view of a semiconductor device, fig. 4 is a schematic cross-sectional view along a cutting line a-a in fig. 3, and a substrate is provided, where the substrate includes a first region a, a third region C and a second region B, the third region C is located between the first region a and the second region B, and the third region C is adjacent to the first region a and the second region B.
In this embodiment, the substrate further includes a first device region and a second device region, the first device region and the second device region are adjacent to each other, the first device region and the second device region are distributed in a mirror image manner with a center line S-S1 of the third region C as an axis, the first region a is located in the first device region, and the second region B is located in the second device region.
The substrate is provided with a fin portion 210, and the substrate of the first region A is provided with a first fin portion 211; a second fin portion 212 is formed in the substrate of the second region B, and the first fin portion 211 is adjacent to the second fin portion 212.
Only adjacent first and second device regions in the semiconductor device are shown in fig. 3.
In this embodiment, the first device region and the second device region are used to form a static random access memory.
In an embodiment, the first device region and the second device region are used to form a PMOS transistor or an NMOS transistor.
The substrate further includes a first gate structure 220, the first gate structure 220 is located on the first region a, the second region B, and the third region C of the substrate, and the first gate structure 220 crosses over the first fin portion 211 and the second fin portion 212 and covers a portion of sidewalls and top surfaces of the first fin portion 211 and the second fin portion 212.
In this embodiment, the forming method of the first gate structure 220 includes: forming a first dummy gate structure crossing the first fin portion 211 and the second fin portion 212 on the semiconductor substrate 200; forming a first dielectric layer covering the semiconductor substrate 200, the top and the side wall of the first fin portion 211, the top and the side wall of the second fin portion 212 and the side wall of the first dummy gate structure; after a first dielectric layer is formed, removing the first pseudo gate structure, and forming a gate opening in the first dielectric layer; the first gate structure 220 is formed within the gate opening.
In this embodiment, the first gate structure 220 includes a gate dielectric layer and a gate layer on the gate dielectric layer. The gate dielectric layer is made of a high-K (K is greater than 3.9) dielectric material, and the gate layer is made of metal, such as tungsten.
The substrate is further provided with a second gate structure 221, and the second gate structure 221 is respectively located in the first region and the second region of the substrate.
In this embodiment, the first fin 211 and the second fin 212 serve as fins of a pass transistor and a pull-down transistor.
The base further includes a semiconductor substrate 200, and the first fin portion 211, the second fin portion 212, and the first gate structure 220 are located on the semiconductor substrate 200.
The material of the semiconductor substrate 200 includes semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, indium gallium arsenide, and the like, wherein the silicon material includes monocrystalline silicon, polycrystalline silicon, or amorphous silicon. The semiconductor substrate 200 can also be a semiconductor-on-insulator structure including an insulator and a semiconductor material layer on the insulator, wherein the semiconductor material layer includes semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, indium gallium arsenide, and the like.
In this embodiment, the material of the semiconductor substrate 200 is monocrystalline silicon.
In this embodiment, the first fin portion 211 and the second fin portion 212 are formed by patterning the semiconductor substrate 200.
In this embodiment, the material of the first fin portion 211 and the second fin portion 212 is monocrystalline silicon.
In other embodiments, the material of the first fin 211 and the second fin 212 is single crystal silicon germanium or other semiconductor materials.
In this embodiment, the method further includes: forming an isolation layer 201 on the semiconductor substrate 200, wherein the isolation layer 201 covers part of the sidewall surfaces of the first fin portion 211 and the second fin portion 212. The material of the isolation layer 201 includes silicon oxide.
Referring to fig. 5, an etch stop layer 300 is formed on the substrate, on sidewalls and a top of the first fin portion 211, and on sidewalls and a top of the second fin portion 212.
In this embodiment, the material of the etching stop layer 300 is silicon nitride; in other embodiments, the material of the etch stop layer 300 may also be silicon carbonitride, silicon boronitride, silicon oxycarbonitride, or silicon oxynitride.
In this embodiment, the etching stop layer 300 is formed to: protecting the substrate from damage during subsequent processing.
In this embodiment, the process of forming the etching stop layer 300 is a chemical vapor deposition process; in other implementations, the process of forming the etch stop layer 300 can also be a physical vapor deposition process or an atomic vapor deposition process.
Referring to fig. 6, a dielectric layer 400 is formed on the etch stop layer 300.
In this embodiment, the dielectric layer 400 is made of silicon oxide; in other embodiments, the material of the dielectric layer 400 may also be silicon carbide, silicon oxycarbide, silicon oxynitride, or the like.
In this embodiment, the process of forming the dielectric layer 400 is a chemical vapor deposition process; in other embodiments, the process for forming the dielectric layer 400 can also be a physical vapor deposition process.
In this embodiment, after the dielectric layer 400 is formed, the top surface of the dielectric layer 400 is also planarized.
Referring to fig. 7, a mask layer 500 is formed on the dielectric layer 400 of the third region C.
In this embodiment, the mask layer 500 is made of silicon nitride; in other embodiments, the material of the mask layer 500 may also be silicon carbonitride, silicon boronitride, silicon oxycarbonitride, or silicon oxynitride, or a photoresist layer.
In this embodiment, the method for forming the mask layer 500 includes: forming an initial mask layer (not shown) on the dielectric layer 400; forming a patterning layer (not shown) on the surface of the initial mask layer, wherein the patterning layer exposes a part of the surface of the initial mask layer; and etching the initial mask layer by taking the patterning layer as a mask to form the mask layer 500 on the dielectric layer 400.
Referring to fig. 8, with the mask layer 500 as a mask, etching the dielectric layer 400 in the first region a to expose the etch stop layer 300, and forming a first trench 410; and etching the dielectric layer 400 in the second region B by using the mask layer 500 as a mask to expose the etching stop layer 300, thereby forming a second trench 420.
In this embodiment, the dielectric layer 400 is etched, and the process for forming the first trench 410 and the second trench 420 is anisotropic dry etching, where the process parameters of the dry etching are: using gases containing fluorine (e.g. fluorine)Such as CH3F、CH2F2Or CHF3) Argon and oxygen, the etching power is 200W-400W, the pressure of the etching cavity is 30 mtorr-200 mtorr, and the etching temperature is 40 ℃ to 60 ℃.
In this embodiment, the first trench 410 is formed to provide a space for forming the first conductive structure.
In this embodiment, the second trench 420 is formed to provide a space for forming a second conductive structure.
Referring to fig. 9, continuing to etch the first fin portion 211 at the bottom of the first trench 410 by using the mask layer 500 as a mask, and forming a first sub-trench 411 in the first fin portion 211; and continuously using the mask layer 500 as a mask to etch the second fin portion 212 at the bottom of the second trench 420, and forming a second sub-trench 421 in the second fin portion 212.
In this embodiment, the first sub-trench 411 is formed to provide a space for forming the first doped layer.
In this embodiment, the second sub-trench 421 is formed to provide a space for forming a second doped layer.
In this embodiment, the process of etching the first fin portion 211 and the second fin portion structure 212 to form the first sub-trench 411 and the second sub-trench 421 is anisotropic dry etching. The parameters of the dry etching include: the adopted etching gas comprises HBr and Ar, wherein the flow rate of HBr is 10 sccm-1000 sccm, and the flow rate of Ar is 10 sccm-1000 sccm.
In this embodiment, first, the first trench 410 and the second trench 420 for filling a conductive structure are formed in the dielectric layer 400 in the first region a and the second region B; etching the first fin portion 211 at the bottom of the first trench 410, and forming the first sub-trench 411 for forming a doped layer in the first fin portion 211; etching the second fin portion 212 at the bottom of the second trench 420, forming the second sub-trench 421 for forming a doped layer in the second fin portion 212, and when forming doped layers in the first sub-trench 411 and the second sub-trench 421, because the dielectric layer 400 is arranged on one side of the first sub-trench 411 and the second sub-trench 421, one side of the doped layer is blocked by the dielectric layer 400 during the growth process of the doped layer, so that the formed doped layer is asymmetrically distributed about the central axis of the fin portion, and thus when a pattern structure is set, the positional relationship between the fin portion and the doped layer can be properly adjusted, so that the process becomes flexible, and the process limitation is broken through.
Referring to fig. 10 to 11, a first doping layer 412 is formed in the first sub-trench 411, and a second doping layer 422 is formed in the second sub-trench 421.
Fig. 10 is a schematic view based on fig. 3, and fig. 11 is a schematic cross-sectional view taken along the cutting line a-a in fig. 10.
In this embodiment, the first doping layers 412 are asymmetrically distributed with respect to a central axis (n-n) of the first fin 211 parallel to the substrate surface direction.
In this embodiment, the second doping layers 422 are asymmetrically distributed with respect to a central axis (m-m) of the second fin 212 parallel to the substrate surface direction.
In this embodiment, since the first doping layer 412 and the second doping layer 422 are asymmetrically arranged with respect to the central axis (n-n) of the first fin 211 and the central axis (m-m) of the second fin 212, respectively, the positional relationship between the first doping layer 412 and the second doping layer 422 and the first fin 211 and the second fin 212 is changed (relative to the existing fig. 1), so that when a pattern is designed, the position of the first fin or the second fin can be relatively adjusted, the distance between the adjacent first fin and the second fin can be appropriately increased, which can facilitate to improve the quality of the formed semiconductor device and break through the limitation of the process.
In this embodiment, referring to fig. 10, it can be seen that the position of the first fin portion 211 is relatively designed to the left (relative to the position of the fin portion 110 in fig. 1), the distance between the first fin portion 211 and the second fin portion 212 is increased, and since a series of steps, such as forming a pseudo-gate structure and performing pseudo-gate structure cutting between fins of adjacent pull-down transistors, is further included before the first gate structure 220 and the second gate structure 221 are formed, and the first fin portion 211 and the second fin portion 212 are used as fins of a pass transistor and a pull-down transistor, such that the positional relationship between the first fin portion 211 and the second fin portion 212 is appropriately adjusted to increase the distance between the adjacent first fin portion 211 and the second fin portion 212, that is, the distance between fins of adjacent pull-down transistors is increased, therefore, the process of cutting the pseudo-gate structure between the fin parts of the adjacent pull-down transistors becomes easy according to the process requirements, and meanwhile, when the pseudo-gate structure is removed to form the gate structure, the pseudo-gate structure is also easily removed, so that the residue of the pseudo-gate structure is reduced, the quality of the formed gate structure is improved, and the performance and the reliability of the semiconductor device are improved.
In this embodiment, a first doping layer 412 and a second doping layer 422 are respectively formed in the first sub-trench 411 and the second sub-trench 421 by epitaxial growth.
In other embodiments, the first doping layer 412 and the second doping layer 422 may be formed by ion doping.
The first doped layer 412 and the second doped layer 422 have source and drain ions.
When the type of the semiconductor device is N type, the conductivity type of the source and drain ions is N type, such as phosphorus ions; when the type of the semiconductor device is P type, the conductivity type of the source and drain ions is P type, such as boron ions.
Referring to fig. 12 to 13, a first conductive structure 413 is formed in the first trench 410, and a second conductive structure 423 is formed in the second trench 420.
Fig. 12 is a schematic view based on fig. 3, and fig. 13 is a schematic cross-sectional view taken along the cutting line a-a in fig. 12.
In this embodiment, the first conductive structure is taken as an example to explain: referring to fig. 1 and 12 in combination, since the first doping layer 412 is asymmetrically distributed on both sides of the central axis (n-n) of the first fin 211, the first conductive structure 413 is also asymmetrically distributed on both sides of the central axis of the first fin 211, and the volumes of the first conductive structure 413 distributed on both sides of the central axis of the first fin 211 are different, as can be seen from the dashed line frame indicated by the arrow in fig. 12, the volume of the first conductive structure 413 on the left side of the first fin 211 is reduced, so that the contact volume between the first conductive structure 413 and the first fin 211 is not as large, and the process limitation is changed on the premise of ensuring the performance of the semiconductor device.
In this embodiment, the second conductive structures 423 are also asymmetrically distributed on two sides of the central axis of the second fin portion 212.
In other embodiments, the second fin 212 is positioned relatively to the right (relative to the fin 110 in fig. 1).
In this embodiment, the first conductive structure 413 is used to connect the first doping layer 412 with a first metal interconnection layer formed later.
In this embodiment, the method for forming the first conductive structure 413 includes: forming a first conductive material layer in the first trench 410 and on the dielectric layer 400; the first conductive material layer is etched back until the surface of the dielectric layer 400 is exposed, and a first conductive structure 413 is formed in the first trench 410.
In this embodiment, the second conductive structure 423 is used for connecting the second doped layer 422 with a first metal interconnection layer formed later.
In this embodiment, the method for forming the second conductive structure 423 includes: forming a second conductive material layer in the second trench 420 and on the dielectric layer 400; and etching back the second conductive material layer until the surface of the dielectric layer 400 is exposed, and forming a second conductive structure 423 in the second trench 420.
Referring to fig. 14, a third conductive structure 222 is formed on a top surface of the first gate structure 220.
In this embodiment, the third conductive structure 221 is used to connect the first gate structure 220 with a first metal interconnection layer formed later.
In this embodiment, referring to fig. 1 and fig. 14 in combination, in this embodiment, comparing the position relationship between the first conductive structure and the third conductive structure in fig. 14 and in a c-dashed circle of fig. 1, it can be seen that the first conductive structure 413 in fig. 14 is designed to be a little leftward with respect to the first conductive structure 150 in fig. 1, and thus the distance between the first conductive structure 413 and the third conductive structure 222 in fig. 14 is larger than the distance between the first conductive structure 150 and the third conductive structure 160 in fig. 1, so that the problem of short circuit between the first conductive structure and the third conductive structure is solved, the design of the pattern becomes more flexible, and the performance of the formed semiconductor device is improved.
Accordingly, the present invention also provides a semiconductor device comprising: the substrate comprises a first area A, a second area B and a third area C which are adjacently arranged, and the third area C is positioned between the first area A and the second area B; a first fin portion 211 located in the substrate of the first region a; a second fin portion 212 located within the substrate of the second region B; an etch stop layer 300 on the substrate, on sidewalls and a top of the first fin portion 211, and on sidewalls and a top of the second fin portion 212; a dielectric layer 400 on the etch stop layer 300; a mask layer 500 on the dielectric layer 400 in the third region; a first trench 410 located in the dielectric layer 400 of the first region a and exposing the etch stop layer 300; a first sub-trench 411 located within the first fin 211 and at a bottom of the first trench 410; a second trench 420 located in the dielectric layer 400 of the second region B and exposing the etch stop layer 300; a second sub-trench 421 located in the second fin 212 and at the bottom of the second trench 420.
In this embodiment, since the first trench 410 is first formed in the dielectric layer 400 in the first region a, the second trench 420 is formed in the dielectric layer 400 in the second region B, the first sub-trench 411 is formed in the first fin portion 211 at the bottom of the first trench 410, the second sub-trench 421 is formed in the second fin portion 212 at the bottom of the second trench 420, and then doped layers are respectively formed in the first sub-trench 411 and the second sub-trench 421 to serve as source and drain regions, since the dielectric layer 400 is provided on one side of the first sub-trench 411 and the second sub-trench 421, the doped layers formed in the first sub-trench 411 and the second sub-trench 421 are blocked by the dielectric layer 400, so that the doped layers are asymmetrically distributed about the central axis of the fin portion, the distribution relation enables the position relation between the doping layer and the fin portion to change, so that when a graph is designed, the position relation of each part can be properly adjusted, process design becomes flexible, process limitation is broken through, and quality and performance reliability of a formed semiconductor device are improved.
In this embodiment, the method further includes: a first doped layer 412 and a second doped layer 422, wherein the first doped layer 412 is located in the first sub-trench 411, and the second doped layer 422 is located in the second sub-trench 421.
In this embodiment, the first doping layers 412 are asymmetrically distributed about a central axis of the first fin 211 parallel to the substrate surface direction.
In this embodiment, the second doping layers 422 are asymmetrically distributed about a central axis of the second fin 212 parallel to the substrate surface direction.
In this embodiment, since the first doping layer 412 and the second doping layer 422 are asymmetrically distributed with respect to the central axes of the first fin portion 211 and the second fin portion 212 parallel to the substrate surface direction, respectively, so that the position relationship between the first doping layer 412 and the first fin portion 211 changes, and the positions of the second doping layer 422 and the second fin portion 211 change, when a pattern is designed, the positions of the fin portions can be appropriately adjusted, so as to provide a better process space for subsequent formation of a gate structure, and the like, thereby facilitating improvement of performance and reliability of a semiconductor device.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (13)

1. A method of forming a semiconductor device, comprising the steps of:
providing a substrate, wherein the substrate comprises a first region, a second region and a third region which are adjacently arranged, the third region is positioned between the first region and the second region, and a first fin portion positioned in the first region and a second fin portion positioned in the second region are arranged in the substrate;
forming an etching stop layer on the substrate, the side wall and the top of the first fin part and the side wall and the top of the second fin part;
forming a dielectric layer on the etching stop layer;
etching the dielectric layer in the first area to expose the etching stop layer and form a first groove;
etching the dielectric layer of the second area to expose the etching stop layer and form a second groove;
etching the first fin part at the bottom of the first groove, and forming a first sub-groove in the first fin part;
and etching the second fin part at the bottom of the second groove, and forming a second sub-groove in the second fin part.
2. The method of forming a semiconductor device according to claim 1, further comprising: and forming a first doping layer in the first sub-groove, and forming a second doping layer in the second sub-groove.
3. The method for forming a semiconductor device according to claim 2, wherein after the forming the first doped layer and the second doped layer, the method further comprises: forming a first conductive structure in the first groove; and forming a second conductive structure in the second groove.
4. The method for forming a semiconductor device according to claim 1, wherein a material of the etch stop layer is silicon nitride, silicon carbide, silicon oxycarbide, or silicon oxynitride.
5. The method for forming a semiconductor device according to claim 1, wherein a process of forming the etch stop layer is a chemical vapor deposition process, an atomic layer deposition process, or a physical vapor deposition process.
6. The method for forming a semiconductor device according to claim 2, wherein a process of forming the first doping layer and the second doping layer is an epitaxial process or an ion implantation process.
7. The method of forming a semiconductor device of claim 1, wherein the substrate further comprises an isolation layer therein, wherein the isolation layer covers a portion of sidewalls of the first fin and the second fin.
8. The method for forming the semiconductor device according to claim 2, wherein the substrate further comprises a first gate structure therein, the first gate structure is located on the first region, the second region and the third region of the substrate, the first gate structure crosses over the first fin and the second fin and covers a portion of sidewalls and a top surface of the first fin and the second fin, the first doping layer is located in the first fin on two sides of the first gate structure, and the second doping layer is located in the second fin on two sides of the first gate structure.
9. The method of forming a semiconductor device according to claim 8, further comprising: and forming a third conductive structure on the top surface of the first gate structure.
10. A semiconductor device formed by the method of any of claims 1 to 9, comprising:
the substrate comprises a first area, a second area and a third area which are adjacently arranged, and the third area is positioned between the first area and the second area;
a first fin portion located within the substrate of the first region;
a second fin portion located within the substrate of the second region;
the etching stop layer is positioned on the substrate, the side wall and the top of the first fin part and the side wall and the top of the second fin part;
the dielectric layer is positioned on the etching stop layer;
the first groove is positioned in the medium layer of the first area and exposes out of the etching stop layer;
a first sub-trench located in the first fin portion and at a bottom of the first trench;
the second groove is positioned in the medium layer of the second area and exposes out of the etching stop layer;
a second sub-trench located within the second fin and at a bottom of the second trench.
11. The semiconductor device of claim 10, further comprising: the first doping layer is located in the first sub-groove, and the second doping layer is located in the second sub-groove.
12. The semiconductor device of claim 11, wherein the first doped layer is asymmetrically distributed about a central axis of the first fin portion parallel to the substrate surface direction.
13. The semiconductor device of claim 11, wherein the second doped layer is asymmetrically distributed with respect to a central axis of the second fin portion parallel to the substrate surface direction.
CN201911296041.9A 2019-12-16 2019-12-16 Semiconductor device and method of forming the same Pending CN112992777A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201911296041.9A CN112992777A (en) 2019-12-16 2019-12-16 Semiconductor device and method of forming the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201911296041.9A CN112992777A (en) 2019-12-16 2019-12-16 Semiconductor device and method of forming the same

Publications (1)

Publication Number Publication Date
CN112992777A true CN112992777A (en) 2021-06-18

Family

ID=76343474

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911296041.9A Pending CN112992777A (en) 2019-12-16 2019-12-16 Semiconductor device and method of forming the same

Country Status (1)

Country Link
CN (1) CN112992777A (en)

Similar Documents

Publication Publication Date Title
US6362073B2 (en) Method for forming semiconductor device having low parasite capacitance using air gap and self-aligned contact plug
CN108573927B (en) Semiconductor structure and forming method thereof
US11810860B2 (en) Semiconductor device with conductive structure and insulation layer of different width
US11515400B2 (en) Semiconductor structure and fabrication method thereof
CN110828460B (en) Semiconductor device and method of forming the same
US11950400B2 (en) Semiconductor device and forming method thereof
US11011527B2 (en) Semiconductor structure and static random access memory, and fabrication methods thereof
CN111354641A (en) Semiconductor device and method of forming the same
CN113497036A (en) Semiconductor structure and forming method thereof
WO2020244198A1 (en) Memory structure, and method for forming same
CN112992777A (en) Semiconductor device and method of forming the same
JP2008171863A (en) Method of forming trench gate
CN114792730A (en) Semiconductor structure and forming method thereof
CN113113486B (en) Semiconductor device and method of forming the same
CN110581133B (en) Semiconductor structure, forming method thereof and SRAM
CN110875183B (en) Semiconductor device and method of forming the same
US20230013653A1 (en) Memory device and method for forming same
CN110534432B (en) Semiconductor device and method of forming the same
KR20040059737A (en) Method for manufacturing memory device
CN108417537B (en) SRAM memory and forming method thereof
CN114093807A (en) Semiconductor device and method of forming the same
CN110875184A (en) Semiconductor device and method of forming the same
KR100362195B1 (en) A method for fabricating SRAM
CN111384172A (en) Semiconductor device and method of forming the same
CN115498038A (en) Semiconductor structure and forming method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination