CN108417537B

CN108417537B - SRAM memory and forming method thereof

Info

Publication number: CN108417537B
Application number: CN201710074019.4A
Authority: CN
Inventors: 甘正浩; 冯军宏
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2017-02-10
Filing date: 2017-02-10
Publication date: 2021-09-07
Anticipated expiration: 2037-02-10
Also published as: CN108417537A

Abstract

An SRAM memory and a forming method thereof are provided, wherein the method comprises the following steps: providing a substrate; a method of forming a pass transistor, the method of forming the pass transistor comprising: forming a transmission gate structure on the substrate, wherein a channel region is arranged in the substrate at the bottom of the transmission gate structure, and the transmission gate structure is provided with a first side and a second side which are opposite; forming a first epitaxial layer in the substrate on the first side of the transmission gate structure, wherein the first epitaxial layer generates stress on the channel region, and the minimum distance from the edge of the first epitaxial layer to the edge of the transmission gate structure is a first distance; and forming a second epitaxial layer in the substrate at the second side of the transmission gate structure, wherein the second epitaxial layer generates stress on the channel region, the materials of the second epitaxial layer and the first epitaxial layer are the same, the minimum distance from the edge of the second epitaxial layer to the edge of the transmission gate structure is a second distance, and the second distance is greater than the first distance. The method can improve the electrical performance of the SRAM memory.

Description

SRAM memory and forming method thereof

Technical Field

The invention relates to the field of semiconductor manufacturing, in particular to an SRAM memory and a forming method thereof.

Background

With the continuous development of semiconductor technology, memories have developed the trend of high integration, high speed and low power consumption.

The memories are functionally divided into Random Access Memories (RAMs) and Read Only Memories (ROMs). When the random access memory is in operation, data can be read from any one of the designated addresses at any time, and data can also be written into any one of the designated memory cells at any time. The random access memory is convenient to read and write and flexible to use.

Random access memories can be divided into Static Random Access Memories (SRAMs) and Dynamic Random Access Memories (DRAMs). The static random access memory uses a trigger with positive feedback to store data, and mainly relies on continuous power supply to maintain the integrity of the data. Static random access memories do not require refreshing during use. Static random access memories have been widely used in computer caching and frequent data processing.

However, the performance of the static random access memory in the prior art is poor.

Disclosure of Invention

The invention provides an SRAM memory and a forming method thereof, which are used for improving the electrical performance of the SRAM memory.

In order to solve the above problems, the present invention provides a method for forming an SRAM memory, comprising: providing a substrate; a method of forming a pass transistor, the method of forming the pass transistor comprising: forming a transmission gate structure on the substrate, wherein a channel region is arranged in the substrate at the bottom of the transmission gate structure, and the transmission gate structure is provided with a first side and a second side which are opposite; forming a first epitaxial layer in the substrate on the first side of the transmission gate structure, wherein the first epitaxial layer generates stress on the channel region, and the minimum distance from the edge of the first epitaxial layer to the edge of the transmission gate structure is a first distance; and forming a second epitaxial layer in the substrate at the second side of the transmission gate structure, wherein the second epitaxial layer generates stress on the channel region, the materials of the second epitaxial layer and the first epitaxial layer are the same, the minimum distance from the edge of the second epitaxial layer to the edge of the transmission gate structure is a second distance, and the second distance is greater than the first distance.

Optionally, when the type of the transmission transistor is N-type, the first epitaxial layer and the second epitaxial layer generate tensile stress on the channel region.

Optionally, the first epitaxial layer and the second epitaxial layer are made of phosphorus-doped silicon or carbon silicon.

Optionally, when the type of the transmission transistor is P-type, the first epitaxial layer and the second epitaxial layer generate compressive stress on the channel region.

Optionally, the material of the first epitaxial layer and the second epitaxial layer includes silicon germanium.

Optionally, the difference between the second distance and the first distance is 1 nm to 3 nm.

Optionally, the method for forming the first epitaxial layer includes: forming a first groove in the substrate on the first side of the transmission grid structure; epitaxially growing a first epitaxial material layer in the first groove by adopting a first epitaxial growth process to form a first epitaxial layer; the method of forming the second epitaxial layer includes: forming a second groove in the substrate on the second side of the transmission grid structure; and epitaxially growing a second epitaxial material layer in the second groove by adopting a second epitaxial growth process to form a second epitaxial layer.

Optionally, after the first groove and the second groove are formed, performing the first epitaxial growth process and the second epitaxial growth process; the first epitaxial growth process and the second epitaxial growth process adopt the same process.

Optionally, the method for forming the pass transistor further includes: while epitaxially growing the first epitaxial material layer, in-situ doping source drain ions in the first epitaxial material layer, and forming a first source drain doping region in the substrate on the first side of the transmission gate structure; doping source-drain ions in the second epitaxial material layer in situ while epitaxially growing the second epitaxial material layer, and forming a second source-drain doped region in the substrate on the second side of the transmission gate structure; the first epitaxial layer is located in the first source-drain doped region, and the second epitaxial layer is located in the second source-drain doped region.

Optionally, the method for forming the pass transistor further includes: and injecting source and drain ions into the first epitaxial layer and the substrate on the first side of the transmission grid structure and the second epitaxial layer and the substrate on the second side of the transmission grid structure, forming a first source and drain doped region in the substrate on the first side of the transmission grid structure, and forming a second source and drain doped region in the substrate on the second side of the transmission grid structure.

Optionally, the SRAM memory further includes: a latch comprising a pull-up transistor and a pull-down transistor; the pull-up transistor and the pull-down transistor store data into the latch through the transmission transistor in a data writing state, and the pull-up transistor and the pull-down transistor output the data stored in the latch through the transmission transistor in a data reading state; the second source-drain doped region is connected with the latch.

Optionally, when the SRAM memory is in a read data state, the first transmission source/drain region is a source region of the transmission transistor, and the second transmission source/drain region is a drain region of the transmission transistor; when the SRAM is in a data writing state, the first transmission source-drain region is a drain region of the transmission transistor, and the second transmission source-drain region is a source region of the transmission transistor.

The present invention also provides an SRAM memory comprising: a substrate; a pass transistor, the pass transistor comprising: the transmission gate structure is positioned on the substrate, a channel region is arranged in the substrate at the bottom of the transmission gate structure, and the transmission gate structure is provided with a first side and a second side which are opposite; the first epitaxial layer is positioned in the substrate on the first side of the transmission gate structure and generates stress on the channel region, and the minimum distance from the edge of the first epitaxial layer to the edge of the transmission gate structure is a first distance; the second epitaxial layer is located in the substrate on the second side of the transmission grid structure, the second epitaxial layer generates stress on the channel region, the materials of the second epitaxial layer and the first epitaxial layer are the same, the minimum distance from the edge of the second epitaxial layer to the edge of the transmission grid structure is the second distance, and the second distance is larger than the first distance.

Optionally, the first epitaxial layer and the second epitaxial layer generate compressive stress on the channel region.

Optionally, the pass transistor further comprises: the first source-drain doped region is positioned in the substrate at the first side of the transmission grid structure; a second source-drain doped region located in the substrate at the second side of the transmission gate structure; the first epitaxial layer is located in the first source-drain doped region, and the second epitaxial layer is located in the second source-drain doped region.

Optionally, the method further includes: a latch comprising a pull-up transistor and a pull-down transistor; the pull-up transistor and the pull-down transistor store data into the latch through the transmission gate structure in a data writing state, and output the data stored in the latch through the transmission gate structure in a data reading state; the second source drain doped region is connected with the latch; when the SRAM is in a data reading state, the first transmission source-drain region is a source region of the transmission transistor, and the second transmission source-drain region is a drain region of the transmission transistor; when the SRAM is in a data writing state, the first transmission source-drain region is a drain region of the transmission transistor, and the second transmission source-drain region is a source region of the transmission transistor.

Compared with the prior art, the technical scheme of the invention has the following advantages:

according to the forming method of the SRAM, the first epitaxial layer is formed in the substrate on the first side of the transmission grid structure, the second epitaxial layer is formed in the substrate on the second side of the transmission grid structure, stress is generated on a channel by the first epitaxial layer and the second epitaxial layer, and the materials of the second epitaxial layer and the first epitaxial layer are the same. The stress of the first epitaxial layer and the second epitaxial layer on the channel region can change the electron mobility and the hole mobility of the channel region, so that the current of the channel region is influenced. Because the minimum distance from the edge of the second epitaxial layer to the edge of the transmission gate structure is greater than the minimum distance from the edge of the first epitaxial layer to the edge of the transmission gate structure, the stress of the second epitaxial layer on the channel region is less than the stress of the first epitaxial layer on the channel region. And then the current flowing from the first epitaxial layer to the second epitaxial layer is different from the current flowing from the second epitaxial layer to the first epitaxial layer. By setting the connection relationship between the first epitaxial layer and the second epitaxial layer and the latch in the SRAM memory, the on-state current of the transmission transistor when the SRAM memory is in a read data state can be smaller than the on-state current of the transmission transistor when the SRAM memory is in a write data state. When the SRAM memory is in a data reading state, the on-state current of the transmission transistor is small, so that the current difference between the transmission transistor and the pull-down transistor in the SRAM memory is large, and the data reading speed is improved; when the SRAM is in a data writing state, the on-state current of the transmission transistor is larger, so that the current difference between the transmission transistor and the pull-up transistor in the SRAM is larger, and the data writing speed is improved. Namely, the read-write speed of the SRAM memory can be improved at the same time. Thereby resulting in improved electrical performance of the SRAM memory.

In the SRAM memory provided by the technical scheme of the invention, the substrate on the first side of the transmission gate structure is provided with the first epitaxial layer, the substrate on the second side of the transmission gate structure is provided with the second epitaxial layer, the first epitaxial layer and the second epitaxial layer generate stress on a channel, and the second epitaxial layer and the first epitaxial layer are made of the same material. The stress of the first epitaxial layer and the second epitaxial layer on the channel region can change the electron mobility and the hole mobility of the channel region, so that the current of the channel region is influenced. Because the minimum distance from the edge of the second epitaxial layer to the edge of the transmission gate structure is greater than the minimum distance from the edge of the first epitaxial layer to the edge of the transmission gate structure, the stress of the second epitaxial layer on the channel region is less than the stress of the first epitaxial layer on the channel region. And then the current flowing from the first epitaxial layer to the second epitaxial layer is different from the current flowing from the second epitaxial layer to the first epitaxial layer. By setting the connection relationship between the first epitaxial layer and the second epitaxial layer and the latch in the SRAM memory, the on-state current of the transmission transistor when the SRAM memory is in a read data state can be smaller than the on-state current of the transmission transistor when the SRAM memory is in a write data state. When the SRAM memory is in a data reading state, the on-state current of the transmission transistor is small, so that the current difference between the transmission transistor and the pull-down transistor in the SRAM memory is large, and the data reading speed is improved; when the SRAM is in a data writing state, the on-state current of the transmission transistor is larger, so that the current difference between the transmission transistor and the pull-up transistor in the SRAM is larger, and the data writing speed is improved. Namely, the read-write speed of the SRAM memory can be improved at the same time. Thereby resulting in improved electrical performance of the SRAM memory.

Drawings

FIG. 1 is a circuit diagram of an SRAM memory cell;

fig. 2 to 11 are schematic structural diagrams illustrating a process of forming an SRAM memory according to an embodiment of the present invention.

Detailed Description

As mentioned in the background, SRAM memories formed in the prior art have poor electrical performance.

FIG. 1 is a circuit diagram of an SRAM memory cell including a pass transistor, a pull-up transistor, and a pull-down transistor, the pass transistor including: a first pass transistor PG1 and a second pass transistor PG2, the pull-up transistors including a first pull-up transistor PU1 and a second pull-up transistor PU2, the pull-down transistors including a first pull-down transistor PD1 and a second pull-down transistor PD2, the pull-up and pull-down transistors forming a latch. The connection relationship of the pass transistor, the pull-up transistor and the pull-down transistor is shown in fig. 1.

When reading data "0", the current in PD1 needs to be larger than that in PG1, otherwise data "0" cannot be read correctly; when writing data "0", the current in PG1 needs to be larger than that in PU1, otherwise data "0" cannot be correctly written; when reading data "1", the current in PD2 needs to be larger than that in PG2, otherwise data "1" cannot be read correctly; when writing data "1", the current in PG2 needs to be larger than that in PU2, otherwise data "1" cannot be written correctly.

The first transfer transistor PG1 includes a first transfer gate structure, and a first transfer source-drain region and a second transfer source-drain region located at both sides of the first transfer gate structure, and the second transfer transistor PG2 includes a second transfer gate structure, and a third transfer source-drain region and a fourth transfer source-drain region located at both sides of the second transfer gate structure. When the data is read, the first transmission source-drain region is a drain region of the first transmission transistor, and the third transmission source-drain region is a drain region of the second transmission transistor; and in the data writing state, the second transmission source-drain region is a drain region of the first transmission transistor, and the fourth transmission source-drain region is a drain region of the second transmission transistor.

Research finds that when the first transmission transistor is turned on, whether the first transmission source drain region or the second transmission source drain region is used as the drain region of the first transmission transistor, the resistances of the drain regions of the first transmission transistor are equal, and when the first transmission source drain region is the drain region, the current in the first transmission transistor is equal to the current in the first transmission transistor when the second transmission source drain region is used as the drain region of the first transmission transistor; when the second transfer transistor is turned on, no matter whether the third transfer source-drain region or the fourth transfer source-drain region is used as the drain region of the second transfer transistor, the resistances of the drain regions of the second transfer transistor are equal, and when the third transfer source-drain region is used as the drain region of the second transfer transistor, the current in the second transfer transistor is equal to the current in the second transfer transistor when the fourth transfer source-drain region is used as the drain region of the second transfer transistor.

For the reasons mentioned above, this leads to: when reading data "0", if the difference between the current in PD1 and the current in PG1 increases, it will result in that when writing data "0", the difference between the current in PG1 and the current in PU1 decreases, and vice versa. When reading data "1", the difference between the current in PD2 and the current in PG2 increases, which results in the difference between the current in PG2 and the current in PU2 decreasing when writing data "1", and vice versa. Resulting in the rate of reading data and the rate of writing data not being increased simultaneously.

On the basis, the invention provides a forming method of an SRAM memory, which comprises the following steps: providing a substrate; a method of forming a pass transistor, the method of forming the pass transistor comprising: forming a transmission gate structure on the substrate, wherein a channel region is arranged in the substrate at the bottom of the transmission gate structure, and the transmission gate structure is provided with a first side and a second side which are opposite; forming a first epitaxial layer in the substrate on the first side of the transmission gate structure, wherein the first epitaxial layer generates stress on the channel region, and the minimum distance from the edge of the first epitaxial layer to the edge of the transmission gate structure is a first distance; and forming a second epitaxial layer in the substrate at the second side of the transmission gate structure, wherein the second epitaxial layer generates stress on the channel region, the materials of the second epitaxial layer and the first epitaxial layer are the same, the minimum distance from the edge of the second epitaxial layer to the edge of the transmission gate structure is a second distance, and the second distance is greater than the first distance.

In the method, a first epitaxial layer is formed in the substrate on the first side of the transmission gate structure, a second epitaxial layer is formed in the substrate on the second side of the transmission gate structure, the first epitaxial layer and the second epitaxial layer generate stress on a channel, and the second epitaxial layer and the first epitaxial layer are made of the same material. The stress of the first epitaxial layer and the second epitaxial layer on the channel region can change the electron mobility and the hole mobility of the channel region, so that the current of the channel region is influenced. Because the minimum distance from the edge of the second epitaxial layer to the edge of the transmission gate structure is greater than the minimum distance from the edge of the first epitaxial layer to the edge of the transmission gate structure, the stress of the second epitaxial layer on the channel region is less than the stress of the first epitaxial layer on the channel region. And then the current flowing from the first epitaxial layer to the second epitaxial layer is different from the current flowing from the second epitaxial layer to the first epitaxial layer. By setting the connection relationship between the first epitaxial layer and the second epitaxial layer and the latch in the SRAM memory, the on-state current of the transmission transistor when the SRAM memory is in a read data state can be smaller than the on-state current of the transmission transistor when the SRAM memory is in a write data state. When the SRAM memory is in a data reading state, the on-state current of the transmission transistor is small, so that the current difference between the transmission transistor and the pull-down transistor in the SRAM memory is large, and the data reading speed is improved; when the SRAM is in a data writing state, the on-state current of the transmission transistor is larger, so that the current difference between the transmission transistor and the pull-up transistor in the SRAM is larger, and the data writing speed is improved. Namely, the read-write speed of the SRAM memory can be improved at the same time. Thereby resulting in improved electrical performance of the SRAM memory.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Referring to fig. 2, a substrate is provided.

In this embodiment, the base includes a semiconductor substrate 100 and a fin portion on the semiconductor substrate 100. In other embodiments, the base is a planar semiconductor substrate.

The semiconductor substrate 100 may be single crystal silicon, polycrystalline silicon, or amorphous silicon; the semiconductor substrate 100 may also be a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, or the like; in this embodiment, the material of the semiconductor substrate 100 is silicon.

The SRAM memory comprises a plurality of memory units, and each memory unit comprises a first area I and a second area II.

The positional relationship with respect to the first zone I and the second zone ii is distinguished according to a specific circuit design.

The fins include a first fin 121 located in the first region I and a second fin 122 located in the second region ii. The fin portion is formed by patterning the semiconductor substrate 100; or the following steps: a fin material layer (not shown) is formed on the surface of the semiconductor substrate 100, and then patterned, thereby forming a first fin 121 and a second fin 122 on the surface of the semiconductor substrate 100.

The surface of the semiconductor substrate 100 further has an isolation structure 110, the surface of the isolation structure 110 is lower than the top surfaces of the first fin 121 and the second fin 122, and the isolation structure 110 is used for electrically isolating the first fin 121 and electrically isolating the second fin 122.

The material of the isolation structure 110 includes silicon oxide.

Next, a transfer transistor is formed.

The pass transistor of each memory cell includes: a first pass transistor (corresponding to PG1 in fig. 1) located in the first region I and a second pass transistor (corresponding to PG2 in fig. 1) located in the second region ii. Both read and write data operations of the SRAM memory are performed through the first pass transistor and the second pass transistor.

The first transmission transistor and the second transmission transistor are of the same type, namely the first transmission transistor and the second transmission transistor are both of an N type or both of a P type. In this embodiment, the types of the first transfer transistor and the second transfer transistor are both N-type as an example.

In this embodiment, a fin field effect transistor is taken as an example for the first transfer transistor and the second transfer transistor. In other embodiments, the first and second pass transistors are planar MOS transistors.

The method of forming the transfer transistor is described in detail below.

Referring to fig. 3 and 4 together, the first region I in fig. 4 is a schematic cross-sectional view taken along the extending direction of the first fin in fig. 3 (axis a-a 1), and the second region ii in fig. 4 is a schematic cross-sectional view taken along the extending direction of the second fin in fig. 3 (axis a 2-A3), so as to form a transfer gate structure on the substrate.

The transfer gate structure of each memory cell includes a first transfer gate structure 130 located in the first region I and a second transfer gate structure 133 located in the second region ii.

Specifically, a first transmission gate structure 130 is formed on the substrate of the first region I; a second transfer gate structure 133 is formed on the substrate of the second region ii.

In this embodiment, the transmission gate structure crosses over the fins, specifically, the first transmission gate structure 130 crosses over the first fin 121, covers a part of the top surface and a part of the sidewall surface of the first fin 121; the second transfer gate structure 133 crosses the second fin 122, covering a portion of the top surface and a portion of the sidewall surface of the second fin 122.

The first transfer gate structure 130 includes a first transfer gate dielectric layer 131 crossing the first fin 121 and a first transfer gate 132 on the first transfer gate dielectric layer 131; the second transfer gate structure 133 includes a second transfer gate dielectric layer 134 crossing the second fin 122 and a second transfer gate 135 on the second transfer gate dielectric layer 134.

The first transfer gate dielectric layer 131 is located on the surface of the partial isolation structure 110 in the first region I, and covers a part of the top surface and a part of the sidewall surface of the first fin 121; the second transfer gate dielectric layer 134 is located on a portion of the surface of the isolation structure 110 in the second region ii, and covers a portion of the top surface and a portion of the sidewall surface of the second fin 122.

The first transfer gate dielectric layer 131 and the second transfer gate dielectric layer 134 are made of silicon oxide; the material of the first transfer gate 132 and the second transfer gate 135 is polysilicon.

Specifically, the method for forming the first transfer gate structure 130 and the second transfer gate structure 133 includes: forming a gate dielectric material layer (not shown) and a gate electrode material layer (not shown) on the gate dielectric material layer on the surface of the substrate; the gate dielectric material layer and the gate electrode material layer are patterned to form a first transfer gate structure 130 and a second transfer gate structure 133.

In this embodiment, the gate dielectric material layer is also located on the isolation structure 110.

The first transfer gate dielectric layer 131 and the second transfer gate dielectric layer 134 correspond to the gate dielectric material layer. The first transfer gate 132 and the second transfer gate 135 correspond to the gate electrode material layer.

The substrate at the bottom of the transmission gate structure is provided with a channel region. The channel region comprises a first channel region positioned in a first region I and a second channel region positioned in a second region II.

The first transfer gate structure 130 has a first channel region in the substrate at the bottom thereof, and the second transfer gate structure 133 has a second channel region in the substrate at the bottom thereof.

The transfer gate structure has opposing first and second sides. The first and second

transfer gate structures

130 and 133 each have opposite first and second sides.

Then, forming a first epitaxial layer in the substrate on the first side of the transmission gate structure, wherein the first epitaxial layer generates stress on the channel region, and the minimum distance from the edge of the first epitaxial layer to the edge of the transmission gate structure is a first distance; and forming a second epitaxial layer in the substrate at the second side of the transmission gate structure, wherein the second epitaxial layer generates stress on the channel region, the materials of the second epitaxial layer and the first epitaxial layer are the same, the minimum distance from the edge of the second epitaxial layer to the edge of the transmission gate structure is a second distance, and the second distance is greater than the first distance.

The first epitaxial layer of each memory cell comprises a first sub-epitaxial layer positioned in a first area I and a third sub-epitaxial layer positioned in a second area II; the second epitaxial layer of each memory cell comprises a second sub-epitaxial layer positioned in the first area I and a fourth sub-epitaxial layer positioned in the second area II.

Forming a second epitaxial layer after forming the first epitaxial layer; alternatively, after the second epitaxial layer is formed, the first epitaxial layer is formed. In this embodiment, an example in which a second epitaxial layer is formed after a first epitaxial layer is formed will be described.

The method for forming the first epitaxial layer comprises the following steps: forming a first groove in the substrate on the first side of the transmission grid structure; and epitaxially growing a first epitaxial material layer in the first groove by adopting a first epitaxial growth process to form a first epitaxial layer.

The method of forming the second epitaxial layer includes: forming a second groove in the substrate on the second side of the transmission grid structure; and epitaxially growing a second epitaxial material layer in the second groove by adopting a second epitaxial growth process to form a second epitaxial layer.

In this embodiment, before the first epitaxial layer and the second epitaxial layer are formed, a blocking material layer is formed on the substrate and on the surface of the transfer gate structure.

Referring to fig. 5, a barrier material layer 141 is formed on the substrate and on the surface of the transfer gate structure.

Specifically, a barrier material layer 141 is formed on the first region i substrate and the surface of the first transfer gate structure 130, and on the second region ii substrate and the surface of the second transfer gate structure 133.

The material of the barrier material layer 141 includes silicon nitride.

The process of forming the barrier material layer 141 is a deposition process, such as a plasma chemical vapor deposition process or an atomic layer deposition process.

The barrier material layer 141 functions to include: the barrier material layer 141 is used for forming a part of the subsequent sidewall; the barrier material layer 141 is used to protect the surface of the substrate and the surface of the transfer gate structure during the subsequent first and second epitaxial growth processes.

Referring to fig. 6, a first recess is formed in the substrate at the first side of the transfer gate structure.

The first grooves include a first sub-groove 151 located in the first zone i and a third sub-groove 153 located in the second zone ii.

A first sub-recess 151 and a third sub-recess 153 are formed, the first sub-recess 151 is located in the substrate on the first side of the first transfer gate structure 130, specifically, the first sub-recess 151 is located in the first fin 121 on the first side of the first transfer gate structure 130, the third sub-recess 153 is located in the substrate on the first side of the second transfer gate structure 133, specifically, the third sub-recess 153 is located in the second fin 122 on the first side of the second transfer gate structure 133.

Specifically, a first photoresist layer (not shown) is formed on the barrier material layer 141, the first photoresist layer has a first opening therein, the first opening includes a first sub-opening located in the first photoresist layer of the first region i and a third sub-opening located in the first photoresist layer of the second region ii, the first sub-opening is used for defining the position of the first sub-groove 151, and the third sub-opening is used for defining the position of the third sub-groove 153; etching the etching blocking material layer 141 and the substrate on the first side of the transmission gate structure by using the first photoresist layer as a mask, specifically, etching the first fin portion 121 and the blocking material layer 141 on the first side of the first transmission gate structure 130, and the second fin portion 122 and the blocking material layer 141 on the first side of the second transmission gate structure 133 by using the first photoresist layer as a mask to form the first sub-groove 151 and the third sub-groove 153; and removing the first photoresist layer after etching the barrier material layer 141, the first fin portion 121 and the second fin portion 122 by using the first photoresist layer as a mask.

In this embodiment, the first sub-groove 151 and the third sub-groove 153 are formed at the same time, so that process efficiency is simplified.

The first recess also extends through the barrier material layer 141. Specifically, the first sub-groove 151 penetrates through the barrier material layer 141 of the first region i, and the third sub-groove 153 penetrates through the barrier material layer 141 of the second region ii.

In this embodiment, the process of etching the substrate and the etching blocking material layer 141 on the first side of the transmission gate structure by using the first photoresist layer as a mask is a first etching process.

The parameters of the first etching process comprise: the gas used is CF₄And CHF₃，CF₄The flow rate of (1) is 15sccm to 25sccm, CHF₃The flow rate of the gas source is 5-20 sccm, the source radio frequency power is 200-500W, the bias voltage is 100-300V, and the chamber pressure is 1-100 mtorr.

It should be noted that, the first etching process etches the barrier material layer 141 on the first side of the transfer gate structure and the base longitudinally along a direction perpendicular to the surface of the semiconductor substrate 100 to form the first groove, and also etches the barrier material layer 141 on the first side of the transfer gate structure along a direction perpendicular to the sidewall of the transfer gate structure.

And then, forming a second groove in the substrate at the second side of the transmission gate structure.

The second groove comprises a second sub-groove located in the first area I and a fourth sub-groove located in the second area II.

Referring to fig. 7, a second photoresist layer 160 is formed in the first groove and on the barrier material layer 141, the second photoresist layer 160 has a second opening therein, the second opening includes a second sub-opening 162 in the second photoresist layer 160 in the first region i and a fourth sub-opening 164 in the second photoresist layer 160 in the second region ii, the second sub-opening 162 is used for defining the position of the second sub-groove, and the fourth sub-opening 164 is used for defining the position of the fourth sub-groove.

The second opening is located at a second side of the transmission gate structure. Specifically, the second sub-opening 162 is located at the second side of the first transfer gate structure 130, and the fourth sub-opening 164 is located at the second side of the second transfer gate structure 133.

Referring to fig. 8, the blocking material layer 141 and the substrate on the second side of the transmission gate structure are etched by using the second photoresist layer 160 as a mask, specifically, the first fin 121 and the blocking material layer 141 on the second side of the first transmission gate structure 130, and the second fin 122 and the blocking material layer 141 on the second side of the second transmission gate structure 133 are etched by using the second photoresist layer 160 as a mask to form a second sub-groove 152 and a fourth sub-groove 154, the second sub-groove 152 is located in the substrate on the second side of the first transmission gate structure 130, and the fourth sub-groove 154 is located in the substrate on the second side of the second transmission gate structure 133.

Specifically, the second sub-recess 152 is located in the first fin 121 on the second side of the first transmission gate structure 130, and the fourth sub-recess 154 is located in the second fin 122 on the second side of the second transmission gate structure 133.

In this embodiment, the second sub-groove 152 and the fourth sub-groove 154 are formed simultaneously, so that process efficiency is simplified.

The second recess also extends through the barrier material layer 141. Specifically, the second sub-groove 152 penetrates through the barrier material layer 141 of the first region i, and the fourth sub-groove 154 penetrates through the barrier material layer 141 of the second region ii.

In this embodiment, the second photoresist layer 160 is used as a mask to etch the etching barrier material layer 141 and the substrate on the second side of the transmission gate structure.

The parameters of the second etching process comprise: the gas used is CF₄And CHF₃，CF₄The flow rate of (1) is 15sccm to 25sccm, CHF₃The flow rate of the gas source is 15-125 sccm, the source radio frequency power is 200-500W, the bias voltage is 100-300V, and the pressure of the chamber is 1-100 mtorr.

It should be noted that, the second etching process etches the barrier material layer 141 on the second side of the transfer gate structure along a direction perpendicular to the sidewall of the transfer gate structure while etching the barrier material layer 141 and the base longitudinally along a direction perpendicular to the surface of the semiconductor substrate 100 to form the second recess.

The etching gases adopted by the first etching process and the second etching process both comprise CF₄And CHF₃When, CF₄Flow rate ofAnd CHF₃The larger the ratio of the flow rates of (a) is, the more advantageous the etching of the barrier material layer 141 in a direction perpendicular to the sidewalls of the transfer gate structure is. The second etching process etches the blocking material layer 141 in a direction perpendicular to the sidewalls of the transfer gate structure to a lesser extent than the first etching process etches the blocking material layer 141 in a direction perpendicular to the sidewalls of the transfer gate structure.

The second etching process etches the blocking material layer 141 in a direction perpendicular to the sidewalls of the transfer gate structure to a lesser extent than the first etching process etches the blocking material layer 141 in a direction perpendicular to the sidewalls of the transfer gate structure. Therefore, the thickness of the etching barrier material layer 141 on the second sidewall of the transmission gate structure after the second etching process is greater than the thickness of the etching barrier material layer 141 on the first sidewall of the transmission gate structure after the first etching process. The thickness of the etching barrier material layer 141 on the second side wall of the transmission gate structure after the second etching process is used for defining the minimum distance from the edge of the second groove to the edge of the transmission gate structure; the thickness of the etching stop material layer 141 on the first sidewall of the transfer gate structure after the first etching process is used to define the minimum distance from the edge of the first groove to the edge of the transfer gate structure. Therefore, the minimum distance from the edge of the second groove to the edge of the transmission gate structure is larger than the minimum distance from the edge of the first groove to the edge of the transmission gate structure.

Specifically, the minimum distance from the edge of the second sub-groove 152 to the edge of the first transfer gate structure 130 is greater than the minimum distance from the edge of the first sub-groove 151 to the edge of the first transfer gate structure 130; a minimum distance from an edge of the fourth sub-groove 154 to an edge of the second transfer gate structure 133 is greater than a minimum distance from an edge of the third sub-groove 153 to an edge of the second transfer gate structure 133.

Referring to fig. 9, the second photoresist layer 160 (refer to fig. 8) is removed.

Next, referring to fig. 10, epitaxially growing a first epitaxial material layer in the first groove by using a first epitaxial growth process to form a first epitaxial layer; and epitaxially growing a second epitaxial material layer in the second groove by adopting a second epitaxial growth process to form a second epitaxial layer.

In this embodiment, after the first and second grooves are formed, the first and second epitaxial growth processes are performed, and the first and second epitaxial growth processes use the same process, so that the processes for forming the first and second epitaxial layers are simplified.

In this embodiment, the first epitaxial growth process and the second epitaxial growth process are performed with the barrier material layer 141 as a protection layer.

The first epitaxial layer of each memory cell comprises a first sub-epitaxial layer 171 positioned in the first area I and a third sub-epitaxial layer 173 positioned in the second area II; the second epitaxial layer of each memory cell includes a second sub-epitaxial layer 172 located in the first region i and a fourth sub-epitaxial layer 174 located in the second region ii.

The first sub-epitaxial layer 171 is located in the substrate at the first side of the first transmission gate structure 130, and specifically, the first sub-epitaxial layer 171 is located in the first fin portion 121 at the first side of the first transmission gate structure 130; the second sub-epitaxial layer 172 is located in the substrate at the second side of the first transmission gate structure 130, and specifically, the second sub-epitaxial layer 172 is located in the first fin portion 121 at the second side of the first transmission gate structure 130.

The third sub-epitaxial layer 173 is located in the substrate at the first side of the second transfer gate structure 133, specifically, the third sub-epitaxial layer 173 is located in the second fin portion 122 at the first side of the second transfer gate structure 133; the fourth sub-epitaxial layer 174 is located in the substrate at the second side of the second transfer gate structure 133, and specifically, the fourth sub-epitaxial layer 174 is located in the second fin portion 122 at the second side of the second transfer gate structure 133.

When the type of the transmission transistor is N type, the first epitaxial layer and the second epitaxial layer generate tensile stress on a channel region. Specifically, when the type of the pass transistor is N type, the first sub-epitaxial layer 171 and the second sub-epitaxial layer 172 generate tensile stress on the first channel region, and the third sub-epitaxial layer 173 and the fourth sub-epitaxial layer 174 generate tensile stress on the second channel region.

When the type of the transmission transistor is P type, the first epitaxial layer and the second epitaxial layer generate compressive stress on the channel region. Specifically, when the type of the pass transistor is a P-type, the first sub-epitaxial layer 171 and the second sub-epitaxial layer 172 generate compressive stress on the first channel region, and the third sub-epitaxial layer 173 and the fourth sub-epitaxial layer 174 generate compressive stress on the second channel region.

And when the type of the transmission transistor is N type, the first epitaxial layer and the second epitaxial layer are made of phosphorus-doped silicon or carbon silicon.

When the materials of the first epitaxial layer and the second epitaxial layer are phosphorus-doped silicon, the concentration of phosphorus in the phosphorus-doped silicon is 1E13atom/cm³～1E16atom/cm³. When the materials of the first epitaxial layer and the second epitaxial layer are carbon silicon, the concentration of carbon element in the carbon silicon is 1E13atom/cm³～1E16atom/cm³. The significance of selecting this range is: if the concentration of the phosphorus element in the phosphorus-doped silicon is too high or the concentration of the carbon element in the carbon silicon is too high, the process waste is caused, and the process difficulty is increased; if the concentration of phosphorus in the phosphorus-doped silicon is too low, or the concentration of carbon in carbon silicon is too low, the stress of the first epitaxial layer and the second epitaxial layer on the channel region is smaller, the stress difference of the first epitaxial layer and the second epitaxial layer on the channel region is smaller, and the degree of improving the data reading capability and the data writing capability of the SRAM device is smaller.

When the materials of the first epitaxial layer and the second epitaxial layer are germanium-silicon, the concentration of germanium element in the germanium-silicon is 1E13atom/cm³～1E16atom/cm³. The significance of selecting this range is: if the concentration of the germanium element in the germanium-silicon is too high, the process is wasted, and the difficulty of the process is increased; if the concentration of the germanium element in the silicon germanium is too small, the stress of the first epitaxial layer and the stress of the second epitaxial layer to the channel region are smaller, the stress difference of the first epitaxial layer and the second epitaxial layer to the channel region is smaller, and the degree of improving the data reading capability and the data writing capability of the SRAM device is smaller.

The minimum distance from the edge of the first sub-epitaxial layer 171 to the edge of the first transfer gate structure 130 is a first sub-distance L1. The minimum distance from the edge of the second sub-epitaxial layer 172 to the edge of the first transmission gate structure 130 is a second sub-distance L2.

The minimum distance from the edge of the third sub-epitaxial layer 173 to the edge of the second transfer gate structure 133 is a third sub-distance L3. The minimum distance from the edge of the fourth sub-epitaxial layer 174 to the edge of the second transfer gate structure 133 is a fourth sub-distance L4.

Since the minimum distance from the edge of the second sub-groove 152 to the edge of the first transfer gate structure 130 is greater than the minimum distance from the edge of the first sub-groove 151 to the edge of the first transfer gate structure 130, the second sub-distance L2 is greater than the first sub-distance L1. Since the minimum distance from the edge of the fourth sub-groove 154 to the edge of the second transfer gate structure 133 is greater than the minimum distance from the edge of the third sub-groove 153 to the edge of the second transfer gate structure 133, the fourth sub-distance L4 is greater than the third sub-distance L3.

The difference between the second distance and the first distance is 1-3 nanometers. Specifically, the difference between the second sub-distance L2 and the first sub-distance L1 is 1 nm to 3 nm, and the difference between the fourth sub-distance L4 and the third sub-distance L3 is 1 nm to 3 nm.

If the difference between the second distance and the first distance is greater than 3 nanometers, the distance from the edge of the second epitaxial layer to the edge of the gate structure is too large, the feature size of the transmission gate structure is increased, and the integration level of the SRAM is reduced; if the difference between the second distance and the first distance is smaller than 1 nanometer, the stress difference between the first epitaxial layer and the second epitaxial layer to the channel region is smaller, and the degree of improvement on the data reading capability and the data writing capability of the SRAM device is smaller.

In an embodiment, the second distance is between 4.5nm and 6.5 nm, such as 5.5nm, in particular the second sub-distance L2 and the fourth sub-distance L4 are between 4.5nm and 6.5 nm, the first distance is between 1.5nm and 4.5nm, such as 2.5nm, in particular the third sub-distance L3 and the first sub-distance L1 are between 1.5nm and 4.5 nm.

Referring to fig. 11, after the first epitaxial layer and the second epitaxial layer are formed, the barrier material layer 141 is removed (refer to fig. 10).

And then, injecting source and drain ions into the first epitaxial layer and the substrate on the first side of the transmission grid structure and the second epitaxial layer and the substrate on the second side of the transmission grid structure, forming a first source and drain doped region in the substrate on the first side of the transmission grid structure, and forming a second source and drain doped region in the substrate on the second side of the transmission grid structure.

The first source-drain doped region comprises a first sub-source drain doped region located in the first region I and a third sub-source drain doped region located in the second region II. The second source drain doping region comprises a second sub-source drain doping region located in the first region I and a fourth sub-source drain doping region located in the second region II.

Specifically, source-drain ions are implanted into the first sub-epitaxial layer 171 and the substrate on the first side of the first transmission gate structure 130, and the second sub-epitaxial layer 172 and the substrate on the second side of the first transmission gate structure 130, so as to form a first sub-source drain doped region in the substrate on the first side of the first transmission gate structure 130, and form a second sub-source drain doped region in the substrate on the second side of the first transmission gate structure 130; source and drain ions are implanted into the third sub-epitaxial layer 173 and the substrate on the first side of the second transfer gate structure 133 and the fourth sub-epitaxial layer 174 and the substrate on the second side of the second transfer gate structure 133, a third sub-source drain doped region is formed in the substrate on the first side of the second transfer gate structure 133, and a fourth sub-source drain doped region is formed in the substrate on the second side of the second transfer gate structure 133.

Specifically, the first sub-source drain doped region is located in the first fin portion 121 on the first side of the first transmission gate structure 130; the second sub-source drain doped region is located in the first fin portion 121 on the second side of the first transmission gate structure 130; the third sub-source drain doped region is located in the second fin portion 122 on the first side of the second transfer gate structure 133; the fourth sub-source drain doped region is located in the second fin 122 at the second side of the second transfer gate structure 133.

The first epitaxial layer is located in the first source-drain doped region, and the second epitaxial layer is located in the second source-drain doped region. Specifically, the first sub-epitaxial layer 171 is located in the first sub-source drain doped region, the second sub-epitaxial layer 172 is located in the second sub-source drain doped region, the third sub-epitaxial layer 173 is located in the third sub-source drain doped region, and the fourth sub-epitaxial layer 174 is located in the fourth sub-source drain doped region.

In other embodiments, source and drain ions are doped in situ in the first epitaxial material layer while the first epitaxial material layer is epitaxially grown, and a first source and drain doped region is formed in the substrate on the first side of the transmission gate structure; doping source-drain ions in the second epitaxial material layer in situ while epitaxially growing the second epitaxial material layer, and forming a second source-drain doped region in the substrate on the second side of the transmission gate structure; the first epitaxial layer is located in the first source-drain doped region, and the second epitaxial layer is located in the second source-drain doped region.

It should be noted that after the barrier material layer 141 is removed, and before the first source-drain doped region and the second source-drain doped region are formed, the method further includes: forming offset side walls on the side walls of the transmission grid electrode structures; forming lightly doped regions in the substrate on two sides of the transmission gate structure and the offset side wall respectively; after the lightly doped region is formed, forming a gap side wall on the side wall of the offset side wall; and respectively forming the first source drain doped region and the second source drain doped region in the substrate at two sides of the transmission gate structure, the offset side wall and the gap side wall.

The SRAM memory further includes a latch including pull-up transistors (corresponding to PU1 and PU2 in fig. 1) and pull-down transistors (corresponding to PD1 and PD2 in fig. 1), the pull-up and pull-down transistors storing data into the latch through the pass transistors in a write data state, and the pull-up and pull-down transistors outputting data stored in the latch through the pass transistors in a read data state.

The pull-down transistors are all of N type, and the pull-up transistors are all of P type.

When the types of the first transmission transistor and the second transmission transistor are both N type or P type.

The second source-drain doped region is connected with the latch. Specifically, the second sub-source drain doped region and the fourth sub-source drain doped region are respectively connected with the latch.

When the SRAM memory is in a read data state, the first transmission source-drain region is a source region of the transmission transistor, the second transmission source-drain region is a drain region of the transmission transistor, and specifically, the first sub-source drain doped region is a source region of the first transmission transistor 130, the second sub-source drain doped region is a drain region of the first transmission transistor 130, the third sub-source drain doped region is a source region of the second transmission transistor 133, and the fourth sub-source drain doped region 184 is a drain region of the second transmission transistor 133.

When the SRAM memory is in a data writing state, the first transmission source drain region is a drain region of the transmission transistor, the second transmission source drain region is a source region of the transmission transistor, and specifically, the first sub-source drain doped region is a drain region of the first transmission transistor 130, the second sub-source drain doped region is a source region of the first transmission transistor 130, the third sub-source drain doped region is a drain region of the second transmission transistor 133, and the fourth sub-source drain doped region 184 is a source region of the second transmission transistor 133.

In the operation process of the SRAM memory, the stress of the drain region of the transmission transistor on the channel region is greatly influenced relative to the stress of the source region of the transmission transistor on the channel region. The first epitaxial layer is located in the first source-drain doped region, and the second epitaxial layer is located in the second source-drain doped region. The first epitaxial layer and the second epitaxial layer generate stress on the channel, and the second epitaxial layer and the first epitaxial layer are made of the same material. The stress of the first epitaxial layer and the second epitaxial layer on the channel region can change the electron mobility and the hole mobility of the channel region, so that the current of the channel region is influenced. Specifically, the first epitaxial layer and the second epitaxial layer are used for improving the current of the channel region.

When the SRAM memory is in a data reading state, the first transmission source-drain region is a source region of the transmission transistor, and the second transmission source-drain region is a drain region of the transmission transistor. When the SRAM is in a data writing state, the first transmission source-drain region is a drain region of the transmission transistor, and the second transmission source-drain region is a source region of the transmission transistor. Because the minimum distance from the edge of the second epitaxial layer to the edge of the transmission gate structure is greater than the minimum distance from the edge of the first epitaxial layer to the edge of the transmission gate structure, the stress of the second epitaxial layer on the channel region is less than the stress of the first epitaxial layer on the channel region. Therefore, when the SRAM is in a read data state, the influence of the stress of the second epitaxial layer on the channel region on the current of the channel region is larger than the influence of the stress of the first epitaxial layer on the channel region on the current of the channel region; when the SRAM is in a data writing state, the influence of the stress of the first epitaxial layer on the channel region on the current of the channel region is larger than the influence of the stress of the second epitaxial layer on the channel region on the current of the channel region. Thus, the on-current of the pass transistor when the SRAM memory is in a read data state is made smaller than the on-current of the pass transistor when the SRAM memory is in a write data state.

When the SRAM memory is in a data reading state, the on-state current of the transmission transistor is small, so that the current difference between the transmission transistor and the pull-down transistor in the SRAM memory is large, and the data reading speed is improved; when the SRAM is in a data writing state, the on-state current of the transmission transistor is larger, so that the current difference between the transmission transistor and the pull-up transistor in the SRAM is larger, and the data writing speed is improved. Namely, the read-write speed of the SRAM memory can be improved at the same time. Thereby resulting in improved electrical performance of the SRAM memory.

Accordingly, the present embodiment further provides an SRAM memory, please refer to fig. 11, which includes: a substrate; a pass transistor, the pass transistor comprising: the transmission gate structure is positioned on the substrate, a channel region is arranged in the substrate at the bottom of the transmission gate structure, and the transmission gate structure is provided with a first side and a second side which are opposite; the first epitaxial layer is positioned in the substrate on the first side of the transmission gate structure and generates stress on the channel region, and the minimum distance from the edge of the first epitaxial layer to the edge of the transmission gate structure is a first distance; the second epitaxial layer is located in the substrate on the second side of the transmission grid structure, the second epitaxial layer generates stress on the channel region, the materials of the second epitaxial layer and the first epitaxial layer are the same, the minimum distance from the edge of the second epitaxial layer to the edge of the transmission grid structure is the second distance, and the second distance is larger than the first distance.

The base includes a semiconductor substrate 100 and a fin portion on the semiconductor substrate 100. In other embodiments, the base is a planar semiconductor substrate.

The fins include a first fin 121 located in the first region I and a second fin 122 located in the second region ii.

The pass transistor of each memory cell includes: a first transfer transistor located in the first region I and a second transfer transistor located in the second region ii. Both read and write data operations of the SRAM memory are performed through the first pass transistor and the second pass transistor.

The first transmission transistor and the second transmission transistor are of the same type, namely the first transmission transistor and the second transmission transistor are both of an N type or both of a P type.

The transfer gate structure includes a first transfer gate structure 130 located at the first region I and a second transfer gate structure 133 located at the second region.

transfer gate structures

130 and 133 each have opposite first and second sides.

The first epitaxial layer comprises a first sub-epitaxial layer 171 located in the first zone i and a third sub-epitaxial layer 173 located in the second zone ii. The second epitaxial layer includes a second sub-epitaxial layer 172 located in the first region i and a fourth sub-epitaxial layer 174 located in the second region ii.

The first transfer transistor includes: a first transmission gate structure 130 located on the first region I substrate, wherein a first channel region is provided in the substrate at the bottom of the first transmission gate structure 130; the first sub-epitaxial layer 171 is positioned in the substrate on the first side of the first transmission gate structure 130, the first sub-epitaxial layer 171 generates stress on the first channel region, and the minimum distance from the edge of the first sub-epitaxial layer 171 to the edge of the first transmission gate structure 130 is a first sub-distance L1; and the second sub-epitaxial layer 172 is positioned in the substrate at the second side of the first transmission gate structure 130, the second sub-epitaxial layer 172 generates stress on the second channel region, the materials of the second sub-epitaxial layer 172 and the first sub-epitaxial layer 171 are the same, the minimum distance from the edge of the second sub-epitaxial layer 172 to the edge of the first transmission gate structure 130 is a second sub-distance L2, and the second sub-distance L2 is greater than the first sub-distance L1.

The location, structure and material of the first transfer gate structure 130 are described with reference to the previous embodiments.

Specifically, the first sub-epitaxial layer 171 is located in the first fin 121 on the first side of the first transmission gate structure 130, and the second sub-epitaxial layer 172 is located in the first fin 121 on the second side of the first transmission gate structure 130.

The second pass transistor includes: a second transfer gate structure 133 on the second region ii substrate; a third sub-epitaxial layer 173 in the substrate on the first side of the second transfer gate structure 133, the third sub-epitaxial layer 173 generating stress on the second channel region, and a minimum distance from an edge of the third sub-epitaxial layer 173 to an edge of the second transfer gate structure 133 being a third sub-distance L3; and a fourth sub-epitaxial layer 174 in the substrate at the second side of the second transfer gate structure 133, the fourth sub-epitaxial layer 174 generating stress to the second channel region, the materials of the fourth sub-epitaxial layer 174 and the third sub-epitaxial layer 173 are the same, a minimum distance from an edge of the fourth sub-epitaxial layer 174 to an edge of the second transfer gate structure 133 is a fourth sub-distance L4, and the fourth sub-distance L4 is greater than the third sub-distance L3.

The location, structure and material of the second transfer gate structure 133 are all referred to the previous embodiments.

Specifically, the third sub-epitaxial layer 173 is located in the second fin portion 122 at the first side of the second transfer gate structure 133, and the fourth sub-epitaxial layer 174 is located in the second fin portion 122 at the second side of the second transfer gate structure 133.

When the type of the transmission transistor is N type, the first epitaxial layer and the second epitaxial layer generate tensile stress on a channel region.

Specifically, when the type of the pass transistor is N type, the first sub-epitaxial layer 171 and the second sub-epitaxial layer 172 generate tensile stress on the first channel region, and the third sub-epitaxial layer 173 and the fourth sub-epitaxial layer 174 generate tensile stress on the second channel region.

When the type of the transmission transistor is P type, the first epitaxial layer and the second epitaxial layer generate compressive stress on the channel region.

Specifically, when the type of the pass transistor is N-type, the first sub-epitaxial layer 171 and the second sub-epitaxial layer 172 generate compressive stress on the first channel region, and the third sub-epitaxial layer 173 and the fourth sub-epitaxial layer 174 generate compressive stress on the second channel region.

The concentration of the phosphorus element in the phosphorus-doped silicon is 1E13atom/cm³～1E16atom/cm³。

The concentration of carbon element in the carbon silicon is 1E13atom/cm³～1E16atom/cm³。

When the type of the transmission transistor is a P type, the material of the first epitaxial layer and the second epitaxial layer comprises silicon germanium.

The concentration of germanium element in the germanium-silicon is 1E13atom/cm³～1E16atom/cm³。

The pass transistor further includes: the first source-drain doped region is positioned in the substrate at the first side of the transmission grid structure; and the second source-drain doped region is positioned in the substrate at the second side of the transmission gate structure.

The first transfer transistor further includes: a first sub-source drain doped region in the first side substrate of the first transfer gate structure 130; and a second sub-source drain doped region in the second side substrate of the first transfer gate structure 130.

Specifically, the first sub-source drain doped region is located in the first fin portion 121 on the first side of the first transmission gate structure 130; the second sub-source drain doped region is located in the first fin 121 on the second side of the first transfer gate structure 130.

The second transfer gate structure further includes: a third sub-source drain doped region in the substrate on the first side of the second transfer gate structure 133; a fourth sub-source drain doped region in the substrate on a second side of the second transfer gate structure 133.

Specifically, the third sub-source drain doped region is located in the second fin portion 122 on the first side of the second transmission gate structure 133; the fourth sub-source drain doped region is located in the second fin 122 at the second side of the second transfer gate structure 133.

The first epitaxial layer is located in the first source-drain doped region, and the second epitaxial layer is located in the second source-drain doped region.

Specifically, the first sub-epitaxial layer 171 is located in the first sub-source drain doped region, and the second sub-epitaxial layer 172 is located in the second sub-source drain doped region; the third sub-epitaxial layer 173 is located in the third sub-source drain doped region and the fourth sub-epitaxial layer 174 is located in the fourth sub-source drain doped region.

The SRAM memory further comprises: a latch comprising a pull-up transistor and a pull-down transistor; and in the data reading state, the pull-up transistor and the pull-down transistor output the data stored in the latch through the transmission transistor.

The type of the transmission transistor is N type or P type.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method for forming an SRAM memory, comprising:

providing a substrate;

a method of forming a pass transistor, the method of forming the pass transistor comprising:

forming a transmission gate structure on the substrate, wherein a channel region is arranged in the substrate at the bottom of the transmission gate structure, and the transmission gate structure is provided with a first side and a second side which are opposite;

forming a first epitaxial layer in the substrate on the first side of the transmission gate structure, wherein the first epitaxial layer generates stress on the channel region, and the minimum distance from the edge of the first epitaxial layer to the edge of the transmission gate structure is a first distance;

forming a second epitaxial layer in the substrate on the second side of the transmission gate structure, wherein the second epitaxial layer generates stress on the channel region, the second epitaxial layer and the first epitaxial layer are made of the same material, the minimum distance from the edge of the second epitaxial layer to the edge of the transmission gate structure is a second distance, and the second distance is greater than the first distance;

forming a first source-drain doped region on the first epitaxial layer on the first side of the transmission gate structure, and forming a second source-drain doped region on the second epitaxial layer on the second side of the transmission gate structure;

the SRAM memory further comprises: a latch comprising a pull-up transistor and a pull-down transistor; the pull-up transistor and the pull-down transistor store data into the latch through the transmission transistor in a data writing state, and the pull-up transistor and the pull-down transistor output the data stored in the latch through the transmission transistor in a data reading state; the second source drain doped region is connected with the latch;

when the SRAM is in a data reading state, the first transmission source-drain region is a source region of the transmission transistor, and the second transmission source-drain region is a drain region of the transmission transistor; when the SRAM is in a data writing state, the first transmission source-drain region is a drain region of the transmission transistor, and the second transmission source-drain region is a source region of the transmission transistor.

2. The method of claim 1, wherein the first epitaxial layer and the second epitaxial layer generate a tensile stress on a channel region when the type of the pass transistor is N-type.

3. The method of claim 2, wherein the material of the first epitaxial layer and the second epitaxial layer is silicon doped with phosphorus or carbon silicon.

4. The method of claim 1, wherein the first epitaxial layer and the second epitaxial layer generate compressive stress on a channel region when the pass transistor is P-type.

5. The method of claim 4, wherein the material of the first epitaxial layer and the second epitaxial layer comprises silicon germanium.

6. The method of claim 1, wherein the difference between the second distance and the first distance is 1 nm to 3 nm.

7. The method of claim 1, wherein the method of forming the first epitaxial layer comprises: forming a first groove in the substrate on the first side of the transmission grid structure; epitaxially growing a first epitaxial material layer in the first groove by adopting a first epitaxial growth process to form a first epitaxial layer;

8. The method according to claim 7, wherein the first and second epitaxial growth processes are performed after the first and second recesses are formed; the first epitaxial growth process and the second epitaxial growth process adopt the same process.

9. The method of claim 7, wherein the method of forming the pass transistor further comprises: while epitaxially growing the first epitaxial material layer, in-situ doping source drain ions in the first epitaxial material layer, and forming a first source drain doping region in the substrate on the first side of the transmission gate structure; doping source-drain ions in the second epitaxial material layer in situ while epitaxially growing the second epitaxial material layer, and forming a second source-drain doped region in the substrate on the second side of the transmission gate structure; the first epitaxial layer is located in the first source-drain doped region, and the second epitaxial layer is located in the second source-drain doped region.

10. The method of claim 1, wherein the method of forming the pass transistor further comprises: and injecting source and drain ions into the first epitaxial layer and the substrate on the first side of the transmission grid structure and the second epitaxial layer and the substrate on the second side of the transmission grid structure, forming a first source and drain doped region in the substrate on the first side of the transmission grid structure, and forming a second source and drain doped region in the substrate on the second side of the transmission grid structure.

11. An SRAM memory, comprising:

a substrate;

a pass transistor, the pass transistor comprising:

the transmission gate structure is positioned on the substrate, a channel region is arranged in the substrate at the bottom of the transmission gate structure, and the transmission gate structure is provided with a first side and a second side which are opposite;

the first epitaxial layer is positioned in the substrate on the first side of the transmission gate structure and generates stress on the channel region, and the minimum distance from the edge of the first epitaxial layer to the edge of the transmission gate structure is a first distance; the first epitaxial layer forms a first source drain doped region;

the second epitaxial layer is positioned in the substrate on the second side of the transmission gate structure and generates stress on the channel region, the materials of the second epitaxial layer and the first epitaxial layer are the same, the minimum distance from the edge of the second epitaxial layer to the edge of the transmission gate structure is a second distance, and the second distance is larger than the first distance; forming a second source-drain doped region on the second epitaxial layer;

a latch comprising a pull-up transistor and a pull-down transistor; the pull-up transistor and the pull-down transistor store data into the latch through the transmission gate structure in a data writing state, and output the data stored in the latch through the transmission gate structure in a data reading state; the second source drain doped region is connected with the latch;

12. The SRAM memory of claim 11, wherein the first epitaxial layer and the second epitaxial layer create a tensile stress on a channel region when the pass transistor is of the N-type.

13. The SRAM memory of claim 12, wherein the material of the first epitaxial layer and the second epitaxial layer is phosphorus doped silicon or carbon silicon.

14. The SRAM memory of claim 11, wherein the first epitaxial layer and the second epitaxial layer create a compressive stress on a channel region when the pass transistor is P-type.

15. The SRAM memory of claim 14, wherein a material of the first epitaxial layer and the second epitaxial layer comprises silicon germanium.

16. The SRAM memory of claim 12, wherein a difference between the second distance and the first distance is between 1 nm and 3 nm.

17. The SRAM memory of claim 12, wherein the pass transistor further comprises: the first source-drain doped region is positioned in the substrate at the first side of the transmission grid structure; a second source-drain doped region located in the substrate at the second side of the transmission gate structure; the first epitaxial layer is located in the first source-drain doped region, and the second epitaxial layer is located in the second source-drain doped region.