CN112986689B - Detection circuit and method for chip configuration pins - Google Patents

Detection circuit and method for chip configuration pins Download PDF

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Publication number
CN112986689B
CN112986689B CN202110421285.6A CN202110421285A CN112986689B CN 112986689 B CN112986689 B CN 112986689B CN 202110421285 A CN202110421285 A CN 202110421285A CN 112986689 B CN112986689 B CN 112986689B
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configuration
voltage
pin
circuit
reference voltage
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CN112986689A (en
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梁源超
聂振超
徐永志
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Zhuhai Zhirong Technology Co.,Ltd.
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Zhuhai Smart Ware Technology Co ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/14—Measuring resistance by measuring current or voltage obtained from a reference source
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G01R27/2605—Measuring capacitance
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]

Abstract

The invention relates to a detection circuit, a method and a system of a chip configuration pin, wherein the detection circuit comprises a function gear configuration circuit, a configuration pin, a voltage comparison circuit, a detection control unit, a sampling time array unit and a configuration identification unit. Meanwhile, the realization difficulty of identifying various configuration gears by a single configuration pin can be reduced, the number of configurable function gears of the single pin is greatly expanded, the demand of chip pins is reduced, the packaging cost of the chip is reduced, and the size of the chip is reduced.

Description

Detection circuit and method for chip configuration pins
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a detection circuit and a detection method for chip configuration pins.
Background
In general, the same chip needs to be configured differently in different application scenarios or application schemes. A typical example is that a mobile power management chip needs to set different charging target voltages and electric quantity curves according to different battery types matched in a complete machine scheme; a quick charging protocol management chip of an adapter needs to broadcast different voltage and current gears according to the power of the whole adapter; a path management chip of a multi-port charger needs to be set into different working modes according to different interface types on a scheme.
Such diversified function customization for different application scenarios or application schemes is often implemented by burning codes in a memory bank inside a chip. However, the requirement of various code values causes great inconvenience to the production management and the sales management of the chip. Although a great deal of manpower and financial resources are spent on perfecting various management systems and management tools, the occurrence of mistakenly programming code values or mixing materials still happens occasionally, and other irreparable losses are caused.
Therefore, a circuit and a method for detecting a chip configuration pin are needed to facilitate chip management.
Disclosure of Invention
The invention aims to provide a detection circuit and a detection method for a chip configuration pin, which are convenient for chip management.
In order to achieve the purpose, the invention provides the following scheme:
a detection circuit for a chip configuration pin, comprising:
the function gear configuration circuit is connected with the voltage comparison circuit through a configuration pin;
the detection control unit is connected with the voltage comparison circuit and used for comparing the voltage of the configuration pin with the reference voltage according to the time array and identifying the resistance value and the capacitance value of the function gear configuration circuit;
the sampling time array unit is connected with the detection control unit and is used for setting a time array for sampling the voltage of the configuration pin;
and the configuration identification unit is connected with the detection control unit and is used for configuring the functional state of the chip according to the resistance value and the capacitance value.
A method for detecting a chip configuration pin comprises the following steps:
inputting constant current to a function gear configuration circuit and a configuration pin;
detecting the voltage of the configuration pin at each sampling time point according to the time array;
comparing the voltage of each sampling time point with a reference voltage to obtain a comparison result;
identifying a resistance value and a capacitance value of the function gear configuration circuit according to the comparison result;
and configuring the functional state of the chip according to the resistance value and the capacitance value.
A system for detecting a chip configuration pin, comprising:
the input module is used for inputting constant current to the functional gear configuration circuit and the configuration pins;
the detection module is used for detecting the voltage of the configuration pin at each sampling time point according to the time array;
the comparison module is used for comparing the voltage of each sampling time point with the reference voltage to obtain a comparison result;
the identification module is used for identifying the resistance value and the capacitance value of the function gear configuration circuit according to the comparison result;
and the configuration module is used for configuring the functional state of the chip according to the resistance value and the capacitance value.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention discloses a detection circuit and a detection method for chip configuration pins. Compared with a code burning mode of a memory body in the chip, the detection method is simpler, diversified function customization of the chip is easier and convenient to realize, and production cost and management cost are greatly reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic diagram of a detection circuit for a chip configuration pin according to embodiment 1 of the present invention;
fig. 2 is a schematic diagram of a detection circuit of a chip configuration pin having a single configuration resistor according to embodiment 1 of the present invention;
fig. 3 is a flowchart of a method for detecting a chip configuration pin according to embodiment 2 of the present invention;
fig. 4 is a timing chart of a control process of the detection control unit in embodiment 2 of the present invention;
FIG. 5 is a diagram of a detection circuit of a chip configuration pin having specific values according to embodiment 2 of the present invention;
FIG. 6 is a timing chart showing control of a detection circuit having specific values in embodiment 2 of the present invention;
fig. 7 is a block diagram of a system for detecting a chip configuration pin according to embodiment 3 of the present invention.
Description of the symbols:
the method comprises the steps of 1-function gear configuration circuit, 2-configuration pin, 3-voltage comparison circuit, 4-detection control unit, 5-sampling time array unit and 6-configuration identification unit.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a detection circuit and a detection method for a chip configuration pin, which are convenient for chip management and reduce the production cost and the management cost of a chip.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Example 1:
referring to fig. 1, the present invention provides a detection circuit for a chip configuration pin, including:
the function gear configuration circuit 1 is connected with the voltage comparison circuit 3 through a configuration pin 2;
the configuration pin 2 is a pin planned by the chip for configuring the functional state, and the connection mode of the configuration pin is detected in the chip power-on initialization process, so that the functional state of the chip is configured according to the agreed mapping relationship.
The detection control unit 4 is connected with the voltage comparison circuit 3 and used for comparing the voltage of the configuration pin with the reference voltage according to the time array and identifying the resistance value and the capacitance value of the function gear configuration circuit 1;
the sampling time array unit 5 is connected with the detection control unit 4 and is used for setting a time array for sampling the voltage of the configuration pin;
and the configuration identification unit 6 is connected with the detection control unit 4 and is used for configuring the functional state of the chip according to the resistance value and the capacitance value.
The detection circuit of the chip configuration pin solves the problems that in the prior art, diversified function customization of the chip can only be realized in a code burning mode of the internal memory of the chip, so that the chip is difficult to manage and the cost is high.
A chip manufacturer provides a universal chip, and a complete machine scheme designer can realize function customization of the chip by only connecting configuration pins of the chip according to a specific mode, such as direct grounding of the pins, direct power connection, connection with different resistors for grounding, connection with different resistors for power supply and the like. FIG. 2 shows a chip PIN detection circuit with a single configuration resistor, which includes a configuration resistor R, a configuration PIN PIN, a current source I, and a switch S0~SNReference voltage array VREF1~VREFNA voltage comparator CMP, a detection control unit and a configuration identification unit. When the chip is powered on, the voltage detection mode is adopted, the voltage of the configuration pin is sampled, and the sampled configuration pin is compared with the reference voltage, so that the customized function state of the chip is identified.
Although the detection circuit can realize the functional state configuration of the chip in a pin configuration mode, the chip production and sales management is facilitated, the configuration detection of a plurality of gears is easy to realize in a single resistor configuration mode, and the difficulty of the configuration detection of more than ten gears is greatly increased. And if more gear positions are to be configured, the number of configuration pins needs to be increased, which also results in increased package cost and increased chip size. In order to further solve the problems of how to reduce the implementation difficulty of identifying various configuration gears by a single configuration pin and reduce the chip volume and the packaging cost, the invention further designs a function gear configuration circuit 1 on the basis of the detection circuit shown in fig. 1, wherein the function gear configuration circuit 1 comprises a configuration capacitor C and a configuration resistor R;
the configuration capacitor C and the configuration resistor R are connected in parallel to form a parallel branch;
the first end of the parallel branch is connected with a voltage comparison circuit 3 through a configuration pin 2;
when the second end of the parallel branch is grounded, the first end of the current source I is connected with a power supply VCC; when the second end of the parallel branch is connected with the power supply, the first end of the current source I is grounded.
The configuration resistance R can have various values: r1~RN(ii) a The configuration capacitance C can have various values: c1~CM. The combination of configuration resistors and configuration capacitors with different values corresponds to various functional states to be configured. Therefore, the values of the N configuration resistors and the values of the M configuration capacitors share N × M gears, and N × M functional states can be configured, wherein N, M is a positive integer, N is greater than or equal to 2, and M is greater than or equal to 2.
As an alternative embodiment, as shown in fig. 1, the voltage comparison circuit 3 further includes: current source I and current source control switch S0Reference voltage array VREF1~VREFNArray control switch S1~SNAnd a voltage comparator CMP;
the first end of the current source I is connected with a power supply VCC or ground;
the second end of the current source I controls the switch S through the current source0Is connected with the configuration pin 2;
based on the connection relationship, the current source control switch S is controlled0When the power supply is turned off, the current source I is disconnected with the configuration pin 2; current source control switch S0When conducting, the current source I outputsA current is output to the configuration pin 2, wherein a part of the current IRAnother part of the current I flows through the configuration resistor RCThe configuration capacitor C is charged. Therefore, the current source I, the current I flowing through the configuration resistorRAnd a current I flowing through the configuration capacitor CCThe following equation relationship exists between:
Figure DEST_PATH_IMAGE002
。
current source control switch S0After the conduction, the total electric quantity output by the current source I is
Figure DEST_PATH_IMAGE004
. Wherein ICt represents the amount of charge to the configuration capacitor C,
Figure DEST_PATH_IMAGE006
，VPINvoltage represented as a configuration pin; i isRt is the amount of electricity flowing through the configuration resistor R, and
Figure DEST_PATH_IMAGE008
is a variation value with VPINAnd increases in size. Thus, the voltage V on the configuration pinPINThe following functional relationship exists with time t:
Figure DEST_PATH_IMAGE010
。
the positive input end of the voltage comparator CMP is connected with the configuration pin 2, and the negative input end of the voltage comparator CMP controls the switch S through the array1~SNAnd a reference voltage array VREF1~VREFNConnecting;
array of reference voltages VREF1~VREFNThe switch S being controlled by an array1~SNGating, for following the voltage V of the configuration pinPINA comparison is made to identify the range of values of the configuration resistance R. The value of each reference voltage is the IR drop voltage V generated by the total current of the current source I through various configuration resistorsRTo select. Wherein VREF1Set to the lowest reference voltage, lowAt the minimum configuration resistance R1Voltage V ofR1. Reference voltage sum VRAre both within the range of the power supplies VCC and GND, and are related in magnitude to each other as shown in table 1.
TABLE 1 definition of reference Voltage arrays
Figure DEST_PATH_IMAGE012
The output of the voltage comparator CMP is connected to the detection control unit 4.
Considering that the detection circuit has deviations in the arrangement resistance R, the current source I and the voltage comparator CMP, each reference voltage and two adjacent voltages V are used to prevent the comparison and judgment from being wrongRIn between, a certain fault tolerance distance needs to be reserved. E.g. VREFNAnd VRN，VREFNAnd VR（N-1）A certain phase difference distance remains.
The invention realizes the configuration of the functional state of the chip by detecting the pins of the chip, thereby facilitating the management of the chip; the configuration circuit of the functional gear comprises configuration capacitors and configuration resistors with different values, and the configuration capacitors and the configuration resistors are connected in parallel to the configuration pins, so that the configuration of multiple functional states of the chip can be realized. And during the power-on initialization process of the chip, outputting a constant current to the configuration pin. When the constant current passes through the parallel combination of different configuration resistors and configuration capacitors, different voltage-time characteristic curves can be generated on the configuration pins. And sampling and detecting the voltage on the configuration pin at a plurality of selected time points, comparing the sampled voltage with a specific reference voltage, and identifying the value ranges of the resistor and the capacitor connected on the configuration pin so as to extract the corresponding functional configuration gear. The detection method of two dimensions of voltage and time is introduced, and the configuration of chip functions is realized through the two-dimensional combination of resistors and capacitors with different values, the realization difficulty of identifying various configuration gears by a single configuration pin is reduced, the quantity of required chip pins is reduced, the packaging cost of the chip is reduced, the size of the chip is reduced, and the number of the configurable function gears of the single pin is greatly expanded.
Example 2:
referring to fig. 3, based on the chip configuration pin detection circuit shown in fig. 1, the present invention further provides a chip configuration pin detection method, including:
s1: inputting constant current to a function gear configuration circuit 1 and a configuration pin 2;
s2: detecting the voltage of the configuration pin 2 at each sampling time point according to the time array;
wherein the time array comprises a plurality of sampling time points T1~TM；T1~T(M-1)The time point is used for identifying the value range, T, of the configuration capacitor CMThe time points are used to identify the value range of the configuration resistance R.
The sampling time point is based on the current source I and the lowest reference voltage VREF1Maximum configuration resistance RNMinimum arrangement resistance R1And a configuration capacitance C;
the number of the sampling time points is determined according to the type of the value of the configuration capacitor in the function gear configuration circuit, and M sampling time points are determined according to the value types of M configuration capacitors, wherein M is a positive integer and is more than or equal to 2.
Defining a current source I to a capacitor CMAnd a maximum resistance RNCharging the parallel branch to VREF1Time of tM_MINDefining a current source I to a capacitor C(M-1)And a minimum resistance R1Charging the parallel branch to VREF1Time of t(M-1)_MAXThus sampling the time point T(M-1)Needs to satisfy t(M-1)_MAX<T(M-1)<tM_MINAnd a certain fault tolerance margin is reserved. About TMIs taken to ensure that the capacitance C is maximally configuredMAnd a maximum configuration resistance RNIn combination of (1) at TMAt the time point, the voltage of the configuration pin can be charged to the maximum reference voltage VREFNAs described above, the presence of the arrangement capacitor C does not affect the recognition of the arrangement resistor R.
S3: comparing the voltage of each sampling time point with a reference voltage to obtain a comparison result;
s4: identifying the resistance value and the capacitance value of the functional gear configuration circuit according to the comparison result, which specifically comprises the following steps:
sequentially sampling the first (M-1) sampling time points (T)1~T(M-1)) The voltages of the corresponding configuration pins are respectively compared with the lowest reference voltage to obtain a first comparison result;
identifying a capacitance value of the function gear configuration circuit according to the first comparison result;
the Mth sampling time point (T)M) Comparing the voltage of the configuration pin with a reference voltage to obtain a second comparison result, specifically comprising:
closing a first one of the array control switches;
taking the voltage of a configuration pin after the jth control switch in the array control switches is switched on as a voltage to be detected, wherein j is more than or equal to 2 and is a positive integer;
taking the jth reference voltage as a comparison voltage;
comparing the voltage to be detected with the comparison voltage;
if the voltage to be detected is smaller than the comparison voltage, the resistance value of the function gear configuration circuit is the value of the (j-1) th configuration resistance;
if the voltage to be detected is larger than the comparison voltage, making j = j +1, and judging whether j is equal to N, wherein N represents the number of the value types of the configuration resistor, N is larger than or equal to 2, and N is a positive integer;
if j is not equal to N, returning to the step of taking the voltage of the configuration pin after the jth control switch in the array control switches is conducted as the voltage to be detected, wherein j is not less than 2, and j is a positive integer; a step of using the jth reference voltage as a comparison voltage; otherwise, the resistance value of the output function gear configuration circuit is the value of the jth configuration resistor.
S5: and configuring the functional state of the chip according to the resistance value and the capacitance value.
As an optional implementation manner, sequentially comparing voltages of the configuration pins corresponding to the first (M-1) sampling time points with the lowest reference voltage, respectively, to obtain a first comparison result; identifying a capacitance value of the functional gear configuration circuit according to the first comparison result, specifically including:
taking the ith sampling time point as a comparison point, wherein i is more than or equal to 1, and i is a positive integer;
comparing the voltage of the configuration pin of the comparison point with the lowest reference voltage;
if the voltage of the configuration pin of the comparison point is greater than the lowest reference voltage, the capacitance value of the function gear configuration circuit is the value of the ith configuration capacitor;
if the voltage of the configuration pin of the comparison point is less than the lowest reference voltage, making i = i +1, and returning to the step of taking the ith sampling time point as the comparison point until i = M-2;
comparing the voltage of the configuration pin corresponding to the (M-1) th sampling time point with the lowest reference voltage;
if the voltage of the configuration pin corresponding to the (M-1) th sampling time point is greater than the lowest reference voltage, the capacitance value of the function gear configuration circuit is the value of the (M-1) th configuration capacitor;
and if the voltage of the configuration pin corresponding to the (M-1) th sampling time point is less than the lowest reference voltage, the capacitance value of the function gear configuration circuit is the value of the Mth configuration capacitor.
FIG. 4 is a timing chart showing the control process of the detection control unit at the time zero point T0On current source control switch S0And outputting the current source to the configuration pin 2, and starting the detection process of the configuration pin 2. At T1At the time point, the switch S is gated1Will T1Configuration pin voltage V of time pointPIN1Following the lowest reference voltage VREF1Comparing, if the comparison result is VPIN1Greater than VREF1Then identify the configured capacitance as the minimum capacitance value C1(ii) a Otherwise, at T2At the time point, the switch S is gated1Will configure the voltage V of the pinPIN2Following the lowest reference voltage VREF1Making a comparison if the comparison is positiveThe fruit is VPIN2Greater than VREF1Then, the identification configuration capacitance is C2. By analogy, in T(M-1)At the time point, the voltage V of the pin is to be configuredPIN（M-1）Following the lowest reference voltage VREF1Comparing, if the comparison result is VPIN（M-1）Greater than VREF1Then, the identification configuration capacitance is C(M-1)Otherwise, recognizing the configured capacitance as CM。
At TMAt the time point, the voltage V of the configuration pin 2PINHas approximated the IR drop voltage V generated by the current source I flowing entirely through the configuration resistor RR. At this time, the switch S is turned off first1On-off switch S2Will VPINWith reference voltage VREF2Comparing, if the comparison result is VPINLess than VREF2Then identify the configured resistance as the minimum value R1(ii) a Otherwise, switch S is turned on3Will VPINWith reference voltage VREF3Comparing, if the comparison result is VPINLess than VREF3Then identify the configured resistance as R2. By analogy, by turning on switch SNWill VPINWith reference voltage VREFNComparing, if the comparison result is VPINLess than VREFNThen identify the configured resistance as RN-1Otherwise, identifying the configured resistance as RN。
In order to make the above detection method of the present invention more clearly understood by those skilled in the art, the following description is given with specific data.
As shown in fig. 5, in the power supply range of 5V, 32 functional states are configured for one pin, and a combination of 8 configuration resistors and 4 configuration capacitors is selected to implement the configuration, and the current source I is selected to be 100 uA.
As shown in Table 2, the resistances of the 8 configurations range from small to large R1~R83k Ω, 6.8k Ω, 11k Ω, 15k Ω, 20k Ω, 27k Ω, 36.5k Ω, and floating (resistance ∞), respectively. 100uA current passes through a configuration resistor R1~R8The resulting IR drop voltages were 0.3V, 0.68V, 1.1V, 1.5V, 2.0V, 2.7V, 3.65V, and 5V, respectively. Reference voltage from low to high VREF1~VREF80.2V, 0.5V, 0.9V, 1.3V, 1.7V, 2.3V, 3.1V, and 4.2V, respectively.
As shown in Table 3, the 4 configuration capacitances are C from small to large1~C4There was no capacitance (0 uF), 0.1uF, 1uF, and 4.7uF, respectively. The configuration pin voltage V can be obtained through derivation and simulationPINCharging to VREF1Time of = 0.2V: the combination of the 0uF capacitor and the 3k Ω resistor requires 0s, the combination of the 0.1uF capacitor and the ∞ resistor requires 200us, the combination of the 0.1uF capacitor and the 3k Ω resistor requires 329us, the combination of the 1uF capacitor and the ∞ resistor requires 2ms, the combination of the 1uF capacitor and the 3k Ω resistor requires 3.29ms, and the combination of the 4.7uF capacitor and the ∞ resistor requires 9.4 ms. In addition, the pin voltage V is configuredPINCharging to VREF8A combination of capacitance and resistance of 4.7uF, 4.2V requires about 200 ms. Therefore, a sampling time point T for identifying the size of the configured capacitor is set1~T3Time T for identifying the magnitude of the configured resistor is 100us, 1ms and 6ms respectively4Is 250 ms.
TABLE 2 configuration resistance and reference Voltage values
Figure DEST_PATH_IMAGE014
Table 3 configuration capacitance values
Figure DEST_PATH_IMAGE016
As shown in fig. 6, at time zero 0, the current source control switch S0 is turned on, the current of the current source 100uA is output to the configuration pin, and the detection process of the configuration pin is started. At the moment of 100us, the gating array controls the switch S1, the voltage VPIN of the configuration pin is compared with the lowest reference voltage 0.2V, and if the comparison result shows that VPIN is greater than 0.2V, the configuration capacitor is identified to be free of capacitor, namely 0 uF; otherwise, at the moment of 1ms, the array control switch S1 is gated, the voltage VPIN of the configuration pin is compared with the lowest reference voltage 0.2V, and if the comparison result shows that VPIN is greater than 0.2V, the configuration capacitor is identified to be 0.1 uF; otherwise, at the moment of 6ms, the array control switch S1 is gated, the voltage VPIN of the configuration pin is compared with the lowest reference voltage 0.2V, and if the comparison result shows that VPIN is greater than 0.2V, the configuration capacitor is identified to be 1 uF; otherwise the identification configuration capacitance is 4.7 uF. Then at the time of 250ms, firstly closing the array control switch S1, turning on the array control switch S2, comparing VPIN with the reference voltage of 0.5V, and if the comparison result shows that VPIN is less than 0.5V, identifying that the configuration resistance is the minimum value of 3k omega; otherwise, turning on the array control switch S3, comparing VPIN with the reference voltage of 0.9V, and if the comparison result shows that VPIN is less than 0.9V, identifying that the configuration resistance is 6.8k omega; otherwise, turning on the array control switch S4, comparing VPIN with the reference voltage 1.3V, and if the comparison result shows that VPIN is less than 1.3V, identifying that the configuration resistance is 11k omega; otherwise, turning on the array control switch S5, comparing VPIN with the reference voltage 1.7V, and if the comparison result shows that VPIN is less than 1.7V, identifying that the configuration resistance is 15k omega; otherwise, turning on the array control switch S6, comparing VPIN with the reference voltage 2.3V, and if the comparison result shows that VPIN is less than 2.3V, identifying that the configuration resistance is 20k omega; otherwise, turning on the array control switch S7, comparing VPIN with the reference voltage 3.1V, and if the comparison result shows that VPIN is less than 3.1V, identifying that the configuration resistance is 27k omega; otherwise, turning on the array control switch S8, comparing VPIN with the reference voltage 4.2V, and if the comparison result shows that VPIN is less than 4.2V, identifying that the configuration resistance is 36.5k omega; otherwise, recognizing that the configuration resistance is infinity, namely the configuration pin is suspended.
The total of 8 different configuration resistors and 4 different configuration capacitors can be 32 combinations of resistors and capacitors, so that 32 functional states can be configured through one configuration pin.
After the constant current is output to the configuration pin, the configuration resistor flows away a part of current, and the other part of current charges the configuration capacitor. A minimum reference voltage is selected that is lower than the IR drop voltage generated by the constant current flowing entirely through the minimum configured resistance. For a certain value of the configuration capacitor, the time required for charging the configuration capacitor to reach the lowest reference voltage depends on the value of the configuration resistor. The larger the configuration resistance is, the shorter the charging time is; the smaller the configuration resistance, the longer the charging time. And selecting a certain sampling time, wherein the time for charging the large capacitor and the maximum resistor to reach the lowest reference voltage is longer than the sampling time, and the time for charging the small capacitor and the minimum resistor to reach the lowest reference voltage is shorter than the sampling time. At the sampling time point, the voltage of the configuration pin is compared with the lowest reference voltage, and whether the configuration capacitor is a large capacitor or a small capacitor can be distinguished. This is the principle of the method for identifying the value of the configuration capacitor.
When the time for the constant current to be output to the configuration pin is long enough, the charging current of the configuration capacitor is smaller and smaller, and the voltage on the configuration pin gradually approaches the IR drop voltage generated by the constant current flowing through the configuration resistor. At this point in time, the voltage of the configuration pin is compared with reference voltages of different levels, and the value range of the configuration resistor can be identified. This is the principle of the method for identifying the value of the configuration resistance.
According to the invention, the configuration circuit of the functional gear comprises the configuration capacitors and the configuration resistors with different values, and the configuration capacitors and the configuration resistors are connected in parallel to the configuration pins, so that the configuration of various functional states of the chip can be realized. On the basis of the traditional voltage detection dimension, the time detection dimension is introduced, the configuration of chip functions is realized through the two-dimensional combination of resistors and capacitors with different values, the number of configurable function gears of a single pin is greatly increased, the quantity of chip pin requirements is reduced, the chip packaging cost is reduced, and the chip volume is reduced.
Example 3:
referring to fig. 7, the present invention further provides a system for detecting a chip configuration pin, including:
an input module M1 for inputting a constant current to the functional gear configuration circuit and the configuration pin;
the detection module M2 is used for detecting the voltage of the configuration pin at each sampling time point according to the time array;
the comparison module M3 is configured to compare the voltage at each sampling time point with a reference voltage to obtain a comparison result;
an identification module M4, configured to identify a resistance value and a capacitance value of the function gear configuration circuit according to the comparison result;
a configuration module M5, configured to configure a chip function state according to the resistance value and the capacitance value.
The emphasis of each embodiment in the present specification is on the difference from the other embodiments, and the same and similar parts among the various embodiments may be referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.

Claims (9)

1. A circuit for detecting a chip configuration pin, comprising:
the function gear configuration circuit is connected with the voltage comparison circuit through a configuration pin;
the detection control unit is connected with the voltage comparison circuit and used for comparing the voltage of the configuration pin with the reference voltage according to the time array and identifying the resistance value and the capacitance value of the function gear configuration circuit;
the sampling time array unit is connected with the detection control unit and is used for setting a time array for sampling the voltage of the configuration pin;
and the configuration identification unit is connected with the detection control unit and used for performing two-dimensional combination according to the resistance value and the capacitance value, mapping the two-dimensional combination to a corresponding functional state and realizing the configuration of the functional state of the chip.
2. The detection circuit for the chip configuration pin of claim 1,
the function gear configuration circuit comprises a configuration capacitor and a configuration resistor;
the configuration capacitor and the configuration resistor are connected in parallel to form a parallel branch;
the parallel branch is connected with the voltage comparison circuit through the configuration pin.
3. The detecting circuit for the chip configuration pin according to claim 2, wherein the configuration resistors with N different resistance values and the configuration capacitors with M different capacitance values realize the configuration of N x M functional states, wherein N, M is a positive integer, N is greater than or equal to 2, and M is greater than or equal to 2.
4. A method for testing a chip configuration pin, wherein the testing circuit of any one of claims 1 to 3 is used, comprising:
inputting current of a current source to a function gear configuration circuit and a configuration pin;
detecting the voltage of the configuration pin at each sampling time point according to the time array;
comparing the voltage of each sampling time point with a reference voltage to obtain a comparison result;
identifying a resistance value and a capacitance value of the function gear configuration circuit according to the comparison result;
and configuring the functional state of the chip according to the resistance value and the capacitance value.
5. The method of claim 4, wherein the time array comprises sampling time points;
the number of the sampling time points is determined according to the type of the value of the configuration capacitor in the function gear configuration circuit, and M sampling time points are determined according to the value types of M configuration capacitors, wherein M is a positive integer and is more than or equal to 2.
6. The method as claimed in claim 5, wherein the sampling time point is determined according to the current source current, the lowest reference voltage, the maximum configuration resistance, the minimum configuration resistance and the configuration capacitance.
7. The method according to claim 5, wherein the comparing the voltage at each sampling time point with a reference voltage to obtain a comparison result; identifying the resistance value and the capacitance value of the functional gear configuration circuit according to the comparison result, which specifically comprises the following steps:
sequentially comparing the voltages of the configuration pins corresponding to the previous (M-1) sampling time points with the lowest reference voltage respectively to obtain a first comparison result;
identifying a capacitance value of the function gear configuration circuit according to the first comparison result;
comparing the voltage of the configuration pin at the Mth sampling time point with a reference voltage to obtain a second comparison result;
and identifying the resistance value of the function gear configuration circuit according to the second comparison result.
8. The method according to claim 7, wherein the voltages of the configuration pins corresponding to the first (M-1) sampling time points are sequentially compared with the lowest reference voltage, respectively, to obtain a first comparison result; identifying a capacitance value of the functional gear configuration circuit according to the first comparison result, specifically including:
taking the ith sampling time point as a comparison point, wherein i is more than or equal to 1, and i is a positive integer;
comparing the voltage of the configuration pin of the comparison point with the lowest reference voltage;
if the voltage of the configuration pin of the comparison point is greater than the lowest reference voltage, the capacitance value of the function gear configuration circuit is the value of the ith configuration capacitor;
if the voltage of the configuration pin of the comparison point is less than the lowest reference voltage, making i = i +1, and returning to the step of taking the ith sampling time point as the comparison point until i = M-2;
comparing the voltage of the configuration pin corresponding to the (M-1) th sampling time point with the lowest reference voltage;
if the voltage of the configuration pin corresponding to the (M-1) th sampling time point is greater than the lowest reference voltage, the capacitance value of the function gear configuration circuit is the value of the (M-1) th configuration capacitor;
and if the voltage of the configuration pin corresponding to the (M-1) th sampling time point is less than the lowest reference voltage, the capacitance value of the function gear configuration circuit is the value of the Mth configuration capacitor.
9. The method according to claim 7, wherein the voltage of the configuration pin at the mth sampling time point is compared with a reference voltage to obtain a second comparison result; identifying the resistance value of the functional gear configuration circuit according to the second comparison result, specifically including:
closing a first one of the array control switches, wherein the array control switch is configured to select a reference voltage;
taking the voltage of a configuration pin after the jth control switch in the array control switches is conducted as a voltage to be detected, wherein j is more than or equal to 2 and is a positive integer;
taking the jth reference voltage as a comparison voltage;
comparing the voltage to be detected with the comparison voltage;
if the voltage to be detected is smaller than the comparison voltage, the resistance value of the function gear configuration circuit is the value of the (j-1) th configuration resistance;
if the voltage to be detected is larger than the comparison voltage, making j = j +1, and judging whether j is equal to N, wherein N represents the number of the value types of the configuration resistor, N is larger than or equal to 2, and N is a positive integer;
if j is not equal to N, returning to the step of taking the voltage of the configuration pin after the jth control switch in the array control switches is conducted as the voltage to be detected, wherein j is not less than 2, and j is a positive integer; a step of using the jth reference voltage as a comparison voltage; otherwise, the resistance value of the output function gear configuration circuit is the value of the jth configuration resistor.
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