CN101521395B - Multifunctional input terminal and method thereof - Google Patents
Multifunctional input terminal and method thereof Download PDFInfo
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- CN101521395B CN101521395B CN2008100340845A CN200810034084A CN101521395B CN 101521395 B CN101521395 B CN 101521395B CN 2008100340845 A CN2008100340845 A CN 2008100340845A CN 200810034084 A CN200810034084 A CN 200810034084A CN 101521395 B CN101521395 B CN 101521395B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
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Abstract
The invention discloses a multifunctional input terminal and a method thereof, wherein single terminal is used for setting the integrated circuit to enter three states (state Q0, state Q1 or state Q2)The invention discloses a multifunctional input terminal and a method thereof, wherein single terminal is used for setting the integrated circuit to enter three states (state Q0, state Q1 or state Q2). The circuit in the integrated circuit is connected to the terminal and judges whether the terminal 1) has low connection ratio by external connection; 2) has high connection ratio by external connec. The circuit in the integrated circuit is connected to the terminal and judges whether the terminal 1) has low connection ratio by external connection; 2) has high connection ratio by external connection; and 3) is suspended or basically suspended. If the circuit determines that the terminal is suspended or basically suspended, the circuit sets that part of operating characteristics of the circuition; and 3) is suspended or basically suspended. If the circuit determines that the terminal is suspended or basically suspended, the circuit sets that part of operating characteristics of the circuit (for example, the maximum current IBATT of the circuit for charging the battery) has a value; the value is a resistance value of an external resistor connected to the terminal and is determined by at (for example, the maximum current IBATT of the circuit for charging the battery) has a value; the value is a resistance value of an external resistor connected to the terminal and is determined by a function value. Therefore, an integrated circuit user can select the external resistor with proper resistance value to set that the operating characteristic has a desired value. If the external resisfunction value. Therefore, an integrated circuit user can select the external resistor with proper resistance value to set that the operating characteristic has a desired value. If the external resis tor does not exist, the terminal is suspended and the circuit sets the operating characteristic corresponding to a zero value. In typical application, the zero value corresponds to stopping state. tor does not exist, the terminal is suspended and the circuit sets the operating characteristic corresponding to a zero value. In typical application, the zero value corresponds to stopping state.
Description
Technical field
The present invention relates to a kind of terminal that relates to integrated circuit, its terminal is used for receiving configuration information, and the circuit on collocating integrate circuit relates in particular to Multifunctional input terminal and method.
Background technology
Fig. 1 (prior art) is a kind of block diagram that is connected to the USB device 1 (being mobile phone in this example) on usb host 3 (being PC in this example) by USB cable 2.Usb host 3 comprises USB circuit 4.USB device 1 comprises USB circuit 5.USB cable 2 has the USB plug 6 of a standard, inserts the adaptive USB port 7 on usb host 3, and therefore, usb host can read and write USB circuit 5 in USB device 1 by two data wire D+ on USB cable 2 and D-.USB cable 2 also provides a supply voltage power conductor VIN and a ground wire GND.These wires can be used to the circuit supply to usb host 3 outsides.USB port 7 is defined between its wire VIN and ground GND the voltage of 5.0 volts is provided.But according to configuration, usb host 3 may provide the source current of maximum 100 milliamperes or the source current of maximum 500 milliamperes.
In illustrated system, again give the chargeable lithium ion battery in mobile phone 18 chargings with usb host 3 and USB port 7.Therefore, mobile phone 1 comprises the integrated circuit of battery charger 9 that is connected to USB circuit 5.Integrated circuit of battery charger 9 is also connected on the VIN and GND wire of illustrated USB cable 2.Charger integrated circuit 9 receives the electric energy from flow through supply voltage wire VIN and the ground wire GND of USB cable 2, then recharges to battery 8 with this electric energy.
Fig. 2 has analyzed the form of charging.Filling the stage soon of first, integrated circuit of battery charger 9 charges to battery 8 with constant current I-CONST.Then, in case cell voltage VBATT reaches predefined voltage V-CONST, integrated circuit of battery charger 9 will switch to the constant voltage charge pattern.This constant voltage charge pattern also is referred to as " completing (the top-off) " stage sometimes.The charger integrated circuit has passed to battery to energy under the pattern of this constant voltage charge, so that cell voltage VBATT has had the predefined time interval to maintain predefined charging scope, afterwards, integrated circuit of battery charger 9 will stop providing energy to battery 8.Vertical line 13 explanation this point in Fig. 2.
Set forth by top, USB port 7 may only can provide the source current of 100 milliamperes, perhaps may be able to provide the source current of 500 milliamperes.Filling the stage soon, expectation is charged to battery 8 with larger constant current, if USB port can provide larger charging current.Therefore, if USB port 7 can provide the source current of flow through VIN and the GND wire of 500 milliamperes, so in the constant current charge stage, the charger integrated circuit will be with the current charges of 500 milliamperes.The information of source current amount that USB circuit 4 in usb host 3 can be exported to the expression main frame its USB port 7 is written to the USB circuit 5 in mobile phone 1.Then, USB circuit 5 offers integrated circuit of battery charger 9 to this information with the form of digital logic signal.If it is the first digit logical value that USB circuit 5 drives these digital logic signals, so, USB can export a maximum (such as, 100 milliamperes) electric current; But, be the second digit logical value if USB circuit 5 drives these digital logic signals, so, USB can export another maximum (such as, 500 milliamperes) electric current.Integrated circuit of battery charger 9 receives this signal on first terminal (T1) 11.
The battery charging can also be opened or stop to usb host 3 in this case example (being PC here).USB circuit 4 in main frame 3 is written to USB circuit 5 in mobile phone 1 to an information bit.This information bit indication charger is open or stop.Then, this information bit passes on integrated circuit of battery charger 9 from USB circuit 5 with the form of second digit logical signal.Integrated circuit of battery charger 9 receives this second digit logical signal on second terminal (T2) 12.Therefore, integrated circuit of battery charger 9 has two terminals 11 and 12, to receive the configuration information from USB circuit 5.
Fig. 3 has illustrated the digital logic value of first and second digit logical signal on terminal T1 and T2, and the corresponding situation of integrated circuit of battery charger 9 that shows configuration.In a distortion of the traditional USB battery charger of Fig. 1, an extra non-essential resistance can be connected between first terminal T1 and earth potential.In some configurations, the amplitude of the resistance set with constant current of this outside resistance, under constant current mode, this constant current of integrated circuit of battery charger 9 use is to battery 8 chargings.Such as, if the signal that terminal T2 receives is that Digital Logic is low, charger stops so; Otherwise according to Fig. 2, with a constant current charges, wherein determined by the resistance that is connected to the non-essential resistance on terminal T1 by constant electric current in the charging quickly stage for charger.According to specific traditional circuit, terminal T1 may or may not be connected to a terminal of USB circuit 5.Need like this improvement traditional batter-charghing system described above.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of Multifunctional input terminal and method, and it can realize multi-functional input, and then has reduced terminal number, thereby has reduced the manufacturing cost of USB device.
In order to solve above technical problem, the invention provides a kind of Multifunctional input terminal.Wherein single terminal can be used to arrange integrated circuit and enters tri-state (state Q0, state Q1 or state Q2).Circuit in integrated circuit is connected to this terminal, and determines this terminal is whether: 1) by the outside connect be connected into low, 2) connect by the outside be connected into height, 3) unsettled or basically unsettled.If it is unsettled or basically unsettled that circuit is determined this terminal, so, the part operation characteristic that circuit will arrange circuit (for example, the maximum current IBATT that circuit charges the battery is set) have a value, this value be the non-essential resistance resistance that is connected to terminal be come by a functional value that arranges fixed.Therefore, the integrated circuit user can arrange by the non-essential resistance of selecting suitable resistance operation characteristic and has a value of wanting.If non-essential resistance does not exist, terminal is unsettled so, and the circuit setting has the operation characteristic of the null value of corresponding to.In the typical case used, null value corresponded to halted state.
In addition, the present invention also provides a kind of method that realizes multi-functional input, the method comprises the following steps: determine (a) whether ic terminal is shorted on the source of digital logic high voltage, perhaps whether terminal is shorted on the source of digital logic low voltage, perhaps whether terminal is unsettled or is connected to by relatively high impedance on the source of a DC potential, wherein the decision of (a) is to be made by the internal circuit of integrated circuit, and terminal is the part of this integrated circuit; (b) statement first digit logical signal is if determine that (a) terminal of integrated circuit is to be shorted on the source of digital logic high voltage; (c) statement second digit logical signal is if determine that (a) terminal of integrated circuit is to be shorted on the source of digital logic low voltage; (d) statement third digit logical signal, if (a) terminal of definite integrated circuit is unsettled or is connected to by relatively high impedance on the source of a DC potential, wherein above-mentioned (b), (c) and (d) in statement be to be realized by the internal circuit of integrated circuit; And (e) provide the electric current of an adjustment, if (a) terminal of definite integrated circuit is unsettled or is connected to by relatively high impedance on the source of a DC potential, the amplitude of the electric current of wherein adjusting is that the resistance by the non-essential resistance that is connected to ic terminal determines, wherein non-essential resistance is the outside at integrated circuit.
The above-mentioned terminal of the present invention and circuit and method are particularly suitable for being used on the USB battery charger.In many application, use terminal of the present invention and circuit and method, allow the terminal number of USB integrated circuit of battery charger to reduce one.The minimizing of terminal number has reduced the manufacturing cost of the USB device (as mobile phone) of using this USB integrated circuit of battery charger.
Description of drawings
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Fig. 1 is the schematic diagram that is used in the tradition six terminal USB integrated circuit of battery charger on mobile phone in prior art.
Fig. 2 be in Fig. 1 traditional USB integrated circuit of battery charger how to the charging of the rechargeable battery on the mobile phone in Fig. 1 schematic diagram.
Fig. 3 analyzes digital signal how the form of USB integrated circuit of battery charger is set on two terminals of the traditional USB integrated circuit of battery charger of Fig. 1.
Fig. 4 is the schematic diagram of system 100 of the present invention, and according to the aspect of a novelty, this system comprises novel USB integrated circuit of battery charger 109.
Fig. 5 is that novel USB integrated circuit of battery charger 109 in Fig. 4 is how to the schematic diagram of rechargeable battery 108 chargings on the mobile phone 101 in Fig. 4.
Fig. 6 is a form, and how its single terminal 112 (T1) of having analyzed novel USB integrated circuit of battery charger 109 configures one of them that USB integrated circuit of battery charger 109 enters three kinds of states.
Fig. 7 is a form, and it illustrates five terminals and the function corresponding to terminal of USB integrated circuit of battery charger 109 in Fig. 4.
Fig. 8 and 9 forms the circuit diagram of a circuit 200 in USB integrated circuit of battery charger 109 together.Circuit 200 detects the wherein state (Q0, Q1, Q2) of integrated circuit 109 configurations.
Figure 10 is a form, and it illustrates three kinds of states of circuit 200 operations in Fig. 8 and 9.It has also illustrated the corresponding function that USB integrated circuit of battery charger 109 is realized under each state of three kinds of states.
Figure 11 is the alternative biasing networks that in Fig. 8 and 9, the grid voltage to transistor M1 and M2 of circuit 200 is setovered.
Figure 12 is the schematic diagram of alternative method, and this alternative method can be connected to USB integrated circuit (as the USB integrated circuit 105 in Fig. 4) on novel USB integrated circuit of battery charger 109.
Embodiment
" member " of indication of the present invention refers to have components and parts or the circuit that certain function maybe can realize certain function, such as specifically referring to circuit 200 (Fig. 8) etc. in embodiment below.In addition, " the supply voltage terminal " of indication of the present invention refers to input voltage terminal 205 (Fig. 8) in the present embodiment, " Digital Logical Circuits " of indication of the present invention refers to inverter 209 (Fig. 8) in the present embodiment, " second Digital Logical Circuits " of indication of the present invention refers to inverter 211 (Fig. 8) in the present embodiment, " the digital decoding circuit " of indication of the present invention refers to digital decoder 217 (Fig. 8) in the present embodiment, and " programmable current source " of indication of the present invention refers to current source circuit 219 (Fig. 8) in the present embodiment.Above-mentioned corresponding relation is only in order better to explain further and illustrate concrete application of the present invention, and should not be considered as limitation of the present invention.
Fig. 4 is the schematic diagram of system 100 of the present invention, and this system 100 comprises the USB device 101 (being mobile phone in this example) that is connected to usb host 103 (being PC in this example) by USB cable 102.Usb host 103 comprises USB circuit 104.USB device 101 comprises USB circuit 105.USB cable 102 has the USB plug 106 of a standard, inserts the adaptive USB port 107 on usb host 103, and therefore, usb host 103 can read and write USB circuit 105 in USB device 101 by two data wire D+ on USB cable 102 and D-.USB cable 102 also provides a supply voltage power conductor VIN and a ground wire GND.These wires can be used to the circuit supply to usb host 103 outsides.USB port 107 is defined between its wire VIN and ground GND the voltage of 5.0 volts is provided.But according to configuration, usb host may provide the source current of maximum 100 milliamperes or the source current of maximum 500 milliamperes.
In illustrated system, again give the chargeable lithium ion battery in mobile phone 101 108 chargings with usb host 103 and USB port 107.Square frame 101A is the local expansion figure of mobile phone 101.Square frame 101A comprises novel integrated circuit of battery charger 109, and it is connected on USB circuit 105 with novel manner.As scheme to illustrate, integrated circuit of battery charger 109 is also connected on the wire VIN and GND of USB cable 102.Charger integrated circuit 109 receives the electric energy from flow through supply voltage wire VIN and the ground wire GND of USB cable 102, then recharges to battery 108 with these electric energy.
Fig. 5 has analyzed the form of charging.Filling the stage soon of first, integrated circuit of battery charger 109 charges to battery 108 with constant current I-CONST.Then, in case cell voltage VBATT reaches predefined voltage V-CONST, mains charger integrated circuit 109 will switch to the constant voltage charge pattern.This constant voltage charge pattern also is referred to as " completing (the top-off) " stage sometimes.Charger integrated circuit 109 has passed to battery 108 to energy under the pattern of this constant voltage charge, so that cell voltage VBATT has had the predefined time interval to maintain predefined charging scope, afterwards, integrated circuit of battery charger 109 will stop providing energy to battery 108.Vertical line 110 explanation this point in Fig. 5.
Set forth by top, USB port 107 may only can provide the source current of 100 milliamperes, and perhaps USB port 107 may be able to provide the source current of 500 milliamperes.Filling the stage soon, expectation can be obtained maximum constant current to battery 108 chargings, if USB port can provide the charging current that increases quantity.Therefore, if USB port 107 can provide the source current of flow through VIN and the GND wire of 500 milliamperes, so in the constant current charge stage, charger integrated circuit 109 will be with the current charges of 500 milliamperes.The information of source current amount that USB circuit 104 in usb host 103 can be exported to the expression main frame its USB port 107 is written to the USB circuit 105 in mobile phone 101.Then, USB circuit 105 offers integrated circuit of battery charger 109 to this information with the form of signal that two digital logic level are arranged.If USB circuit 105 drives digital logic signal IN and wire 111 has the first digit logical value, so that terminal (T1) 112 is connected on ground wire (GND wire) 113, so, the source current that provides of USB port 107 just has first maximum of 100 milliamperes; But if USB circuit 105 drives signal IN and wire 111 has the second digit logical value, so that terminal (T1) 112 is connected on VIN wire 114, so, the source current that USB port 107 provides just has the maximum of second 500 milliamperes.Integrated circuit of battery charger 109 receives this IN signal on a kind of single terminal (T1) 112.
Usb host 103 in this example (being PC here) can also make charger integrated circuit 109 with constant current, is exactly " user " selected value, gives battery 108 chargings.The term here " user " typically refers to " user " of mobile phone manufacturer or USB integrated circuit of battery charger 109, and they buy this integrated circuit, and they are arranged on product such as mobile phone 101.It is to be determined by the resistance that is connected to the non-essential resistance 115 on terminal T1 that charger integrated circuit 109 is given the constant current of battery 108 chargings.Non-essential resistance 115 is the outsides at charger integrated circuit 109.Although in a particular embodiment, usb host 103 can not as the example of prior art in Fig. 1 to 3, stop charger integrated circuit 109, still, charger integrated circuit 109 has terminal number still less, and charger integrated circuit 109 is communicated by letter with USB circuit 105 by these terminals.
Fig. 6 is the function of explanation USB integrated circuit of battery charger 109 or the form of configuration.If being " connecing low " or other, terminal T1 is connected to digital logic low voltage on GND wire 113 through short circuit or relatively low impedance, so signal IN is referred to as at the low state " 0 " of Digital Logic.Charger integrated circuit 109 detects this " 0 " state and the maximum that arranges to the constant current of battery 108 chargings is 100 milliamperes.If being " connecing height " or other, terminal T1 is connected to digital logic high voltage on VIN wire 114 through short circuit or relatively low impedance, so signal IN is referred to as in Digital Logic high state " 1 ".Charger integrated circuit 109 detects this one state and the maximum that arranges to the constant current of battery 108 chargings is 500 milliamperes.If terminal T1 does not have " connecing height " or " connecing low ", in the specific embodiment of Fig. 4, terminal T1 receives on earth potential with the non-essential resistance 115 of relatively large resistance so.The state of this high impedance represents with " R " in the form of Fig. 6.Charger integrated circuit 109 detects this " R " state and the maximum that arranges to the constant current of battery 108 chargings is a current value, and this current value is that a predetermined function of the resistance of non-essential resistance 105 decides.
Fig. 7 is the form of illustrating the terminal of USB integrated circuit of battery charger 109.Notice five terminals are arranged here, in conjunction with Fig. 8,9, can find out they be respectively IN (terminal) 112, CHAGER FINISH (charging is completed) terminal 116, VBATT (battery charging) terminal 203, GND () terminal 204 and VIN (input voltage) terminal 205, they in contrast in Fig. 1 traditional USB integrated circuit of battery charger six terminals are arranged.After in Fig. 5, battery charging process was completed, integrated circuit of battery charger 109 was completed the terminal 116 drive currents light-emitting diode (LED) 117 of flowing through from charging, thereby sends the charged indication of a visible battery 108.Another is chosen as, and make light-emitting diode (LED) 117 luminous in battery 108 charging processes, and LED 117 is not luminous when charging is completed.
Fig. 8 and 9 forms a circuit diagram together, the circuit diagram of a new circuit 200 in USB integrated circuit of battery charger 109.Circuit 200 is determined: 1) whether terminal 112 (T1) is connected on GND wire 113 by relatively low impedance in the outside of integrated circuit 109 and (is referred to as state Q0), 2) whether terminal 112 (T1) is connected on VIN wire 114 by relatively low impedance in the outside of integrated circuit 109 and (is referred to as state Q1), 3) whether terminal 112 (T1) is unsettled or be connected to a direct voltage source in the outside of integrated circuit 109 by relatively high impedance, as (being referred to as state Q2) on GND wire 113.
If circuit 200 determines that terminal 112 (T1) is at state Q0, circuit 200 provides electric current I BATT by wire 201 so.In the present embodiment, in the constant current quick charge stage of battery charging, electric current I BATT flow through logic and multiplexer 202 and VBATT terminal 203 are fed to battery 108.In state Q0, the amplitude of this electric current is 100 milliamperes.If circuit 200 determines that terminal 112 (T1) is at state Q1, to provide amplitude by wire 201 be the IBATT electric current of 500 milliamperes to circuit 200 so.If circuit 200 determines that terminal 112 (T1) is at state Q2, to provide amplitude by wire 201 be (12 * 10 to circuit 200 so
6/ R) milliampere IBATT electric current, wherein R unit is ohm.R is the resistance of non-essential resistance 115.Figure 10 has illustrated circuit 200 at Q0, Q1, the function under every kind of state of Q2 state.
The below sets forth the running of the circuit 200 in Fig. 8 and 9.
State Q2:
For purposes of illustration, suppose that terminal 112 (T1) is unsettled and is not connected with other node fully.Suppose not exist resistance 115.N slot field-effect transistor (NFET) M1 and P-channel field-effect transistor (PEFT) transistor (PFET) M2 only are biased in lightly conducting in this case.NFET M1 is biased in conducting less than the electric current of electric current I 1.Current source 206 is nonideal current sources, and node N2 is drawn high to voltage VIN.The voltage VIN of node N2 is digital logic high voltage.It is digital logic low that Digital Logic inverter 209 detects this situation statement signal A.Then inverter 210 statement signal AB are the high value of Digital Logic (" B " here is the anti-of representative " resistance barrier (bar) " or signal A).Note that in the form of Figure 10, the signal A of state Q2 is appointed as digital " 0 ", and signal AB is appointed as numeral " 1 ".
Similarly, PFET M2 is biased in conducting less than the electric current of electric current I 2.Therefore current source 207 is pulled low to node N3 the earth potential of ground terminal 204.The voltage of node N3 is digital logic low voltage.Therefore, inverter 212 statement signal BB are digital logic low.Note that in the form of Figure 10, the signal B of state Q2 is appointed as numeral " 1 ", and signal BB is appointed as digital " 0 ".
Form digital decoder 217 with door 213-215 and inverter 216.Decoder 217 detection signal AB are claimed as height and signal B is claimed as height, and output signal Q2 is the high situation of Digital Logic.Other state output signal Q0 and Q1 are not claimed as height.Note that in the form of Figure 10, the signal Q2 of state Q2 is digital logic high levels, but signal Q0 and Q1 are digital logic low levels.
The gate bias that biasing networks 218 is given transistor M1 and M2 makes transistor M1 and M2 in the lightly conducting pattern.Transistor M3 is connected with M4 that each is that diode connects, so the electromotive force between the grid of transistor M1 and M2 is approximately the voltage drop of two forward biased diodes.This is biased in voltage drop between the grid of transistor M1 and M2 and is approximately two threshold voltages, and therefore, transistor M1 and M2 are only lightly conducting.Voltage drop unit 218A with node N4 be arranged on one above Ground electromotive force but be optional dc offset voltage.Such as, voltage drop unit 218A may be a resistance of suitable value, the voltage that node N4 is set is 0.5 volt.Current source 208 provides flow through the transistor M3 of diode connection and the electric current of M4, sets up the voltage drop through transistor M3 and M4, so that gate bias voltage between node N1 and N4 to be set.
Yet, in the example of Fig. 4 to 10, the connection of setting up a relative high impedance with non-essential resistance 115 between terminal 112 (T1) and GND terminal 204.This resistance is enough high, so that can not drag down the source electrode of NFET M1, so NFET M1 draws the electric current same with I1.In addition, during the maximum current that allows less than current source circuit 219 at the electric current of needs, current source circuit 219 is kept the voltage of terminal 112 at 1.2 volts.Therefore, the electric current that NFET M1 draws is less than electric current I 1, and node N2 remains on the state that the high and decoder 217 of Digital Logic continues to detect Q2.
As Fig. 9 explanation, current IS ET2 is the mirror image of the NFET current mirror by comprising N channel transistor 224 and 225 again.It is the current IS ET triple channel switching circuit 226 of flowing through as a result.Switching circuit 226 is subject to the control of digital state signal Q0, Q1, Q2, and therefore, when Q2 is claimed as when high, switching circuit 226 connects its Q2 switching nodes to its output node.Because the in-phase input end of differential amplifier 228 is inputs of high impedance, institute is so that current IS ET flows through resistance 227.The work of differential amplifier 228 makes the voltage of its in-phase input end and inverting input almost completely equal.Therefore, make the voltage drop on resistance 227 the same with the voltage drop on resistance 229.Be an one thousandth of the resistance of resistance 227 by the resistance that makes resistance 229, making electric current I BATT is 1,000 times of current IS ET.Electric current I BATT flow through wire 201, logic and switching circuit 202, and flow out VBATT terminal 203, give above-mentioned battery 108 chargings.The current amplitude of this milliampere magnitude is approximately 12 * 10
6Divided by R, wherein R is the resistance of non-essential resistance 115.
If it is unsettled there is no resistance or other circuit and terminal 112 here, but not terminal of being connected to 112 (T1) and ground non-essential resistance 115 between terminal 204 is arranged.So, do not have electric current can flow out terminal 112.Under this kind configuration, current source circuit 219 does not conduct the electric current through NFET 221, and electric current I 4 is zero, and the electric current I BATT of wire 201 is also zero.This is " not charging " or " stopping " state that stops the battery charging.In the specific embodiment of Fig. 4, provide usb host 103 that the ability that stops charging is arranged, require not have non-essential resistance 115.Therefore, the electric current I BATT that does not have the client to set.In state Q2, IBATT is zero.Here suppose that amplifier 220 is ideal circuit of zero imbalance, and mate well between nonideal current source I1 and I2.Any offset error or mismatch between I1 and I2 that causes due to the input offset voltage of amplifier 220 will be exaggerated 10,000 times, then output to VBATT terminal 203 and charge the battery.Additional circuit, Fig. 8 and not illustrating detects minimum current value, when ISET2＜IMIN being detected, makes IBATT=0.
As shown in Figure 9, provide a charging to complete testing circuit 233.After the charge cycle in Fig. 5 was completed, testing circuit 233 driving LED 117 were completed in charging, come pilot cell 108 charged with this.Another is chosen as, and charging completing circuit 233 stops driving LED 117 and no longer carries out with the expression charging.
State Q0:
If terminal 112 (T1) is shorted on ground wire 113 or is connected on ground wire 113 with short circuit or relatively low impedance, the voltage on terminal 112 drags down from the due voltage of state Q2 so.The voltage of terminal 112 is exactly the source voltage of NFET M1.Therefore the voltage that reduces on terminal 112 realizes increasing the source electrode of transistor M1 to the voltage of grid, because the grid of transistor M1 is biased in a fixing direct voltage.Along with the reduction of voltage on terminal 112, the conducting that therefore transistor M1 also becomes more and more stronger is until the more electric current of electric current I 1 of transistor M1 conduction ratio current source 206.In this point, the voltage of node N2 is pulled down to digital logic low voltage.Therefore inverter 209 states that signal A is the high value of Digital Logic, and inverter 210 statement signal AB are digital logic low.Note that in the form of Figure 10, the signal A of Q0 statusline is designated as Digital Logic " 1 ".Similarly, please note that signal AB is designated as Digital Logic " 0 ".
The voltage that drags down terminal 112 reduces the source voltage of PFET M2, has reduced the grid of PFETM2 to source voltage.Therefore do not make PFET M2 that stronger conducting is arranged in the Q2 state than it.Node N3 is digital logic low, and inverter 211 statement signal B are the high value of Digital Logic, and inverter 212 statement signal BB are digital logic low.Note that in Figure 10 form, the signal B of Q0 statusline is designated as Digital Logic " 1 ".Similarly, please note that signal BB is designated as Digital Logic " 0 ".
These situations of decoder 217 decoding, signal A wherein is that the high and signal B of Digital Logic is that Digital Logic is high, and statement status signal Q0 is that Digital Logic is high.With reference to Fig. 9, please note the status signal control switch circuit 226 (seeing Fig. 9) of Q0, Q1, Q2.Because status signal Q0 is declared, so connecting the Q0 switch, switching circuit 226 is input to switch output.Switch input Q0 is connected to the current source 230 of 100 microamperes.Therefore draw this electric current of 100 microamperes to flow through switching circuit 226.Due to resistance 227,229, the effect of amplifier 228 and PFET 231, electric current I BATT is 1,000 times of electric current of current source 230 of flowing through.Therefore in state Q0, the electric current I BATT of the wire 201 of flowing through is 100 milliamperes.
State Q1:
If terminal 112 (T1) is shorted to digital logic high voltage VIN (5.0 volts) or is connected on VIN wire 114 by relatively low impedance, the voltage of terminal 112 will be drawn high voltage VIN so.The voltage of terminal 112 is source voltages of PFET M2.Therefore the voltage that increases on terminal 112 realizes increasing the source electrode of transistor M2 to the voltage of grid, is biased on a fixing direct voltage because the grid of transistor M2 is biased network 218.The more electric current of transistor M2 conduction ratio electric current I 2.Therefore, the voltage transition of node N3 is to digital logic high voltage.Inverter 211 statement signal B are digital logic low, and inverter 212 statement signal BB are the high value of numeral.Note that in the form of Figure 10, the signal BB demonstration of middle that row is declared as Digital Logic " 1 ".
If the voltage of terminal 112 is drawn high voltage VIN, reduced so the grid of transistor M1 to source voltage.Transistor M1 is the more electric current of conduction ratio electric current I 1 no longer.Voltage on node N2 is digital logic high voltage.Signal A has digital logic low, and signal AB has the high value of Digital Logic.Note that in the form of Figure 10, middle that row signal AB shows it is to be declared as Digital Logic " 0 ".
These situations of decoder 217 decoding, wherein signal AB is that the high and signal BB of Digital Logic is that Digital Logic is high, and statement status signal Q1 is the high value of Digital Logic.Referring again to Fig. 9, signal Q1 control switch circuit 226 is so that switch input Q1 is connected to its switch output by switching circuit 226.The current source 232 of 500 microamperes attaches to the switch input of Q1, therefore, makes the current flowing resistance 227 of 500 microamperes.This electric current is exaggerated device 229 and PFET231 amplifies, thereby electric current I BATT is the multiple of 500 microamperes of electric currents.In the example of Fig. 9, this multiple is 1,000 times.Therefore, the electric current of 500 milliamperes flow through multiplexer and logic 202, and flow out VBATT terminal 203, give battery 108 chargings.Therefore in state Q1, the electric current that flows through wire 201 is 500 milliamperes.
If circuit 200 operates in state Q0, wherein terminal 112 is shorted to other voltage of a DC potential by low-down external impedance, rather than 1.2 volts, and if current source circuit 219 is being worked, current source circuit 219 will attempt to drive the voltage of terminal 112 to 1.2 volts so.As mentioned above, the work of differential amplifier 220 with the voltage of the in-phase input end that keeps it and inverting input at identical electromotive force.In the case, due to low-down external impedance, electric current I 4 may be a large electric current that exceeds to expect, it may cause in integrated circuit 109 and damage or waste unacceptable a large amount of power consumption.Therefore, transistor 221 is got the size of a less W and larger L, so transistor 221 when its grid to source voltage is VIN, has a little maximum current ducting capacity.This will be set to a level (as a milliampere) that can not cause damaging circuit to the maximum of electric current I 4.
In addition, provide a RC timing circuit that comprises resistance 234 and electric capacity 235.When circuit 200 powers on, if circuit 200 is arranged on state Q0, so initial firing current source circuit 219.The input EN that enables of differential amplifier will be high for Digital Logic.Yet, terminal 112 to very low-impedance outside between earth potential connect can conducting with conduction ratio transistor 221 larger electric current, so circuit 200 will detect state Q0 rightly.Therefore decoder 217 will state that signal Q0B is the signal digital logic low.Signal Q0B receives on the RC circuit, so after the time-delay of a short time, enabling input EN and being declared as lowly of differential amplifier 220 thereby stops current source circuit 219.Therefore, in the beginning that enters the Q0 state, the moment situation that it is a short time that electric current I 4 is flowing the large electric current situation of electric current.Circuit 200 in the Q0 state stops current source circuit 219 in subsequently normal work period.
When circuit 200 powered on, it was to connect lowly that circuit 200 does not also detect terminal 112, connects high or at vacant state.If the resistance of outside high value 115 is connected between terminal 115 and ground, and if there is no firing current source circuit 219, so just may not have enough electric currents that is derived from terminal 112 to improve the voltage of terminal 112.If the voltage on this situation and terminal 112 maintains earth potential, will to detect be the state that is operated in Q0 rather than Q2 to circuit 200 so.Circuit 200 will fall into to be died from the situation that this kind detect state Q0, because do not have enough electric currents that is derived from terminal 112 to improve the voltage of terminal 112.Yet, in circuit 200, when powering on, firing current source circuit 219.Under initial electrifying condition, current source circuit 219 rises the voltage of terminal 112, has therefore avoided circuit 200 to fall into the Q0 state of dying from.
General applicability
The above has described a kind of testing circuit and method, whether its detection has an end to be: 1) meet low (state Q0) by short circuit or by relatively low external impedance, 2) connect height (state Q1) by short circuit or by relatively low external impedance, or 3) unsettled or be connected on (state Q2) on a direct voltage by relatively high external impedance.The electric circuit inspection terminal is wherein which the state at these states, and makes response, the digital signal of the state that the output indication detects.If the state that detects is state Q2, the operation characteristic of circuit altering section parallel circuit so, so operation characteristic has an amplitude or numerical value, this amplitude or numerical value are the predetermined functions of resistance of relatively high external impedance.Perhaps, operation characteristic is a magnitude of current that is connected with electric current I BATT as described above, and perhaps perhaps in other embodiments operation characteristic is a magnitude of voltage, frequency values, capacitance, inductance value, filter characteristic, or time, temperature perhaps arranges, perhaps other operation characteristic.Sort circuit and method are in the situation that the function of not using second terminal to realize detecting three kinds of states and operation characteristic is set.We admit, analog to digital converter can be used for detecting one of them of many discrete voltage level of the voltage that input terminal receives, and perhaps detect one of them of many discrete ranges of measured parameter; But the circuit of above-described Fig. 8 and Fig. 9 is more simply too much than increasing a multidigit analog to digital converter.The multidigit analog to digital converter requires the user to provide the digital to analog converter of an equal resolution and precision to drive terminal 112 in integrated circuit usually.In the USB of Fig. 4 battery charger example, novel USB integrated circuit of battery charger 109 has five terminals, and by comparison, in Fig. 1, traditional USB charger system has six terminals.This is one and is particularly suitable for novel circuit and the application-specific of method.
Although for purposes of illustration, combine some specific embodiments and describe the present invention,, the invention is not restricted to this.Figure 11 is the another kind of biasing networks to the gate bias of the transistor M1 of the circuit 200 of Fig. 8 and 9 and M2.Figure 12 is the schematic diagram of alternative method, this alternative method can be connected to USB integrated circuit (as the USB integrated circuit 105 in Fig. 4) on novel USB integrated circuit of battery charger 109, wherein " GPIOA " refers to universal input output A, " GPIOB " refers to universal input output B, and " L " is that low level, " H " are resistance for high level, " HI-Z " for high impedance, " R ".Therefore, the combination of various modification, improvement and the multifrequency nature of described embodiment can try out and not exceed the scope of the present invention of setting forth in the claims.
Claims (12)
1. an integrated circuit, is characterized in that, it comprises:
A terminal;
A circuit, it determines that whether terminal is connected on the source of digital logic high voltage in the integrated circuit outside by relatively low impedance, be connected on the source of digital logic low voltage by relatively low impedance in the integrated circuit outside, perhaps be connected on the source of a direct voltage by relatively high impedance in the integrated circuit outside, this circuit comprises a current source, the electric current of an adjustment of its output, if it is to be connected on the source of direct voltage by relatively high impedance that circuit is determined terminal, the amplitude of the electric current of wherein adjusting is the function of the resistance of relative high impedance.
2. integrated circuit according to claim 1, is characterized in that, it also comprises in addition:
A supply voltage terminal, wherein the supply voltage terminal is the source of above-mentioned digital logic high voltage; With
A ground terminal, wherein terminal is the source of above-mentioned digital logic low voltage.
3. integrated circuit according to claim 1, it is characterized in that, if wherein circuit determines that terminal is to be connected on the source of above-mentioned digital logic high voltage, circuit asserts first digit logical signal, if wherein circuit determines that terminal is to be connected on the source of above-mentioned digital logic low voltage, circuit asserts second digit logical signal, if wherein circuit determines that terminal is to be connected on the source of above-mentioned direct voltage by relatively high impedance, circuit asserts third digit logical signal.
4. integrated circuit according to claim 1, is characterized in that, wherein above-mentioned direct voltage source is the ground terminal of integrated circuit, and wherein terminal is the source of above-mentioned digital logic low voltage.
5. integrated circuit according to claim 1, is characterized in that, wherein circuit comprises:
First current source, it has first node and Section Point;
A N slot field-effect transistor, it has source electrode, grid and drain electrode, and the drain electrode of wherein said N slot field-effect transistor is connected to second node of the first current source, and wherein source electrode is connected to terminal;
A P-channel field-effect transistor (PEFT) transistor, it has source electrode, grid and drain electrode, and the transistorized source electrode of wherein said P-channel field-effect transistor (PEFT) is connected to terminal; With
Second current source, it has first node and Section Point, and wherein the first node of the second current source is received the transistorized drain electrode of described P-channel field-effect transistor (PEFT).
6. integrated circuit according to claim 5, is characterized in that, it also comprises in addition:
A Digital Logical Circuits, it has an input and an output, and wherein input is connected to the Section Point of the first current source.
7. integrated circuit according to claim 6, is characterized in that, it also comprises in addition:
Second Digital Logical Circuits, it has an input and an output, and wherein the input of the second Digital Logical Circuits is connected to the first node of the second current source.
8. integrated circuit according to claim 5, is characterized in that, wherein circuit also comprises in addition:
A biasing networks, the gate bias of its described N slot field-effect transistor on first almost completely constant direct voltage, and the transistorized gate bias of described P-channel field-effect transistor (PEFT) on second almost completely constant direct voltage.
9. integrated circuit according to claim 5, is characterized in that, wherein circuit also comprises in addition:
A biasing networks, the grid of its described N slot field-effect transistor and the transistorized gate bias of described P-channel field-effect transistor (PEFT) are on identical almost completely constant direct voltage.
10. integrated circuit according to claim 5, it is characterized in that, wherein circuit by detecting in the drain electrode of described N slot field-effect transistor and the digital logic states in the transistorized drain electrode of described P-channel field-effect transistor (PEFT), determines that terminal is connected on the source of digital logic high voltage in the relatively low impedance of the outside use of integrated circuit.
11. integrated circuit according to claim 1 is characterized in that wherein current source comprises;
A transistor, it has grid, source electrode and drain electrode; With
A differential amplifier, it has first differential input end and second differential input end and an output, and wherein the first differential input end is connected to terminal and transistorized source electrode, and wherein the output of differential amplifier is connected to transistorized grid.
12. integrated circuit according to claim 1 is characterized in that, is connected to the source of digital logic low voltage if circuit is determined terminal by relatively low impedance in the outside of integrated circuit, stops so current source.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN2008100340845A CN101521395B (en) | 2008-02-29 | 2008-02-29 | Multifunctional input terminal and method thereof |
| CN201210234833.5A CN103001273B (en) | 2008-02-29 | 2008-02-29 | Multifunctional input terminal |
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| CN2008100340845A CN101521395B (en) | 2008-02-29 | 2008-02-29 | Multifunctional input terminal and method thereof |
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| CN201210234782.6A Division CN103023084B (en) | 2008-02-29 | 2008-02-29 | Multifunctional input terminal |
| CN201210236339.2A Division CN103001274B (en) | 2008-02-29 | 2008-02-29 | Multifunctional input terminal and method |
| CN201210234833.5A Division CN103001273B (en) | 2008-02-29 | 2008-02-29 | Multifunctional input terminal |
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| CN101521395B true CN101521395B (en) | 2013-06-05 |
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| CN103972944B (en) * | 2013-02-05 | 2017-11-17 | 飞思卡尔半导体公司 | Adaptive voltage amplifier and battery charger detection |
| CN107404133A (en) * | 2016-05-20 | 2017-11-28 | 中兴通讯股份有限公司 | Charging method, charger and terminal |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1707900A (en) * | 2004-06-09 | 2005-12-14 | 中国科学院海洋研究所 | Integrated charger |
| CN2857252Y (en) * | 2005-11-24 | 2007-01-10 | 康佳集团股份有限公司 | Cell phone charger having integrated data transmitting functions |
| CN1967965A (en) * | 2005-11-17 | 2007-05-23 | 英华达(上海)电子有限公司 | Charging circuit of electron device with USB interface and method thereof |
| CN201213227Y (en) * | 2008-02-29 | 2009-03-25 | 技领半导体(上海)有限公司 | Multifunctional input terminal |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3949636B2 (en) * | 2003-09-30 | 2007-07-25 | Ｎｅｃエレクトロニクス株式会社 | LVDS driver circuit |
-
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1707900A (en) * | 2004-06-09 | 2005-12-14 | 中国科学院海洋研究所 | Integrated charger |
| CN1967965A (en) * | 2005-11-17 | 2007-05-23 | 英华达(上海)电子有限公司 | Charging circuit of electron device with USB interface and method thereof |
| CN2857252Y (en) * | 2005-11-24 | 2007-01-10 | 康佳集团股份有限公司 | Cell phone charger having integrated data transmitting functions |
| CN201213227Y (en) * | 2008-02-29 | 2009-03-25 | 技领半导体(上海)有限公司 | Multifunctional input terminal |
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