CN103001274B - Multifunctional input terminal and method - Google Patents
Multifunctional input terminal and method Download PDFInfo
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- CN103001274B CN103001274B CN201210236339.2A CN201210236339A CN103001274B CN 103001274 B CN103001274 B CN 103001274B CN 201210236339 A CN201210236339 A CN 201210236339A CN 103001274 B CN103001274 B CN 103001274B
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Abstract
The invention discloses a multifunctional input terminal and a method. An integrated circuit can be set to be in a state Q0, a state Q1 or a state Q2 by the single terminal. A circuit of the integrated circuit is connected to the terminal and determines whether the terminal is connected at a low position through an external connector or not, whether the terminal is connected at a high position through the external connector or not, or whether the terminal is suspended or suspended basically. If the terminal is determined to be suspended or suspended basically, then part of running characteristics of the circuit is set to have a value (for example, the maximum current IBATT of the circuit for charging batteries is set), the value is an external resistance connected to the terminal and is determined by a set function value, and accordingly users of the integrated circuit can set the value of the running characteristics as needed by selecting a moderate external resistance. If the external resistance does not exist, the terminal is suspended, and the running characteristic of the circuit is set to be null. In typical application, the null indicates a stop state of the circuit.
Description
The application is the original applying number submitted to by February 29th, 2008 is 200810034084.5, and name is called Multifunctional input terminal and method divisional application.Meanwhile, this application claims the rights and interests enjoying the Chinese Patent Application No. 200810034084.5 that on February 29th, 2008 submits, be incorporated herein its full content as a reference.
Technical field
The present invention relates to a kind of terminal relating to integrated circuit, its terminal is used for receiving configuration information, and the circuit on collocating integrate circuit, particularly relates to Multifunctional input terminal and method.
Background technology
Fig. 1 (prior art) is that a kind of to be connected to usb host 3(by USB cable 2 be PC in this example) on USB device 1(be mobile phone in this example) block diagram.Usb host 3 comprises USB circuit 4.USB device 1 comprises USB circuit 5.USB cable 2 has the USB plug 6 of a standard, inserts the adaptive USB port 7 on usb host 3, and therefore, usb host can be read by two data wire D+ and D-in USB cable 2 and write the USB circuit 5 in USB device 1.USB cable 2 also provides an a supply voltage power conductor VIN and ground wire GND.These wires can be used to the circuit supply of usb host 3 outside.USB port 7 is defined between its wire VIN and ground GND and provides the voltage of 5.0 volts.But according to configuration, usb host 3 may provide the source current of the source current of maximum 100 milliamperes or maximum 500 milliamperes.
In illustrated system, charge again to the chargeable lithium ion battery 8 in mobile phone 1 by usb host 3 and USB port 7.Therefore, mobile phone 1 comprises the integrated circuit of battery charger 9 being connected to USB circuit 5.Integrated circuit of battery charger 9 is also connected on VIN and the GND wire of illustrated USB cable 2.Charger integrated circuit 9 receives the electric energy flowing through supply voltage wire VIN and ground wire GND from USB cable 2, then recharges to battery 8 with this electric energy.
Fig. 2 analyzes the form of charging.First fill the stage soon, integrated circuit of battery charger 9 charges to battery 8 with constant current I-CONST.Then, once cell voltage VBATT reaches the voltage V-CONST preset, integrated circuit of battery charger 9 will be switched to constant voltage charge pattern.This constant voltage charge pattern is also referred to as sometimes " completing (the top-off) " stage.Charger integrated circuit gives battery energy transferring under the pattern of this constant voltage charge, so that cell voltage VBATT has had the time interval preset to maintain the chargeable range preset, afterwards, stopping is provided energy to battery 8 by integrated circuit of battery charger 9.Vertical line 13 in Fig. 2 illustrates this point.
By set forth above, USB port 7 only may can provide the source current of 100 milliamperes, or may can provide the source current of 500 milliamperes.Filling the stage soon, expecting to charge to battery 8 with larger constant current, if USB port can provide larger charging current.Therefore, if USB port 7 can provide the source current flowing through VIN and GND wire of 500 milliamperes, so in the constant current charge stage, charger integrated circuit is by with the current charges of 500 milliamperes.USB circuit 4 in usb host 3 is representing that information that main frame can export to the power electric flow of its USB port 7 is written to the USB circuit 5 in mobile phone 1.Then, USB circuit 5 is supplied to integrated circuit of battery charger 9 with the form of digital logic signal this information.If USB circuit 5 drives this digital logic signal to be first digit logical value, so, USB can export the electric current of a maximum (such as, 100 milliamperes); But if USB circuit 5 drives this digital logic signal to be second digit logical value, so, USB can export the electric current of another maximum (such as, 500 milliamperes).Integrated circuit of battery charger 9 receives this signal on first terminal (T1) 11.
Usb host 3(in this case example is PC here) can also open or stop battery charging.USB circuit 4 in main frame 3 is written to an information bit in the USB circuit 5 in mobile phone 1.This information bit instruction charger opens or stops.Then, this information bit passes to integrated circuit of battery charger 9 from USB circuit 5 with the form of second digit logical signal.Integrated circuit of battery charger 9 receives this second digit logical signal on second terminal (T2) 12.Therefore, integrated circuit of battery charger 9 has two terminals 11 and 12, to receive the configuration information from USB circuit 5.
Fig. 3 describes the digital logic value of on terminal T1 and T2 first and second digit logical signal, and the situation that the integrated circuit of battery charger 9 showing configuration is corresponding.In a distortion of the traditional USB battery charger of Fig. 1, an extra non-essential resistance can be connected between first terminal T1 and earth potential.In some configurations, the amplitude of the resistance set with constant current of this non-essential resistance, under constant current mode, this constant current of integrated circuit of battery charger 9 is charged to battery 8.Such as, if the signal that terminal T2 receives is that Digital Logic is low, so charger stops; Otherwise according to Fig. 2, charger is in the charging quickly stage with a constant current charges, and wherein constant electric current is determined by the resistance of the non-essential resistance be connected on terminal T1.According to specific traditional circuit, terminal T1 or may may not be connected to a terminal of USB circuit 5.Need like this to improve traditional batter-charghing system described above.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of Multifunctional input terminal and method, and it can realize multi-functional input, and then decreases terminal number, thus reduces the manufacturing cost of USB device.
In order to solve above technical problem, the invention provides a kind of Multifunctional input terminal.Wherein single terminal can be used to arrange integrated circuit and enters tri-state (state Q0, state Q1 or state Q2).Circuit in integrated circuit is connected to this terminal, and whether determines this terminal: 1) be connected into low by outside, and 2) be connected into height, 3 by outside) unsettled or substantially unsettled.If it is unsettled or substantially unsettled that circuit determines this terminal, so, circuit will arrange the part operation characteristic of circuit (such as, the maximum current IBATT that circuit charges the battery is set) there is a value, this value is the non-essential resistance resistance being connected to terminal is determined by the functional value arranged.Therefore, integrated circuit user can have a value wanted by selecting the non-essential resistance of suitable resistance to arrange operation characteristic.If non-essential resistance does not exist, so terminal is unsettled, and circuit is arranged has the operation characteristic corresponding to null value.In typical applications, null value corresponds to halted state.
In addition, present invention also offers a kind of method realizing multi-functional input, the method comprises the following steps: (a) determines whether ic terminal is shorted on the source of digital logic high voltage, or whether terminal is shorted on the source of digital logic low voltage, or whether terminal is unsettled or is connected to by relatively high impedance on the source of a DC potential, wherein the decision of (a) is made by the internal circuit of integrated circuit, and terminal is a part for this integrated circuit; B () statement first digit logical signal, if (a) determines that the terminal of integrated circuit is shorted on the source of digital logic high voltage; C () statement second digit logical signal, if (a) determines that the terminal of integrated circuit is shorted on the source of digital logic low voltage; (d) statement third digit logical signal, if the terminal of the integrated circuit (a) determined is unsettled or is connected to by relatively high impedance on the source of a DC potential, the statement wherein in above-mentioned (b), (c) and (d) is realized by the internal circuit of integrated circuit; And (e) provides an electric current adjusted, if the terminal of the integrated circuit (a) determined is unsettled or is connected to by relatively high impedance on the source of a DC potential, the amplitude of the electric current wherein adjusted is determined by the resistance of the non-essential resistance being connected to ic terminal, and wherein non-essential resistance is the outside at integrated circuit.
The above-mentioned terminal of the present invention and circuit and method are particularly suitable for being used on USB battery charger.In numerous applications, apply terminal of the present invention and circuit and method, allow the terminal number of USB integrated circuit of battery charger to reduce one.The minimizing of terminal number reduces the manufacturing cost of the USB device (as mobile phone) of this USB integrated circuit of battery charger of application.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Fig. 1 is the schematic diagram of the tradition six terminal USB integrated circuit of battery charger be used in prior art on mobile phone.
Fig. 2 be in Fig. 1 traditional USB integrated circuit of battery charger how to the rechargeable battery charging schematic diagram on the mobile phone in Fig. 1.
Fig. 3 analyzes the form how digital signal arranges USB integrated circuit of battery charger in two terminals of the traditional USB integrated circuit of battery charger of Fig. 1.
Fig. 4 is the schematic diagram of present system 100, and according to a novel aspect, this system comprises novel USB integrated circuit of battery charger 109.
Fig. 5 is the schematic diagram how novel USB integrated circuit of battery charger 109 in Fig. 4 charges to the rechargeable battery 108 on the mobile phone 101 in Fig. 4.
Fig. 6 is a form, and it analyzes the single terminal 112(T1 of novel USB integrated circuit of battery charger 109) how to configure USB integrated circuit of battery charger 109 and enter one of them of three kinds of states.
Fig. 7 is a form, and it illustrates five terminals of the USB integrated circuit of battery charger 109 in Fig. 4 and function corresponding to terminal.
Fig. 8 forms the circuit diagram of a circuit 200 in USB integrated circuit of battery charger 109 together with 9.Circuit 200 detects the state (Q0, Q1, Q2) that wherein integrated circuit 109 configures.
Figure 10 is a form, and it illustrates three kinds of states that the circuit 200 in Fig. 8 and 9 runs.It also illustrates the corresponding function that USB integrated circuit of battery charger 109 realizes under each state of three kinds of states.
Figure 11 is the alternative biasing networks biased to the grid voltage of transistor M1 and M2 of circuit 200 in Fig. 8 and 9.
Figure 12 is the schematic diagram of alternative method, and this alternative method can be connected to USB integrated circuit (the USB integrated circuit 105 as in Fig. 4) on novel USB integrated circuit of battery charger 109.
Embodiment
" component " of indication of the present invention refers to have components and parts or the circuit that certain function maybe can realize certain function, such as specifically refers to circuit 200(Fig. 8 in embodiment below) etc.In addition, " power voltage terminal " of indication of the present invention refers to input voltage terminal 205(Fig. 8 in the present embodiment), " Digital Logical Circuits " of indication of the present invention refers to inverter 209(Fig. 8 in the present embodiment), " second Digital Logical Circuits " of indication of the present invention refers to inverter 211(Fig. 8 in the present embodiment), " digital decoding circuit " of indication of the present invention refers to digital decoder 217(Fig. 8 in the present embodiment), " programmable current source " of indication of the present invention refers to current source circuit 219(Fig. 8 in the present embodiment).Above-mentioned corresponding relation is only used to better explain further and embody rule of the present invention is described, and should not be considered as limitation of the present invention.
Fig. 4 is the schematic diagram of present system 100, this system 100 comprise be connected in this example of usb host 103(as PC by USB cable 102) this example of USB device 101(in be mobile phone).Usb host 103 comprises USB circuit 104.USB device 101 comprises USB circuit 105.USB cable 102 has the USB plug 106 of a standard, inserts the adaptive USB port 107 on usb host 103, and therefore, usb host 103 can be read by two data wire D+ and D-in USB cable 102 and write the USB circuit 105 in USB device 101.USB cable 102 also provides an a supply voltage power conductor VIN and ground wire GND.These wires can be used to the circuit supply of usb host 103 outside.USB port 107 is defined between its wire VIN and ground GND and provides the voltage of 5.0 volts.But according to configuration, usb host may provide the source current of the source current of maximum 100 milliamperes or maximum 500 milliamperes.
In illustrated system, charge again to the chargeable lithium ion battery 108 in mobile phone 101 by usb host 103 and USB port 107.Square frame 101A is the local expansion figure of mobile phone 101.Square frame 101A comprises novel integrated circuit of battery charger 109, and it is connected on USB circuit 105 by novel manner.As schemed to illustrate, integrated circuit of battery charger 109 is also connected on wire VIN and GND of USB cable 102.Charger integrated circuit 109 receives the electric energy flowing through supply voltage wire VIN and ground wire GND from USB cable 102, then recharges to battery 108 with these electric energy.
Fig. 5 analyzes the form of charging.First fill the stage soon, integrated circuit of battery charger 109 charges to battery 108 with constant current I-CONST.Then, once cell voltage VBATT reaches the voltage V-CONST preset, mains charger integrated circuit 109 will be switched to constant voltage charge pattern.This constant voltage charge pattern is also referred to as sometimes " completing (the top-off) " stage.Charger integrated circuit 109 gives battery 108 energy transferring under the pattern of this constant voltage charge, so that cell voltage VBATT has had the time interval preset to maintain the chargeable range preset, afterwards, stopping is provided energy to battery 108 by integrated circuit of battery charger 109.Vertical line 110 in Fig. 5 illustrates this point.
By set forth above, USB port 107 only may can provide the source current of 100 milliamperes, or USB port 107 may can provide the source current of 500 milliamperes.Filling the stage soon, expecting that can obtain maximum constant current charges to battery 108, if USB port can provide the charging current increasing quantity.Therefore, if USB port 107 can provide the source current flowing through VIN and GND wire of 500 milliamperes, so in the constant current charge stage, charger integrated circuit 109 is by with the current charges of 500 milliamperes.USB circuit 104 in usb host 103 is representing that information that main frame can export to the power electric flow of its USB port 107 is written to the USB circuit 105 in mobile phone 101.Then, USB circuit 105 is supplied to integrated circuit of battery charger 109 there to be the form of the signal of two digital logic level this information.If USB circuit 105 drives digital logic signal IN and wire 111 to have first digit logical value, so that terminal (T1) 112 is connected on ground wire (GND wire) 113, so, the source current that USB port 107 provides just has the maximum of first 100 milliamperes; But if USB circuit 105 drive singal IN and wire 111 have second digit logical value, so that terminal (T1) 112 is connected on VIN wire 114, so, the source current that USB port 107 provides just has the maximum of second 500 milliamperes.Integrated circuit of battery charger 109 receives this IN signal in the single terminal of one (T1) 112.
Usb host 103(in this example is here for PC) charger integrated circuit 109 can also be made with constant current, be exactly " user " selected value, charge to battery 108.Here term " user " typically refers to " user " of handset manufacturers or USB integrated circuit of battery charger 109, and they buy this integrated circuit, and they are arranged on product as on mobile phone 101.The constant current that charger integrated circuit 109 charges to battery 108 is determined by the resistance of the non-essential resistance 115 be connected on terminal T1.Non-essential resistance 115 is in the outside of charger integrated circuit 109.Although in a particular embodiment, usb host 103 as the example of prior art in Fig. 1 to 3, can not stop charger integrated circuit 109, but, charger integrated circuit 109 has less terminal number, and charger integrated circuit 109 is communicated with USB circuit 105 by these terminals.
Fig. 6 illustrates the function of USB integrated circuit of battery charger 109 or the form of configuration.If terminal T1 be " connecing low " or other be connected to digital logic low voltage on GND wire 113 through short circuit or relatively low impedance, so signal IN is referred to as in digital logic low state " 0 ".Charger integrated circuit 109 detects this " 0 " state and is set to the maximum of constant current that battery 108 charges is 100 milliamperes.If terminal T1 be " connecing height " or other be connected to digital logic high voltage on VIN wire 114 through short circuit or relatively low impedance, so signal IN is referred to as in digital logic high state " 1 ".Charger integrated circuit 109 detects this one state and is set to the maximum of constant current that battery 108 charges is 500 milliamperes.If terminal T1 does not have " connecing height " or " connecing low ", so in the specific embodiment of Fig. 4, terminal T1 receives on earth potential with the non-essential resistance 115 of relatively large resistance.The state of this high impedance represents with " R " in the form of Fig. 6.Charger integrated circuit 109 detects this " R " state and is set to the maximum of constant current that battery 108 charges is a current value, and this current value is that a predetermined function of the resistance of non-essential resistance 105 decides.
Fig. 7 is the form of the terminal illustrating USB integrated circuit of battery charger 109.Notice there are five terminals here, composition graphs 8,9, can find out that they are IN (terminal) 112, CHAGER FINISH (charging complete) terminal 116, the charging of VBATT(battery respectively) terminal 203, GND () terminal 204 and VIN (input voltage) terminal 205, they in contrast in Fig. 1 traditional USB integrated circuit of battery charger have six terminals.After in Fig. 5, battery charging process completes, integrated circuit of battery charger 109 flows through light-emitting diode (LED) 117 from charging complete terminal 116 drive current, thus sends the instruction that a visible battery 108 is charged.Another is chosen as, and make light-emitting diode (LED) 117 luminous in battery 108 charging process, and LED117 is not luminous when charging complete.
Fig. 8 forms a circuit diagram together with 9, the circuit diagram of a new circuit 200 in USB integrated circuit of battery charger 109.Circuit 200 is determined: 1) terminal 112(T1) whether be connected on GND wire 113 by relatively low impedance in the outside of integrated circuit 109 and (be referred to as state Q0), 2) terminal 112(T1) whether be connected on VIN wire 114 by relatively low impedance in the outside of integrated circuit 109 and (be referred to as state Q1), 3) terminal 112(T1) whether unsettled or be connected to a direct voltage source in the outside of integrated circuit 109 by relatively high impedance, as GND wire 113 (is referred to as state Q2).
If circuit 200 determines terminal 112(T1) be at state Q0, so circuit 200 provides electric current I BATT by wire 201.In the present embodiment, in the constant current quick charge stage of battery charging, electric current I BATT flows through logic and multiplexer 202 and VBATT terminal 203, is fed to battery 108.In state Q0, the amplitude of this electric current is 100 milliamperes.If circuit 200 determines terminal 112(T1) be at state Q1, so circuit 200 provides amplitude to be the IBATT electric current of 500 milliamperes by wire 201.If circuit 200 determines terminal 112(T1) be at state Q2, so circuit 200 provides amplitude to be (12 × 10 by wire 201
6/ R) the IBATT electric current of milliampere, wherein R unit is ohm.R is the resistance of non-essential resistance 115.Figure 10 illustrates the function of circuit 200 under often kind of state of Q0, Q1, Q2 state.
Set forth the running of the circuit 200 in Fig. 8 and 9 below.
state Q2:
Current source 206 is nonideal current sources, and it provides electric current I 1.Current source 207 is nonideal current sources, and it provides electric current I 2.Electric current I 1 and I2 approximately equal.Current source 208 is nonideal current sources, and it provides electric current I 3.I3 is much smaller than electric current I 1.
For purposes of illustration, terminal 112(T1 is supposed) be unsettled and be not connected with other node completely.Suppose to there is not resistance 115.N slot field-effect transistor (NFET) M1 and P-channel field-effect transistor (PEFT) transistor (PFET) M2 is only biased in lightly conducting in this case.NFET M1 is biased in the electric current that conducting is less than electric current I 1.Current source 206 is nonideal current sources, and node N2 is drawn high to voltage VIN.The voltage VIN of node N2 is digital logic high voltage.Digital Logic inverter 209 detects that this situation statement signal A is digital logic low.Then inverter 210 states that signal AB is digital logic low high value (" B " be here representative " barrier (bar) " or signal A's is anti-).Note that in the form of Figure 10, the signal A of state Q2 is appointed as digital " 0 ", and signal AB is appointed as numeral " 1 ".
Similarly, PFET M2 is biased in the electric current that conducting is less than electric current I 2.Therefore current source 207 is pulled low to node N3 the earth potential of ground terminal 204.The voltage of node N3 is digital logic low voltage.Therefore, inverter 212 states that signal BB is digital logic low.Note that in the form of Figure 10, the signal B of state Q2 is appointed as numeral " 1 ", and signal BB is appointed as digital " 0 ".
Digital decoder 217 is formed with door 213-215 and inverter 216.Decoder 217 detection signal AB is claimed as height and signal B is claimed as height, and output signal Q2 is the situation that Digital Logic is high.Other state output signal Q0 and Q1 is not claimed as height.Note that in the form of Figure 10, the signal Q2 of state Q2 is digital logic high levels, but signal Q0 and Q1 is digital logic low levels.
Biasing networks 218 gives the gate bias of transistor M1 and M2, makes transistor M1 and M2 in lightly conducting pattern.Each of transistor M3 with M4 is that diode is connected, so the electromotive force between the grid of transistor M1 and M2 is approximately the voltage drop of two forward biased diodes.This makes the voltage drop between the grid of transistor M1 and M2 be biased in and is approximately two threshold voltages, and therefore, transistor M1 and M2 is only lightly conducting.Voltage drop unit 218A node N4 is arranged on one above Ground electromotive force but be optional DC offset voltage.Such as, voltage drop unit 218A may be a resistance of suitable value, and the voltage arranging node N4 is 0.5 volt.Current source 208 provides the electric current flowing through transistor M3 and M4 that diode connects, and sets up the voltage drop through transistor M3 and M4, to arrange gate bias voltage between node N1 and N4.
But, in the example of Fig. 4 to 10, with non-essential resistance 115 at terminal 112(T1) and GND terminal 204 between set up connecting of a relative high impedance.This resistance is enough high, so that the source electrode of NFET M1 can not be dragged down, therefore NFET M1 draws the electric current same with I1.In addition, when the electric current needed is less than the maximum current of current source circuit 219 permission, current source circuit 219 maintains the voltage of terminal 112 at 1.2 volts.Therefore, the electric current that NFET M1 draws is less than electric current I 1, and node N2 remains on the state that the high and decoder 217 of Digital Logic continues to detect Q2.
Circuit 200 comprises current source circuit 219.Current source circuit 219 comprises a differential amplifier 220, and it has an inverting input, an in-phase input end, an enable input EN and output.As schemed to illustrate, in-phase input end is connected to the reference voltage of 1.2 volts.Operationally, the work of the amplifier 220 of high-gain keeps the voltage on its inverting input and in-phase input end almost completely equal.At the duration of work of amplifier, inverting input is therefore also at the voltage of approximate 1.2 volts.Because as figure illustrates, inverting input is connected to terminal 112(T1) on, so the voltage of 1.2 volts appears at terminal 112(T1) on, and the voltage jump of 1.2 volts is on non-essential resistance 115.The electric current flowing through resistance 115 equals 1.2 volts of resistances divided by resistance 115.Because flow into the inverting input of the amplifier 220 of high input impedance almost complete absence of electric current, the electric current therefore flowing through non-essential resistance 115 must also flow through N-channel transistor 221.This electric current is expressed as I4.The amplitude of electric current I 4 is set by the resistance setting non-essential resistance 115.Electric current I 4, by comprising the mirror image of the current mirror of p channel transistor 222 and 223, produces a current IS ET2 be directly proportional with it.PFET 223 may be greater than PFET 222, and therefore current IS ET2 is the multiple of electric current I 4.In this example, the size of PFET222 and the same of PFET 223.
As Fig. 9 illustrates, current IS ET2 is again by comprising the mirror image of the NFET current mirror of N-channel transistor 224 and 225.Its result current IS ET flows through triple channel switching circuit 226.Switching circuit 226 is subject to the control of digital state signal Q0, Q1, Q2, and therefore, when Q2 is claimed as high, switching circuit 226 connects its output node of Q2 switching node to it.Because the in-phase input end of differential amplifier 228 is inputs of high impedance, so make current IS ET flow through resistance 227.The work of differential amplifier 228 makes the voltage of its in-phase input end and inverting input almost completely equal.Therefore, make the voltage drop on resistance 227 the same with the voltage drop on resistance 229.By making the resistance of resistance 229 be one thousandths of the resistance of resistance 227, electric current I BATT is made to be 1,000 times of current IS ET.Electric current I BATT flows through wire 201, logic and switching circuit 202, and flows out VBATT terminal 203, charges to above-mentioned battery 108.The current amplitude of this milliampere of magnitude is approximately 12 × 10
6divided by R, wherein R is the resistance of non-essential resistance 115.
If, there is no resistance or other circuit here and terminal 112 is unsettled, but not have be connected to terminal 112(T1) and ground terminal 204 between non-essential resistance 115.So, electric current is not had can to flow out terminal 112.Under this kind of configuration, current source circuit 219 is not conducted through the electric current of NFET 221, and electric current I 4 is zero, and the electric current I BATT of wire 201 is also zero.This stops battery charging " not charging " or " stopping " state.In the specific embodiment of Fig. 4, provide usb host 103 to have the ability stopping charging, require there is no non-essential resistance 115.Therefore, the electric current I BATT that client can set is not had.In state Q2, IBATT is zero.Here suppose that amplifier 220 is ideal circuit of one zero imbalance, and mate well between nonideal current source I1 and I2.Mismatch between any offset error of causing due to the input offset voltage of amplifier 220 or I1 and I2 will be exaggerated 10,000 times, then output to VBATT terminal 203 and charge the battery.Additional circuit, Fig. 8 and not illustrating, detecting minimum current value, when ISET2<IMIN being detected, making IBATT=0.
As shown in Figure 9, a charging complete testing circuit 233 is provided.After the charge cycle in Fig. 5 completes, charging complete testing circuit 233 driving LED 117, carrys out pilot cell 108 with this charged.Another is chosen as, and charging complete circuit 233 stops driving LED 117 to represent that charging is no longer carried out.
state Q0:
If terminal 112(T1) be shorted on ground wire 113 with short circuit or relatively low impedance or be connected on ground wire 113, the voltage so in terminal 112 drags down from the due voltage of state Q2.The voltage of terminal 112 is exactly the source voltage of NFET M1.Therefore the voltage reduced in terminal 112 realizes increasing the voltage of source electrode to grid of transistor M1, because the grid of transistor M1 is biased in a fixing direct voltage.Along with the reduction of voltage in terminal 112, therefore transistor M1 also becomes more and more stronger conducting, until the more electric current of the electric current I 1 of transistor M1 conduction ratio current source 206.In this point, the voltage of node N2 is pulled down to digital logic low voltage.Therefore inverter 209 states that signal A is digital logic low high value, and inverter 210 states that signal AB is digital logic low.Note that in the form of Figure 10, the signal A of Q0 statusline is designated as Digital Logic " 1 ".Similarly, please note that signal AB is designated as Digital Logic " 0 ".
The voltage dragging down terminal 112, to reduce the source voltage of PFET M2, reduces the grid of PFETM2 to source voltage.So there is no make PFET M2 in Q2 state, have stronger conducting than it.Node N3 is digital logic low, and inverter 211 states that signal B is digital logic low high value, and inverter 212 states that signal BB is digital logic low.Note that in Figure 10 form, the signal B of Q0 statusline is designated as Digital Logic " 1 ".Similarly, please note that signal BB is designated as Digital Logic " 0 ".
Decoder 217 is decoded this situation, and signal A is wherein that Digital Logic is high and signal B is that Digital Logic is high, and states that status signal Q0 is that Digital Logic is high.With reference to Fig. 9, please note that the status signal control switch circuit 226(of Q0, Q1, Q2 is shown in Fig. 9).Because status signal Q0 is declared, so switching circuit 226 connects Q0 switch be input to switch output.Switch input Q0 is connected to the current source 230 of 100 microamperes.Therefore this electric current of 100 microamperes is drawn to flow through switching circuit 226.Due to resistance 227,229, the effect of amplifier 228 and PFET 231, electric current I BATT is 1,000 times of the electric current flowing through current source 230.Therefore, in state Q0, the electric current I BATT flowing through wire 201 is 100 milliamperes.
state Q1:
If terminal 112(T1) be shorted to digital logic high voltage VIN(5.0 volt) or be connected on VIN wire 114 by relatively low impedance, so the voltage of terminal 112 will be driven high voltage VIN.The voltage of terminal 112 is source voltages of PFET M2.Therefore the voltage increased in terminal 112 realizes increasing the voltage of source electrode to grid of transistor M2, is biased on a fixing direct voltage because the grid of transistor M2 is biased network 218.The more electric current of transistor M2 conduction ratio electric current I 2.Therefore, the voltage transition of node N3 is to digital logic high voltage.Inverter 211 states that signal B is digital logic low, and inverter 212 states that signal BB is digital high.Note that in the form of Figure 10, the signal BB display of that row middle is declared as Digital Logic " 1 ".
If the voltage of terminal 112 is driven high voltage VIN, so reduce the grid of transistor M1 to source voltage.Transistor M1 is the more electric current of conduction ratio electric current I 1 no longer.Voltage on node N2 is digital logic high voltage.Signal A has digital logic low, and signal AB has digital logic low high value.Note that in the form of Figure 10, middle that row signal AB display is declared as Digital Logic " 0 ".
Decoder 217 is decoded this situation, and wherein signal AB is that Digital Logic is high and signal BB is that Digital Logic is high, and states that status signal Q1 is digital logic low high value.Referring again to Fig. 9, signal Q1 control switch circuit 226, so that the switch that switch input Q1 is connected to it by switching circuit 226 exports.The current source 232 of 500 microamperes attaches to the switch input of Q1, therefore, makes the current flowing resistance 227 of 500 microamperes.This electric current is exaggerated device 229 and PFET231 amplifies, and thus electric current I BATT is the multiple of 500 muA.In the example of figure 9, this multiple is 1,000 times.Therefore, the electric current of 500 milliamperes flows through multiplexer and logic 202, and flows out VBATT terminal 203, charges to battery 108.Therefore, in state Q1, the electric current flowing through wire 201 is 500 milliamperes.
If circuit 200 operates in state Q0, wherein terminal 112 is shorted to other voltage of a DC potential by low-down external impedance, instead of 1.2 volts, and if current source circuit 219 is in work, so attempt drives the voltage of terminal 112 to 1.2 volts by current source circuit 219.As mentioned above, the work of differential amplifier 220 with the voltage of the in-phase input end with inverting input that keep it at identical electromotive force.In the case, due to low-down external impedance, electric current I 4 may be a big current exceeding to expect, it may cause and damages or waste unacceptable a large amount of power consumption in integrated circuit 109.Therefore, the size of a less W and larger L got by transistor 221, so transistor 221 is when its grid to source voltage is VIN, has the maximum current ducting capacity that little.This will be set to the maximum of electric current I 4 level (as a milliampere) that can not cause damaging circuit.
In addition, the RC timing circuit that comprises resistance 234 and electric capacity 235 is provided.When circuit 200 powers on, if circuit 200 is arranged on state Q0, so initial firing current source circuit 219.The enable input EN of differential amplifier will be high for Digital Logic.But the very low-impedance outside between terminal 112 to earth potential connects can the larger electric current of conducting by conduction ratio transistor 221, so circuit 200 will detect state Q0 rightly.Therefore decoder 217 will state that signal Q0B is signal digital logic low.Signal Q0B receives on RC circuit, so after the time delay of a short time, the enable input EN of differential amplifier 220 will be declared as low, thus stops current source circuit 219.Therefore, entering the beginning of Q0 state, the big current situation that electric current I 4 flows electric current is the moment situation of a short time.Circuit 200 in Q0 state, in normal work period subsequently, stops current source circuit 219.
When circuit 200 powers on, circuit 200 does not also detect that terminal 112 connects low, connects high or at vacant state.If the resistance 115 of outside high value is connected between terminal 115 and ground, and if there is no firing current source circuit 219, so just may there is no enough electric currents being derived from terminal 112 to improve the voltage of terminal 112.If the voltage in this situation and in terminal 112 maintains earth potential, so circuit 200 is the state being operated in Q0 instead of Q2 by detecting.Circuit 200 is died from this kind detect in the situation of state Q0, because do not have enough electric currents being derived from terminal 112 to improve the voltage of terminal 112 by being fallen into.But, in circuit 200, when powering on, firing current source circuit 219.Under initial electrifying condition, current source circuit 219 rises the voltage of terminal 112, therefore avoids circuit 200 and falls into and die from Q0 state.
What non-essential resistance 115 can have still cause circuit 200 to detect is operated in the minimum resistance of state Q2, can by determining as the emulation of SPICE or by the experiment of the actual realization of circuit with circuit emulator.The most high value being connected to earth potential (between terminal 112 and ground wire 113) of state Q0 will be detected as by circuit 200, and state Q2(will be detected as by circuit 200 between terminal 112 and ground wire 113) minimum resistance between provide a surplus.
general applicability
Described above is a kind of testing circuit and method, whether it detects has one end to be: 1) connect low (state Q0) by short circuit or by relatively low external impedance, 2) height (state Q1) is connect by short circuit or by relatively low external impedance, or 3) unsettled or be connected on a direct voltage (state Q2) by relatively high external impedance.Electric circuit inspection terminal is wherein which the state in these states, and makes response, exports the digital signal indicating the state detected.If the state detected is state Q2, so the operation characteristic of circuit altering section parallel circuit, so operation characteristic has an amplitude or numerical value, this amplitude or numerical value are the predetermined functions of resistance of relatively high external impedance.Perhaps, operation characteristic is the magnitude of current be connected with electric current I BATT as described above, or perhaps operation characteristic is in other embodiments a magnitude of voltage, frequency values, capacitance, inductance value, filter characteristic, or time, temperature, or arrange, or other operation characteristic.This circuit and method achieve detection three kinds of states and arrange the function of operation characteristic when there is no use second terminal.We admit, analog to digital converter can be used for detecting one of them of the many discrete voltage level of voltage that input terminal receives, or detect one of them of many discrete ranges of measured parameter; But the circuit of above-described Fig. 8 and Fig. 9 is more simply too much than increase multidigit analog to digital converter.Multidigit analog to digital converter requires that user provides the digital to analog converter of an equal resolution and precision to drive terminal 112 in integrated circuits usually.In the USB battery charger example of Fig. 4, novel USB integrated circuit of battery charger 109 has five terminals, and by comparison, USB charger system traditional in Fig. 1 has six terminals.This is one and is particularly suitable for novel circuit and the application-specific of method.
Although for purposes of illustration, combine some specific embodiments to describe the present invention, the present invention is not limited thereto.Figure 11 is to the another kind of biasing networks of the gate bias of transistor M1 and M2 of the circuit 200 of Fig. 8 and 9.Figure 12 is the schematic diagram of alternative method, this alternative method can be connected on novel USB integrated circuit of battery charger 109 USB integrated circuit (the USB integrated circuit 105 as in Fig. 4), wherein " GPIOA " refers to that universal input exports A, " GPIOB " refers to that universal input exports B, and " L " be low level, " H " be high level, " HI-Z " is high impedance, " R " is resistance.Therefore, the combination of the various modification of described embodiment, improvement and multifrequency nature can try out and not exceed scope of the present invention set forth in the claims.
Claims (4)
1. a method for multi-functional input, is characterized in that, it comprises:
A () determines whether ic terminal is shorted on the source of digital logic high voltage, or whether terminal is shorted on the source of digital logic low voltage, or whether terminal is unsettled or is connected to by relatively high impedance on the source of a DC potential, wherein the decision of (a) is made by the internal circuit of integrated circuit, and terminal is a part for this integrated circuit;
If b () (a) determines that the terminal of integrated circuit is shorted on the source of digital logic high voltage, statement first digit logical signal;
If c () (a) determines that the terminal of integrated circuit is shorted on the source of digital logic low voltage, statement second digit logical signal;
If the terminal of d integrated circuit that () (a) determines is unsettled or is connected to by relatively high impedance on the source of a DC potential, statement third digit logical signal, the statement wherein in above-mentioned (b), (c) and (d) is realized by the internal circuit of integrated circuit; And
If the terminal of e integrated circuit that () (a) determines is connected on the source of a DC potential by relatively high impedance, an electric current adjusted is provided, the amplitude of the electric current wherein adjusted is determined by the resistance of the non-essential resistance being connected to ic terminal, and wherein non-essential resistance is the outside at integrated circuit.
2. the method for multi-functional input according to claim 1, it is characterized in that, wherein the source of digital logic high voltage is the power voltage terminal of integrated circuit, and wherein the source of digital logic low voltage is the ground terminal of integrated circuit, and wherein the source of DC potential is the ground terminal of integrated circuit.
3. an integrated circuit, is characterized in that, it comprises:
A terminal; With
Component, to determine: whether (a) terminal is connected on the source of digital logic high voltage at integrated circuit external by short circuit or relatively low impedance, or whether (b) terminal is connected on the source of digital logic low voltage at integrated circuit external by short circuit or relatively low impedance, or whether (c) terminal is unsettled or is connected to by relatively high impedance on the source of a DC potential, if wherein component determines that (a) terminal is connected on the source of digital logic high voltage at integrated circuit external by short circuit or relatively low impedance, so component statement first digit logical signal, if wherein component determines that (b) terminal is connected on the source of digital logic low voltage at integrated circuit external by short circuit or relatively low impedance, so component statement second digit logical signal, if wherein component determines that (c) terminal is unsettled or is connected to by relatively high impedance on the source of a DC potential, so component statement third digit logical signal.
4. integrated circuit according to claim 3, it is characterized in that, if wherein component determines that (c) terminal is connected on the source of a DC potential by relatively high impedance, so component also provides an electric current adjusted, the amplitude of the electric current wherein adjusted depends on the resistance of the non-essential resistance being connected to terminal, and wherein non-essential resistance is the outside at integrated circuit.
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| CN201210236339.2A CN103001274B (en) | 2008-02-29 | 2008-02-29 | Multifunctional input terminal and method |
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| US6211649B1 (en) * | 1999-03-25 | 2001-04-03 | Sourcenext Corporation | USB cable and method for charging battery of external apparatus by using USB cable |
| US6362610B1 (en) * | 2001-08-14 | 2002-03-26 | Fu-I Yang | Universal USB power supply unit |
| CN1367564A (en) * | 2000-10-12 | 2002-09-04 | 索尼国际(欧洲)股份有限公司 | Charging circuit for charging mobile terminal by using USB interface |
| CN1574541A (en) * | 2003-06-11 | 2005-02-02 | 捷讯研究有限公司 | Universal serial bus (USB) charger for a mobile device |
| CN1967965A (en) * | 2005-11-17 | 2007-05-23 | 英华达(上海)电子有限公司 | Charging circuit of electron device with USB interface and method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6507172B2 (en) * | 2001-03-19 | 2003-01-14 | Maxim Integrated Products, Inc. | Universal serial bus powered battery charger |
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Patent Citations (5)
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|---|---|---|---|---|
| US6211649B1 (en) * | 1999-03-25 | 2001-04-03 | Sourcenext Corporation | USB cable and method for charging battery of external apparatus by using USB cable |
| CN1367564A (en) * | 2000-10-12 | 2002-09-04 | 索尼国际(欧洲)股份有限公司 | Charging circuit for charging mobile terminal by using USB interface |
| US6362610B1 (en) * | 2001-08-14 | 2002-03-26 | Fu-I Yang | Universal USB power supply unit |
| CN1574541A (en) * | 2003-06-11 | 2005-02-02 | 捷讯研究有限公司 | Universal serial bus (USB) charger for a mobile device |
| CN1967965A (en) * | 2005-11-17 | 2007-05-23 | 英华达(上海)电子有限公司 | Charging circuit of electron device with USB interface and method thereof |
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