CN103001274A - Multifunctional input terminal and method - Google Patents
Multifunctional input terminal and method Download PDFInfo
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- CN103001274A CN103001274A CN2012102363392A CN201210236339A CN103001274A CN 103001274 A CN103001274 A CN 103001274A CN 2012102363392 A CN2012102363392 A CN 2012102363392A CN 201210236339 A CN201210236339 A CN 201210236339A CN 103001274 A CN103001274 A CN 103001274A
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Abstract
The invention discloses a multifunctional input terminal and a method. An integrated circuit can be set to be in a state Q0, a state Q1 or a state Q2 by the single terminal. A circuit of the integrated circuit is connected to the terminal and determines whether the terminal is connected at a low position through an external connector or not, whether the terminal is connected at a high position through the external connector or not, or whether the terminal is suspended or suspended basically. If the terminal is determined to be suspended or suspended basically, then part of running characteristics of the circuit is set to have a value (for example, the maximum current IBATT of the circuit for charging batteries is set), the value is an external resistance connected to the terminal and is determined by a set function value, and accordingly users of the integrated circuit can set the value of the running characteristics as needed by selecting a moderate external resistance. If the external resistance does not exist, the terminal is suspended, and the running characteristic of the circuit is set to be null. In typical application, the null indicates a stop state of the circuit.
Description
The application is to be 200810034084.5 by the original applying number of submitting on February 29th, 2008, and name is called Multifunctional input terminal and method is divided an application.Simultaneously, the application requires to enjoy the rights and interests of the Chinese patent application submitted on February 29th, 2008 numbers 200810034084.5, is incorporated herein its full content as a reference.
Technical field
The present invention relates to a kind of terminal that relates to integrated circuit, its terminal is used for receiving configuration information, and the circuit on the collocating integrate circuit relates in particular to Multifunctional input terminal and method.
Background technology
Fig. 1 (prior art) is that a kind of to be connected to usb host 3(by USB cable 2 be PC in this example) on USB device 1(be mobile phone in this example) block diagram.Usb host 3 comprises USB circuit 4.USB device 1 comprises USB circuit 5.USB cable 2 has the USB plug 6 of a standard, inserts the adaptive USB port 7 on the usb host 3, and therefore, usb host can read and write USB circuit 5 in the USB device 1 by two data wire D+ on the USB cable 2 and D-.USB cable 2 also provides a supply voltage power conductor VIN and a ground wire GND.These wires can be used to the circuit supply to usb host 3 outsides.USB port 7 is defined between its wire VIN and the ground GND 5.0 volts voltage is provided.But according to configuration, usb host 3 may provide maximum 100 milliamperes source current or maximum 500 milliamperes source current.
In illustrated system, again give the chargeable lithium ion battery in the mobile phone 18 chargings with usb host 3 and USB port 7.Therefore, mobile phone 1 comprises the integrated circuit of battery charger 9 that is connected to USB circuit 5.Integrated circuit of battery charger 9 is also connected on the VIN and GND wire of illustrated USB cable 2.Charger integrated circuit 9 receives the electric energy from flow through supply voltage wire VIN and the ground wire GND of USB cable 2, then recharges to battery 8 with this electric energy.
Fig. 2 has analyzed the form of charging.Filling the stage soon of first, integrated circuit of battery charger 9 charges to battery 8 with constant current I-CONST.Then, in case cell voltage VBATT reaches predefined voltage V-CONST, integrated circuit of battery charger 9 will switch to the constant voltage charge pattern.This constant voltage charge pattern also is referred to as " finishing (the top-off) " stage sometimes.The charger integrated circuit has passed to battery to energy under the pattern of this constant voltage charge, so that cell voltage VBATT has had the predefined time interval to maintain predefined charging scope, afterwards, integrated circuit of battery charger 9 will stop to provide energy to battery 8.Vertical line 13 explanation this point among Fig. 2.
Set forth by top, USB port 7 may only can provide 100 milliamperes source current, and 500 milliamperes source current perhaps may be able to be provided.Filling the stage soon, expectation is charged to battery 8 with larger constant current, if USB port can provide larger charging current.Therefore, if USB port 7 can provide the source current of 500 milliamperes flow through VIN and GND wire, so in the constant current charge stage, the charger integrated circuit will be with 500 milliamperes current charges.The information of source current amount that USB circuit 4 in the usb host 3 can be exported to the expression main frame its USB port 7 is written to the USB circuit 5 in the mobile phone 1.Then, USB circuit 5 offers integrated circuit of battery charger 9 to this information with the form of digital logic signal.If it is the first digit logical value that USB circuit 5 drives these digital logic signals, so, USB can export a maximum (such as, 100 milliamperes) electric current; But, be the second digit logical value if USB circuit 5 drives these digital logic signals, so, USB can export another maximum (such as, 500 milliamperes) electric current.Integrated circuit of battery charger 9 receives this signal in first terminal (T1) 11.
Usb host 3(in this case example is PC here) can also open or stop the battery charging.USB circuit 4 in the main frame 3 is written to USB circuit 5 in the mobile phone 1 to an information bit.This information bit indication charger is unlatching or stops.Then, this information bit passes on the integrated circuit of battery charger 9 from USB circuit 5 with the form of second digit logical signal.Integrated circuit of battery charger 9 receives this second digit logical signal in second terminal (T2) 12.Therefore, integrated circuit of battery charger 9 has two terminals 11 and 12, to receive the configuration information from USB circuit 5.
Fig. 3 has illustrated the digital logic value of first and second digit logical signal on terminal T1 and T2, and the corresponding situation of integrated circuit of battery charger 9 that shows configuration.In a distortion of the traditional USB battery charger of Fig. 1, an extra non-essential resistance can be connected between first terminal T1 and the earth potential.In some configurations, the amplitude of the resistance set with constant current of this outside resistance, under constant current mode, this constant current of integrated circuit of battery charger 9 usefulness is to battery 8 chargings.Such as, if the signal that terminal T2 receives is that Digital Logic is low, charger stops so; Otherwise, according to Fig. 2, charger the charging quickly stage with a constant current charges, wherein constant electric current is determined by the resistance that is connected to the non-essential resistance on the terminal T1.According to specific traditional circuit, terminal T1 may or may not be connected to a terminal of USB circuit 5.Need like this improvement traditional batter-charghing system described above.
Summary of the invention
Technical problem to be solved by this invention provides a kind of Multifunctional input terminal and method, and it can realize multi-functional input, and then has reduced terminal number, thereby has reduced the manufacturing cost of USB device.
In order to solve above technical problem, the invention provides a kind of Multifunctional input terminal.Wherein single terminal can be used to arrange integrated circuit and enters three-state (state Q0, state Q1 or state Q2).Circuit in the integrated circuit is connected to this terminal, and determines this terminal is whether: 1) be connected into by the outside low, 2) be connected into height, 3 by the outside) unsettled or basically unsettled.If it is unsettled or basically unsettled that circuit is determined this terminal, so, the part operation characteristic that circuit will arrange circuit (for example, the maximum current IBATT that circuit charges the battery is set) have a value, this value be the non-essential resistance resistance that is connected to terminal be come by a functional value that arranges fixed.Therefore, the integrated circuit user can arrange by the non-essential resistance of selecting suitable resistance operation characteristic and has a value of wanting.If non-essential resistance does not exist, terminal is unsettled so, and the circuit setting has the operation characteristic of the null value of corresponding to.In the typical case used, null value corresponded to halted state.
In addition, the present invention also provides a kind of method that realizes multi-functional input, the method may further comprise the steps: determine (a) whether ic terminal is shorted on the source of digital logic high voltage, perhaps whether terminal is shorted on the source of digital logic low voltage, perhaps terminal is whether unsettled or be connected to by relatively high impedance on the source of a DC potential, wherein the decision of (a) is to be made by the internal circuit of integrated circuit, and terminal is the part of this integrated circuit; (b) statement first digit logical signal is to be shorted on the source of digital logic high voltage if (a) determine the terminal of integrated circuit; (c) statement second digit logical signal is to be shorted on the source of digital logic low voltage if (a) determine the terminal of integrated circuit; (d) statement third digit logical signal, if (a) terminal of definite integrated circuit is unsettled or is connected to by relatively high impedance on the source of a DC potential, wherein above-mentioned (b), (c) and (d) in statement be to be realized by the internal circuit of integrated circuit; And (e) provide the electric current of an adjustment, if (a) terminal of definite integrated circuit is unsettled or is connected to by relatively high impedance on the source of a DC potential, the amplitude of the electric current of wherein adjusting is that the resistance by the non-essential resistance that is connected to ic terminal determines that wherein non-essential resistance is the outside at integrated circuit.
The above-mentioned terminal of the present invention and circuit and method are particularly suitable for being used on the USB battery charger.In many application, use terminal of the present invention and circuit and method, allow the terminal number of USB integrated circuit of battery charger to reduce one.The minimizing of terminal number has reduced the manufacturing cost of the USB device (such as mobile phone) of using this USB integrated circuit of battery charger.
Description of drawings
Below in conjunction with the drawings and specific embodiments the present invention is described in further detail.
Fig. 1 is the schematic diagram that is used in the tradition six terminal USB integrated circuit of battery charger on the mobile phone in the prior art.
Fig. 2 be among Fig. 1 traditional USB integrated circuit of battery charger how to the charging of the rechargeable battery on the mobile phone among Fig. 1 schematic diagram.
Fig. 3 analyzes how digital signal arranges the USB integrated circuit of battery charger in two terminals of the traditional USB integrated circuit of battery charger of Fig. 1 form.
Fig. 4 is the schematic diagram of system 100 of the present invention, and according to the aspect of a novelty, this system comprises novel USB integrated circuit of battery charger 109.
Fig. 5 is that novel USB integrated circuit of battery charger 109 among Fig. 4 is how to the schematic diagram of rechargeable battery 108 chargings on the mobile phone 101 among Fig. 4.
Fig. 6 is a form, and it has analyzed the single terminal 112(T1 of novel USB integrated circuit of battery charger 109) how to dispose one of them that USB integrated circuit of battery charger 109 enters three kinds of states.
Fig. 7 is a form, and it illustrates five terminals and the function corresponding to terminal of USB integrated circuit of battery charger 109 among Fig. 4.
Fig. 8 and 9 forms the circuit diagram of a circuit 200 in USB integrated circuit of battery charger 109 together.Circuit 200 detects the wherein state (Q0, Q1, Q2) of integrated circuit 109 configurations.
Figure 10 is a form, and it illustrates three kinds of states of circuit 200 operations in Fig. 8 and 9.It has also illustrated the corresponding function that USB integrated circuit of battery charger 109 is realized under each state of three kinds of states.
Figure 11 is the alternative biasing networks that the grid voltage to transistor M1 and M2 of circuit 200 is setovered in Fig. 8 and 9.
Figure 12 is the schematic diagram of alternative method, and this alternative method can be connected to USB integrated circuit (such as the USB integrated circuit 105 among Fig. 4) on the novel USB integrated circuit of battery charger 109.
Embodiment
" member " of indication of the present invention refers to have components and parts or the circuit that certain function maybe can realize certain function, such as specifically referring to circuit 200(Fig. 8 among the embodiment below) etc.In addition, " the supply voltage terminal " of indication of the present invention refers to input voltage terminal 205(Fig. 8 in the present embodiment), " Digital Logical Circuits " of indication of the present invention refers to inverter 209(Fig. 8 in the present embodiment), " second Digital Logical Circuits " of indication of the present invention refers to inverter 211(Fig. 8 in the present embodiment), " the digital decoding circuit " of indication of the present invention refers to digital decoder 217(Fig. 8 in the present embodiment), " programmable current source " of indication of the present invention refers to current source circuit 219(Fig. 8 in the present embodiment).Above-mentioned corresponding relation only is in order better to explain further and illustrate concrete application of the present invention, and should not be considered as limitation of the present invention.
Fig. 4 is the schematic diagram of system 100 of the present invention, this system 100 comprise to be connected in this example of usb host 103(by USB cable 102 be PC) this example of USB device 101(in be mobile phone).Usb host 103 comprises USB circuit 104.USB device 101 comprises USB circuit 105.USB cable 102 has the USB plug 106 of a standard, inserts the adaptive USB port 107 on the usb host 103, and therefore, usb host 103 can read and write USB circuit 105 in the USB device 101 by two data wire D+ on the USB cable 102 and D-.USB cable 102 also provides a supply voltage power conductor VIN and a ground wire GND.These wires can be used to the circuit supply to usb host 103 outsides.USB port 107 is defined between its wire VIN and the ground GND 5.0 volts voltage is provided.But according to configuration, usb host may provide maximum 100 milliamperes source current or maximum 500 milliamperes source current.
In illustrated system, again give the chargeable lithium ion battery in the mobile phone 101 108 chargings with usb host 103 and USB port 107.Square frame 101A is the local expansion figure of mobile phone 101.Square frame 101A comprises novel integrated circuit of battery charger 109, and it is connected on the USB circuit 105 with novel manner.As scheme to illustrate that integrated circuit of battery charger 109 is also connected on the wire VIN and GND of USB cable 102.Charger integrated circuit 109 receives the electric energy from flow through supply voltage wire VIN and the ground wire GND of USB cable 102, then recharges to battery 108 with these electric energy.
Fig. 5 has analyzed the form of charging.Filling the stage soon of first, integrated circuit of battery charger 109 charges to battery 108 with constant current I-CONST.Then, in case cell voltage VBATT reaches predefined voltage V-CONST, mains charger integrated circuit 109 will switch to the constant voltage charge pattern.This constant voltage charge pattern also is referred to as " finishing (the top-off) " stage sometimes.Charger integrated circuit 109 has passed to battery 108 to energy under the pattern of this constant voltage charge, so that cell voltage VBATT has had the predefined time interval to maintain predefined charging scope, afterwards, integrated circuit of battery charger 109 will stop to provide energy to battery 108.Vertical line 110 explanation this point among Fig. 5.
Set forth by top, USB port 107 may only can provide 100 milliamperes source current, and perhaps USB port 107 may be able to provide 500 milliamperes source currents.Filling the stage soon, expectation can be obtained maximum constant current to battery 108 chargings, if USB port can provide the charging current that increases quantity.Therefore, if USB port 107 can provide the source current of 500 milliamperes flow through VIN and GND wire, so in the constant current charge stage, charger integrated circuit 109 will be with 500 milliamperes current charges.The information of source current amount that USB circuit 104 in the usb host 103 can be exported to the expression main frame its USB port 107 is written to the USB circuit 105 in the mobile phone 101.Then, USB circuit 105 offers integrated circuit of battery charger 109 to this information with the form of signal that two digital logic level are arranged.If USB circuit 105 drives digital logic signal IN and wire 111 has the first digit logical value, so that terminal (T1) 112 is connected on the ground wire (GND wire) 113, so, the source current that provides of USB port 107 just has first maximum of 100 milliamperes; But if USB circuit 105 drives signal IN and wire 111 has the second digit logical value, so that terminal (T1) 112 is connected on the VIN wire 114, so, the source current that USB port 107 provides just has second 500 milliamperes maximum.Integrated circuit of battery charger 109 receives this IN signal in a kind of single terminal (T1) 112.
Usb host 103(in this example is PC here) can also make charger integrated circuit 109 with constant current, exactly be " user " selected value, give battery 108 chargings.The term here " user " typically refers to " user " of mobile phone manufacturer or USB integrated circuit of battery charger 109, and they buy this integrated circuit, and they are installed on product such as the mobile phone 101.It is to be determined by the resistance that is connected to the non-essential resistance 115 on the terminal T1 that charger integrated circuit 109 is given the constant current of battery 108 chargings.Non-essential resistance 115 is the outsides at charger integrated circuit 109.Although in a particular embodiment, usb host 103 can not as the example of prior art among Fig. 1 to 3, stop charger integrated circuit 109, still, charger integrated circuit 109 has terminal number still less, and charger integrated circuit 109 is communicated by letter with USB circuit 105 by these terminals.
Fig. 6 is the function of explanation USB integrated circuit of battery charger 109 or the form of configuration.If being " connecing low " or other, terminal T1 is connected to digital logic low voltage on the GND wire 113 through short circuit or relatively low impedance, so signal IN is referred to as at the low state " 0 " of Digital Logic.Charger integrated circuit 109 detects this " 0 " state and the maximum that arranges to the constant current of battery 108 chargings is 100 milliamperes.If being " connecing height " or other, terminal T1 is connected to digital logic high voltage on the VIN wire 114 through short circuit or relatively low impedance, so signal IN is referred to as in Digital Logic high state " 1 ".Charger integrated circuit 109 detects this one state and the maximum that arranges to the constant current of battery 108 chargings is 500 milliamperes.If terminal T1 does not have " connecing height " or " connecing low ", in the specific embodiment of Fig. 4, terminal T1 receives on the earth potential with the non-essential resistance 115 of relatively large resistance so.The state of this high impedance represents with " R " in the form of Fig. 6.Charger integrated circuit 109 detects this " R " state and the maximum that arranges to the constant current of battery 108 chargings is a current value, and this current value is that a predetermined function of the resistance of non-essential resistance 105 decides.
Fig. 7 is the form of illustrating the terminal of USB integrated circuit of battery charger 109.Notice five terminals are arranged here, in conjunction with Fig. 8,9, can find out that they are respectively IN (terminal) 112, CHAGER FINISH (charging is finished) terminal 116, the charging of VBATT(battery) terminal 203, GND () terminal 204 and VIN (input voltage) terminal 205, they in contrast among Fig. 1 traditional USB integrated circuit of battery charger six terminals are arranged.After battery charging process was finished among Fig. 5, integrated circuit of battery charger 109 was finished the terminal 116 drive currents light-emitting diode (LED) 117 of flowing through from charging, thereby sends the charged indication of a visible battery 108.Another is chosen as, and make light-emitting diode (LED) 117 luminous in battery 108 charging processes, and LED117 is not luminous when charging is finished.
Fig. 8 and 9 forms a circuit diagram together, the circuit diagram of a new circuit 200 in USB integrated circuit of battery charger 109.Whether circuit 200 is determined: 1) terminal 112(T1) be connected on the GND wire 113 by relatively low impedance in the outside of integrated circuit 109 and (be referred to as state Q0), 2) terminal 112(T1) whether be connected on the VIN wire 114 by relatively low impedance in the outside of integrated circuit 109 and (be referred to as state Q1), 3) terminal 112(T1) whether unsettled or be connected to a direct voltage source in the outside of integrated circuit 109 by relatively high impedance, as (being referred to as state Q2) on the GND wire 113.
If circuit 200 is determined terminal 112(T1) be at state Q0, circuit 200 provides electric current I BATT by wire 201 so.In the present embodiment, in the constant current quick charge stage of battery charging, electric current I BATT flow through logic and multiplexer 202 and VBATT terminal 203 are fed to battery 108.In state Q0, the amplitude of this electric current is 100 milliamperes.If circuit 200 is determined terminal 112(T1) be at state Q1, to provide amplitude by wire 201 be 500 milliamperes IBATT electric current to circuit 200 so.If circuit 200 is determined terminal 112(T1) be at state Q2, to provide amplitude by wire 201 be (12 * 10 to circuit 200 so
6/ R) milliampere IBATT electric current, wherein R unit is ohm.R is the resistance of non-essential resistance 115.Figure 10 has illustrated circuit 200 at Q0, Q1, the function under every kind of state of Q2 state.
The below sets forth the running of the circuit 200 among Fig. 8 and 9.
State Q2:
For purposes of illustration, suppose terminal 112(T1) be unsettled and be not connected with other node fully.Suppose not exist resistance 115.N slot field-effect transistor (NFET) M1 and P-channel field-effect transistor (PEFT) transistor (PFET) M2 only are biased in lightly conducting in this case.NFET M1 is biased in conducting less than the electric current of electric current I 1.Current source 206 is nonideal current sources, and node N2 is drawn high to voltage VIN.The voltage VIN of node N2 is digital logic high voltage.It is digital logic low that Digital Logic inverter 209 detects this situation statement signal A.Then inverter 210 statement signal AB are the high value of Digital Logic (" B " here is the anti-of representative " resistance barrier (bar) " or signal A).Note that in the form of Figure 10 the signal A of state Q2 is appointed as digital " 0 ", signal AB is appointed as numeral " 1 ".
Similarly, PFET M2 is biased in conducting less than the electric current of electric current I 2.Therefore current source 207 is pulled low to node N3 the earth potential of ground terminal 204.The voltage of node N3 is digital logic low voltage.Therefore, inverter 212 statement signal BB are digital logic low.Note that in the form of Figure 10 the signal B of state Q2 is appointed as numeral " 1 ", signal BB is appointed as digital " 0 ".
Form digital decoder 217 with door 213-215 and inverter 216.Decoder 217 detection signal AB are claimed as height and signal B is claimed as height, and output signal Q2 is the high situation of Digital Logic.Other state output signal Q0 and Q1 are not claimed as height.Note that in the form of Figure 10 the signal Q2 of state Q2 is digital logic high levels, but signal Q0 and Q1 are digital logic low levels.
The gate bias that biasing networks 218 is given transistor M1 and M2 makes transistor M1 and M2 in the lightly conducting pattern.Transistor M3 is connected with M4 that each is that diode connects, so the electromotive force between the grid of transistor M1 and M2 is approximately the voltage drop of two forward biased diodes.This is biased in voltage drop between the grid of transistor M1 and M2 and is approximately two threshold voltages, and therefore, transistor M1 and M2 only are lightly conducting.Voltage drop unit 218A with node N4 be arranged on one above Ground electromotive force but be optional dc offset voltage.Such as, voltage drop unit 218A may be a resistance of suitable value, the voltage that node N4 is set is 0.5 volt.Current source 208 provides flow through the transistor M3 of diode connection and the electric current of M4, sets up the voltage drop through transistor M3 and M4, so that gate bias voltage between node N1 and the N4 to be set.
Yet, in the example of Fig. 4 to 10, with non-essential resistance 115 at terminal 112(T1) and GND terminal 204 between set up a relative high impedance connection.This resistance is enough high, so that can not drag down the source electrode of NFET M1, so NFET M1 draws the electric current same with I1.In addition, when the maximum current that the electric current of needs allows less than current source circuit 219, current source circuit 219 is kept the voltage of terminal 112 at 1.2 volts.Therefore, the electric current that NFET M1 draws is less than electric current I 1, and node N2 remains on the state that Digital Logic height and decoder 217 continue to detect Q2.
Such as Fig. 9 explanation, current IS ET2 is the mirror image of the NFET current mirror by comprising N channel transistor 224 and 225 again.It is the current IS ET triple channel switching circuit 226 of flowing through as a result.Switching circuit 226 is subject to the control of digital state signal Q0, Q1, Q2, and therefore, when Q2 is claimed as when high, switching circuit 226 connects its Q2 switching nodes to its output node.Because the in-phase input end of differential amplifier 228 is inputs of high impedance, institute is so that current IS ET flows through resistance 227.The work of differential amplifier 228 makes the voltage of its in-phase input end and inverting input almost completely equal.Therefore, make the voltage drop on the resistance 227 the same with the voltage drop on the resistance 229.Be an one thousandth of the resistance of resistance 227 by the resistance that makes resistance 229, making electric current I BATT is 1,000 times of current IS ET.Electric current I BATT flow through wire 201, logic and switching circuit 202, and flow out VBATT terminal 203, give above-mentioned battery 108 chargings.The current amplitude of this milliampere magnitude is approximately 12 * 10
6Divided by R, wherein R is the resistance of non-essential resistance 115.
If it is unsettled not having resistance or other circuit and terminal 112 here, be connected to terminal 112(T1 but not have) and the non-essential resistance 115 of ground between the terminal 204.So, there is not electric current can flow out terminal 112.Under this kind configuration, current source circuit 219 does not conduct the electric current through NFET 221, and electric current I 4 is zero, and the electric current I BATT of wire 201 also is zero.This is " not charging " or " stopping " state that stops the battery charging.In the specific embodiment of Fig. 4, provide usb host 103 that the ability that stops to charge is arranged, require not have non-essential resistance 115.Therefore, the electric current I BATT that does not have the client to set.In state Q2, IBATT is zero.Here suppose that amplifier 220 is ideal circuit of zero imbalance, and mate well between nonideal current source I1 and the I2.Any because offset error or the mismatch between I1 and the I2 that the input offset voltage of amplifier 220 causes will be exaggerated 10,000 times, then output to VBATT terminal 203 and charge the battery.Additional circuit, Fig. 8 and not illustrating detects minimum current value, when detecting ISET2＜IMIN, makes IBATT=0.
As shown in Figure 9, provide a charging to finish testing circuit 233.After the charge cycle among Fig. 5 was finished, testing circuit 233 driving LED 117 were finished in charging, come pilot cell 108 charged with this.Another is chosen as, and charging completing circuit 233 stops driving LED 117 and no longer carries out with the expression charging.
State Q0:
If terminal 112(T1) with short circuit or relatively low impedance be shorted to ground wire 113 on or be connected to ground wire 113 on, the voltage on the terminal 112 drags down from the due voltage of state Q2 so.The voltage of terminal 112 is exactly the source voltage of NFET M1.Therefore the voltage that reduces on the terminal 112 realizes increasing the source electrode of transistor M1 to the voltage of grid, because the grid of transistor M1 is biased in a fixing direct voltage.Along with the reduction of voltage on the terminal 112, the conducting that therefore transistor M1 also becomes more and more stronger is until the electric current I 1 more electric current of transistor M1 conduction ratio current source 206.In this point, the voltage of node N2 is pulled down to digital logic low voltage.Therefore inverter 209 states that signal A is the high value of Digital Logic, and inverter 210 statement signal AB are digital logic low.Note that in the form of Figure 10 the signal A of Q0 statusline is designated as Digital Logic " 1 ".Similarly, please note that signal AB is designated as Digital Logic " 0 ".
The voltage that drags down terminal 112 reduces the source voltage of PFET M2, has reduced the grid of PFETM2 to source voltage.Therefore do not make PFET M2 than it stronger conducting be arranged in the Q2 state.Node N3 is digital logic low, and inverter 211 statement signal B are the high value of Digital Logic, and inverter 212 statement signal BB are digital logic low.Note that in Figure 10 form the signal B of Q0 statusline is designated as Digital Logic " 1 ".Similarly, please note that signal BB is designated as Digital Logic " 0 ".
State Q1:
If terminal 112(T1) be shorted to digital logic high voltage VIN(5.0 volt) or be connected on the VIN wire 114 by relatively low impedance, the voltage of terminal 112 will be drawn high voltage VIN so.The voltage of terminal 112 is source voltages of PFET M2.Therefore the voltage that increases on the terminal 112 realizes increasing the source electrode of transistor M2 to the voltage of grid, is biased on the fixing direct voltage because the grid of transistor M2 is biased network 218.Transistor M2 conduction ratio electric current I 2 more electric currents.Therefore, the voltage transition of node N3 is to digital logic high voltage.Inverter 211 statement signal B are digital logic low, and inverter 212 statement signal BB are the high value of numeral.Note that in the form of Figure 10 the signal BB demonstration of middle that row is declared as Digital Logic " 1 ".
If the voltage of terminal 112 is drawn high voltage VIN, reduced so the grid of transistor M1 to source voltage.Transistor M1 is conduction ratio electric current I 1 more electric current no longer.Voltage on the node N2 is digital logic high voltage.Signal A has digital logic low, and signal AB has the high value of Digital Logic.Note that in the form of Figure 10 middle that row signal AB shows it is to be declared as Digital Logic " 0 ".
If circuit 200 operates in state Q0, wherein terminal 112 is shorted to other voltage of a DC potential by low-down external impedance, rather than 1.2 volts, and if current source circuit 219 work, so current source circuit 219 will attempt the driving terminal 112 voltage to 1.2 volts.As mentioned above, the work of differential amplifier 220 with the voltage of the in-phase input end that keeps it and inverting input at identical electromotive force.In the case, because low-down external impedance, electric current I 4 may be a large electric current that exceeds to expect, it may cause in integrated circuit 109 and damage or waste unacceptable a large amount of power consumption.Therefore, transistor 221 is got the size of a less W and larger L, so transistor 221 when its grid to source voltage is VIN, has a little maximum current ducting capacity.This will be set to a level (such as a milliampere) that can not cause damaging circuit to the maximum of electric current I 4.
In addition, provide a RC timing circuit that comprises resistance 234 and electric capacity 235.When circuit 200 powers on, if circuit 200 is arranged on state Q0, so initial firing current source circuit 219.The input EN that enables of differential amplifier will be high for Digital Logic.Yet, terminal 112 to very low-impedance outside between earth potential connect can conducting with conduction ratio transistor 221 larger electric current, so circuit 200 will detect state Q0 rightly.Therefore decoder 217 will state that signal Q0B is the signal digital logic low.Signal Q0B receives on the RC circuit, so after the time-delay of a short time, enabling input EN and will being declared as lowly of differential amplifier 220 thereby stops current source circuit 219.Therefore, in the beginning that enters the Q0 state, the moment situation that it is a short time that electric current I 4 is flowing the large electric current situation of electric current.Circuit 200 in the Q0 state stops current source circuit 219 in subsequently normal work period.
When circuit 200 powered on, it was to connect lowly that circuit 200 does not also detect terminal 112, connects high or at vacant state.If the resistance of outside high value 115 is connected between terminal 115 and the ground, and if do not have firing current source circuit 219, so just may there be enough electric currents that is derived from terminal 112 to improve the voltage of terminal 112.If the voltage on this situation and terminal 112 maintains earth potential, will to detect be the state that is operated in Q0 rather than Q2 to circuit 200 so.Circuit 200 will fall into to be died from the situation that this kind detect state Q0, because there are not enough electric currents that is derived from terminal 112 to improve the voltage of terminal 112.Yet, in the circuit 200, when powering on, firing current source circuit 219.Under initial electrifying condition, current source circuit 219 rises the voltage of terminal 112, has therefore avoided circuit 200 to fall into the Q0 state of dying from.
General applicability
The above has described a kind of testing circuit and method, whether its detection has an end to be: 1) meet low (state Q0) by short circuit or by relatively low external impedance, 2) connect height (state Q1) by short circuit or by relatively low external impedance, or 3) unsettled or be connected on (state Q2) on the direct voltage by relatively high external impedance.The electric circuit inspection terminal is wherein which the state at these states, and makes response, the digital signal of the state that the output indication detects.If the state that detects is state Q2, operation characteristic of circuit altering section parallel circuit so, so operation characteristic has an amplitude or numerical value, this amplitude or numerical value are the predetermined functions of resistance of relatively high external impedance.Perhaps, operation characteristic is a magnitude of current that links to each other with electric current I BATT as described above, and perhaps perhaps in other embodiments operation characteristic is a magnitude of voltage, frequency values, capacitance, inductance value, filter characteristic, or time, temperature perhaps arranges, perhaps other operation characteristic.Sort circuit and method have realized detecting three kinds of states and operation characteristic is set in the situation of not using second terminal function.We admit, analog to digital converter can be used for detecting one of them of many discrete voltage level of the voltage that input terminal receives, and perhaps detect one of them of many discrete ranges of measured parameter; But the circuit of above-described Fig. 8 and Fig. 9 is more simply too much than increasing a multidigit analog to digital converter.The multidigit analog to digital converter requires the user to provide the digital to analog converter of an equal resolution and precision to drive terminal 112 in integrated circuit usually.In the USB of Fig. 4 battery charger example, novel USB integrated circuit of battery charger 109 has five terminals, and by comparison, traditional USB charger system has six terminals among Fig. 1.This is one and is particularly suitable for novel circuit and the application-specific of method.
Although for purposes of illustration, combine some specific embodiments and describe the present invention,, the invention is not restricted to this.Figure 11 is the another kind of biasing networks to the gate bias of the transistor M1 of the circuit 200 of Fig. 8 and 9 and M2.Figure 12 is the schematic diagram of alternative method, this alternative method can be connected to USB integrated circuit (such as the USB integrated circuit 105 among Fig. 4) on the novel USB integrated circuit of battery charger 109, wherein " GPIOA " refers to universal input output A, " GPIOB " refers to universal input output B, and " L " is that low level, " H " are resistance for high level, " HI-Z " for high impedance, " R ".Therefore, the combination of various modification, improvement and the multifrequency nature of described embodiment can try out and not exceed the scope of the present invention of setting forth in the claims.
Claims (4)
1. method is characterized in that it comprises:
(a) determine whether ic terminal is shorted on the source of digital logic high voltage, perhaps whether terminal is shorted on the source of digital logic low voltage, perhaps terminal is whether unsettled or be connected to by relatively high impedance on the source of a DC potential, wherein the decision of (a) is to be made by the internal circuit of integrated circuit, and terminal is the part of this integrated circuit;
(b) statement first digit logical signal is to be shorted on the source of digital logic high voltage if (a) determine the terminal of integrated circuit;
(c) statement second digit logical signal is to be shorted on the source of digital logic low voltage if (a) determine the terminal of integrated circuit;
(d) statement third digit logical signal, if (a) terminal of definite integrated circuit is unsettled or is connected to by relatively high impedance on the source of a DC potential, wherein above-mentioned (b), (c) and (d) in statement be to be realized by the internal circuit of integrated circuit; And
(e) provide the electric current of an adjustment, if (a) terminal of definite integrated circuit is unsettled or is connected to by relatively high impedance on the source of a DC potential, the amplitude of the electric current of wherein adjusting is that the resistance by the non-essential resistance that is connected to ic terminal determines that wherein non-essential resistance is the outside at integrated circuit.
2. method according to claim 1, it is characterized in that, wherein the source of digital logic high voltage is the supply voltage terminal of integrated circuit, and wherein the source of digital logic low voltage is the ground terminal of integrated circuit, and wherein the source of DC potential is the ground terminal of integrated circuit.
3. integrated circuit is characterized in that it comprises:
A terminal; With
Member, to determine: (a) whether terminal is connected on the source of digital logic high voltage by short circuit or relatively low impedance in the integrated circuit outside, or (b) whether terminal is connected on the source of digital logic low voltage by short circuit or relatively low impedance in the integrated circuit outside, or (c) whether terminal be unsettled or be connected to by relatively high impedance on the source of a DC potential, if wherein member is determined (a), member is stated the first digit logical signal so, if wherein member is determined (b), member is stated the second digit logical signal so, if wherein member is determined (c), member is stated the third digit logical signal so.
4. integrated circuit according to claim 3, it is characterized in that if wherein member is determined (c), member also provides the electric current of an adjustment so, the amplitude of the electric current of wherein adjusting depends on the resistance of the non-essential resistance that is connected to terminal, and wherein non-essential resistance is the outside at integrated circuit.
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Cited By (1)
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| CN107769295A (en) * | 2016-08-22 | 2018-03-06 | 三星Sdi株式会社 | Method for charging batteries and use its battery charging equipment |
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| CN103001274B (en) | 2015-01-21 |
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