CN113777469A

CN113777469A - Circuit and method for detecting correct access of chip pin capacitance based on capacitance range

Info

Publication number: CN113777469A
Application number: CN202111005537.3A
Authority: CN
Inventors: 周华文
Original assignee: Shanghai Xinling Microelectronic Co ltd
Current assignee: Shanghai Xinling Microelectronic Co ltd
Priority date: 2021-08-30
Filing date: 2021-08-30
Publication date: 2021-12-10

Abstract

The present invention provides a circuit and method for detecting the correct access of chip pin capacitance based on the capacitance range, one end of a first switch tube of the circuit is connected with a first current source, the other end of the first switch tube is respectively connected with a first capacitor and a negative end of a second comparator, the other end of the first capacitor is grounded, one end of the second switch tube is connected with a second current source, the other end of the second switch tube is respectively connected with a second capacitor and a positive end of the first comparator, the other end of the second capacitor is grounded, one end of a third switch tube is connected with a third current source, the other end of the third switch tube is respectively connected with the negative end of the first comparator, the positive end of the second comparator, an output signal end of a chip and a chip pin capacitor, output ends of the first comparator and the second comparator are respectively connected with two input ends of an AND circuit, and an output end of the AND circuit is connected with an opening signal end of the chip. The invention can ensure that the chip can limit the work under the condition of abnormal pin connection, thereby avoiding the damage caused by abnormal work.

Description

Circuit and method for detecting correct access of chip pin capacitance based on capacitance range

Technical Field

The invention relates to the field of integrated circuits, in particular to a circuit and a method for detecting correct access of chip pin capacitance based on capacitance range.

Background

In a practical circuit, the capacitor plays a significant role in the circuit. Especially, the circuits of the input and output ports of the integrated circuit play a crucial role in determining whether the integrated circuit is working normally or whether the performance of the integrated circuit is good or bad.

The current integrated circuit technology can not integrate a large capacitor into a circuit, so that a capacitor is required to be connected to a plurality of pins to enable the circuit to work normally. There are circuits that avoid the use of excessive capacitance due to the speed of the transmitted signal or other requirements. The capacitor and the integrated circuit pin are connected through a PCB (printed circuit board). During the factory process, there is a possibility of some leakage, cold joint or short circuit with solder paste on the side capacitor.

In the prior art, for the detection of the abnormal access capacitance, the integrated circuit itself is not processed, but is checked at the board level or at the factory. The factory can only be checked visually, by X-ray inspection, or just before power-up. When the power is on, some circuits are damaged due to the fact that no pin capacitor causes overlarge chip current, overlarge voltage and the like. This time it is too late.

That is, in the current technology, the integrated circuit chip does not detect the capacitance of the pin (except for the circuit specially detecting the capacitive device), and directly starts the chip to work

Taking a middle LDO (low dropout linear rectifier) chip of a power chip as an example, the output capacitance of the middle LDO chip is very important for the stability of a loop. That is, the output capacitance value in a certain range plays an important role in whether the chip outputs stably. Without a grounding capacitor, the circuit is very likely to oscillate (loop instability). Once oscillation occurs, the output voltage is uncontrollable and the voltage amplitude may be large and may exceed the allowable range of the integrated circuit pin circuit. The rising edge and the falling edge of the pin voltage or current may be rapidly charged and discharged due to the absence of a capacitor, which may cause the other parts of the circuit to be triggered by mistake, especially may trigger an ESD (electrostatic protection) circuit, or may cause latch-up (latch up), which further causes the rapid charging and discharging of the circuit, and the chip may burn out after the voltage or the current or the temperature is increased to a certain limit. And part of circuits need external capacitors to control the soft start time, and if the pin capacitors are subjected to solder leakage or cold solder joint, the soft start is ineffectual, so that the whole system is electrified too fast, and the current and voltage impact is too large, thereby causing serious damage to the next-stage chip device or causing time sequence disorder.

In short, the prior art is that the integrated circuit itself can directly start to work regardless of whether the external part of the integrated circuit is connected with a capacitor or not.

Disclosure of Invention

The invention aims to: the circuit detects the capacitance of the pin end of the integrated circuit before the working output of the integrated circuit, and then starts the main circuit after detecting that the capacitance of the pin end can meet the capacitance of the integrated circuit which normally works.

The invention aims to be realized by the following technical scheme:

a circuit for detecting correct access of chip pin capacitance based on capacitance range comprises a first current source, a second current source, a third current source, a first switch tube, a second switch tube, a third switch tube, a first capacitor, a second capacitor, a first comparator, a second comparator and an AND gate circuit, wherein control signal ends of the first switch tube, the second switch tube and the third switch tube are connected, one end of the first switch tube is connected with the first current source, the other end of the first switch tube is respectively connected with a negative end of the first capacitor and a negative end of the second comparator, the other end of the first capacitor is grounded, one end of the second switch tube is connected with the second current source, the other end of the second switch tube is respectively connected with a positive end of the second capacitor and the first comparator, the other end of the second capacitor is grounded, one end of the third switch tube is connected with the third current source, and the other end of the third switch tube is respectively connected with a negative end of the first comparator, The output ends of the first comparator and the second comparator are respectively connected with two input ends of an AND circuit, and the output end of the AND circuit is connected with an opening signal end of the chip.

As a further technical solution, the first switch tube is one of PMOS, NMOS, NPN, and PNP.

As a further technical solution, the second switch tube is one of PMOS, NMOS, NPN, and PNP.

As a further technical solution, the third switching tube is one of PMOS, NMOS, NPN, and PNP.

Before the work output of an integrated circuit chip, the integrated circuit chip detects the capacitance of the chip pins, and after the capacitance of the chip pins can meet the capacitance of the integrated circuit chip in normal work, a main circuit of the integrated circuit chip is started.

As a further technical scheme, the detection method specifically comprises the following steps: when the power is on, the first switch tube, the second switch tube and the third switch tube are opened at the same time, so that the first capacitor, the second capacitor and the chip pin capacitor are charged at the same time, then the voltage values charged by the three capacitors are compared within a set time, if the voltage value of the first capacitor is less than the voltage value of the chip pin capacitor, and the voltage value of the second capacitor is greater than the voltage value of the chip pin capacitor, the chip pin capacitor is normally accessed, and the chip can be normally started.

Compared with the prior art, the invention can carry out self detection on the connectivity of the pin before the functional circuit of the integrated circuit main body works, enter a normal starting process under the condition of meeting the set condition, and lock the chip until the problem is solved if the abnormity of the capacitance of the pin is detected. Therefore, the chip is ensured to limit work and not to be damaged due to abnormal work under the condition that the pin connection is abnormal.

Drawings

FIG. 1 is a schematic diagram of the circuit structure of the present invention;

FIG. 2 is a flow chart of the operation of the present invention;

FIG. 3 is a waveform of V2> Vout, V1< Vout;

FIG. 4 is a waveform of V2< Vout, V1< Vout;

FIG. 5 shows waveforms of V2> Vout and V1> Vout.

Detailed Description

The invention is described in detail below with reference to the figures and specific embodiments.

Examples

As shown in FIG. 1, the present invention provides a circuit for detecting correct connection of chip pin capacitance based on capacitance range, which includes a first current source I1, a second current source I2, a third current source I3, a first switch tube M1, a second switch tube M2, a third switch tube M3, a first capacitor C1, a second capacitor C2, a first comparator, a second comparator and an AND gate circuit. The control signal ends of the first switch tube M1, the second switch tube M2 and the third switch tube M3 are connected, G1 is the control signal of the three switch tubes, G1 is high level to indicate that the switch is on, and low level to indicate that the switch is off. One end of the first switch tube M1 is connected to the first current source I1, and the other end of the first switch tube M1 is connected to the first capacitor C1 and the negative terminal of the second comparator, respectively. The other terminal of the first capacitor C1 is connected to ground. One end of the second switch tube M2 is connected to the second current source I2, and the other end of the second switch tube M2 is connected to the second capacitor C2 and the positive terminal of the first comparator, respectively. The other terminal of the second capacitor C2 is connected to ground. One end of the third switching tube M3 is connected to the third current source I3, and the other end of the third switching tube M3 is respectively connected to the negative terminal of the first comparator, the positive terminal of the second comparator, the output signal terminal of the chip a2, and the chip pin capacitor Cout. The other end of the chip pin capacitor Cout is grounded. The output ends of the first comparator and the second comparator are respectively connected with two input ends of the AND circuit, and the output end of the AND circuit is connected with the opening signal end of the chip A2.

The first switch tube is one of PMOS, NMOS, NPN and PNP. The second switch tube is one of PMOS, NMOS, NPN and PNP. The third switch tube is one of PMOS, NMOS, NPN and PNP.

V1 represents the voltage value at node C1; v2 represents the voltage value at node C2; a2 denotes the original basic chip circuit; the line connecting chip a2 to chip pin capacitor Cout is the original signal and represents the output signal. The chip A2 is connected to the output of the AND circuit, and the detected signal of the external capacitor OK is used to turn on the original basic chip circuit of A2. The invention judges whether the capacitor is in a certain range by charging, thereby realizing the detection of whether the chip pin capacitor is correctly accessed.

As shown in fig. 2, the work flow of the present invention is: after the chip A2 is powered on, the chip pin capacitance is detected, whether the chip pin capacitance has capacitance is judged, if yes, the chip A2 outputs normal work, and if not, the chip pin capacitance is re-detected.

At the beginning of power-on, the main module of chip a2 does not work, and does not output to the outside. First, the first switch tube M1, the second switch tube M2 and the third switch tube M3 are turned on simultaneously, so that the internal first capacitor C1, the second capacitor C2 and the external chip pin capacitor Cout are charged simultaneously, and the charging currents are I1, I2 and I3, respectively. Then, the voltage value V1 charged by the first capacitor C1, the voltage value V2 charged by the second capacitor C2 and the voltage value Vout charged by the chip pin capacitor Cout are compared within a predetermined time.

If V2> Vout, the waveform is as shown in fig. 3, i.e. V2/Vout >1, so Cout ═ V2/Vout ═ K2 × C2> K2 × C2, where K2 ═ I3/I2, i.e. the output capacitance is greater than the required capacitance value K2 × C2.

And if V1< Vout, the waveform is as shown in fig. 3, i.e. V1/Vout <1, so Cout ═ V1/Vout ═ K1 × C1< K1 × C1, where K1 ═ I3/I1, i.e. the output capacitance is smaller than the required capacitance value K1 × C1.

After the two conditions are combined, that is, K2 × C2< Cout < K1 × C1 are simultaneously satisfied, that is, it is illustrated that the chip pin is not in a cold joint or short circuit, and the pin capacitor is normally connected. At this time, the comparator output is high, and the main circuit module a2 is normally turned on.

If V2< Vout, the waveform is as shown in fig. 4, i.e. V2/Vout <1, so Cout ═ V2/Vout ═ K2 × C2< K2 × C2, where K2 ═ I3/I2, i.e. the output capacitance is smaller than the required capacitance value K2 × C2.

Or if V1> Vout, the waveform is as shown in fig. 5, i.e. V1/Vout >1, so Cout ═ V1/Vout ═ K1 × C1> K1 × C1, where K1 ═ I3/I1, i.e. the output capacitance is greater than the required capacitance value K1 × C1.

That is, if Cout > K1C 1 or Cout < K2C 2 is present, then it is likely that the capacitance being bonded is too small (with a miscount), and it is more likely that the capacitor will have a cold or missing bond. In this case, the main circuit module a2 is no longer turned on, thereby preventing damage to the chip or system caused by normal operation of a 2.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, it should be noted that any modifications, equivalents and improvements made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. The circuit for detecting the correct access of the chip pin capacitor based on the capacitor range is characterized by comprising a first current source, a second current source, a third current source, a first switch tube, a second switch tube, a third switch tube, a first capacitor, a second capacitor, a first comparator, a second comparator and an AND gate circuit, wherein control signal ends of the first switch tube, the second switch tube and the third switch tube are connected, one end of the first switch tube is connected with the first current source, the other end of the first switch tube is respectively connected with the negative ends of the first capacitor and the second comparator, the other end of the first capacitor is grounded, one end of the second switch tube is connected with the second current source, the other end of the second switch tube is respectively connected with the positive ends of the second capacitor and the first comparator, the other end of the second capacitor is grounded, one end of the third switch tube is connected with the third current source, and the other end of the third switch tube is respectively connected with the negative end, the negative end and the negative end of the first comparator, The output ends of the first comparator and the second comparator are respectively connected with two input ends of an AND circuit, and the output end of the AND circuit is connected with an opening signal end of the chip.

2. The circuit for detecting correct connection of chip pin capacitors according to claim 1, wherein the first switch tube is one of PMOS, NMOS, NPN, PNP.

3. The circuit for detecting correct connection of chip pin capacitors according to claim 1, wherein the second switch tube is one of PMOS, NMOS, NPN, PNP.

4. The circuit for detecting correct connection of chip pin capacitors according to claim 1, wherein the third switch tube is one of PMOS, NMOS, NPN, PNP.

5. A method for testing the circuit of claim 1, wherein the integrated circuit chip itself tests the capacitance of the chip pins before the integrated circuit chip outputs its operation, and when the capacitance of the chip pins can satisfy the capacitance of the integrated circuit chip for normal operation, the main circuit of the integrated circuit chip is turned on.

6. The detection method according to claim 5, wherein the detection method is specifically: when the power is on, the first switch tube, the second switch tube and the third switch tube are opened at the same time, so that the first capacitor, the second capacitor and the chip pin capacitor are charged at the same time, then the voltage values charged by the three capacitors are compared within a set time, if the voltage value of the first capacitor is less than the voltage value of the chip pin capacitor, and the voltage value of the second capacitor is greater than the voltage value of the chip pin capacitor, the chip pin capacitor is normally accessed, and the chip can be normally started.