CN112985465A

CN112985465A - Signal processing device, measuring device, and signal processing method

Info

Publication number: CN112985465A
Application number: CN202011295360.0A
Authority: CN
Inventors: 市原纯; 吉川康秀; 小原圭辅
Original assignee: Azbil Corp
Current assignee: Azbil Corp
Priority date: 2019-12-02
Filing date: 2020-11-18
Publication date: 2021-06-18
Also published as: JP2021089157A

Abstract

The invention provides a signal processing device, a measuring device, a signal processing method and a signal processing program capable of outputting signals with a resolution higher than that of a DA converter. A signal processing device (40) processes digital information obtained from a signal obtained by measuring a physical quantity and outputs the digital information to a DA converter (70), and the signal processing device (40) is provided with a control unit (50) which performs an alternative process on the lowest bit of the digital information to be transmitted to the DA converter (70) as the lowest bit or a bit varying to +1, and outputs the lowest bit to the DA converter (70).

Description

Signal processing device, measuring device, and signal processing method

Technical Field

The present invention relates to a signal processing device, a measuring device, a signal processing method, and a signal processing program for performing arithmetic processing on a digital signal input from the outside and outputting the digital signal.

Background

Conventionally, a measuring device for measuring a physical quantity such as pressure is known. As a measuring device, there is a capacitance type pressure sensor or the like that derives pressure from a change in capacitance according to displacement of a diaphragm (for example, see patent document 1). Such a measuring device performs AD conversion on a pressure signal or a temperature signal from a detector, for example, inputs the pressure signal or the temperature signal to a signal processing device, converts a pressure value, which is a result of polynomial operation performed by the signal processing device, into an analog signal, and outputs the analog signal.

Here, a DA converter (DA converter) is used as a device for converting digital information data output from the signal processing device into an analog signal. Resolution is known as 1 index indicating the performance of the DA converter. In the conventional measurement device, it is necessary to select a DA converter that satisfies the specification of the output resolution of the measurement device when selecting and designing the DA converter.

Documents of the prior art

Patent document

Patent document 1: japanese patent laid-open publication No. 2005-331328

Disclosure of Invention

Problems to be solved by the invention

However, in general, with regard to the DA converter, the higher the resolution, the more expensive. That is, in the DA converter, there is a trade-off relationship between resolution and product cost. Therefore, there is a demand for reducing the resolution of the DA converter as low as possible.

The present invention has been made to solve the above-described problems, and an object thereof is to provide a signal processing device, a measurement device, a signal processing method, and a signal processing program that can output a signal with a resolution higher than the original resolution of a DA converter.

Means for solving the problems

A signal processing device of the present invention processes digital information obtained from a signal obtained by measuring a physical quantity and outputs the processed digital information to a DA converter, and the signal processing device includes a control unit that performs an alternative process on the lowest bit of the digital information to be transmitted to the DA converter, the lowest bit being the lowest bit or varying to the lowest bit +1, and outputs the processed digital information to the DA converter.

The measurement device of the present invention includes the signal processing device, a DA converter as a data output destination of the signal processing device, and a low-pass filter for smoothing an analog signal output from the DA converter.

The signal processing method of the present invention includes: a calculation processing step of processing digital information obtained from the signal in which the physical quantity is measured, and calculating digital information to be sent to the DA converter; a selection processing step of selecting either the lowest bit of the digital information to be transmitted to the DA converter to be maintained or to be the lowest bit + 1; and a processing step of outputting the digital information including the selected lowest bit to the DA converter.

The signal processing program of the present invention causes a computer to perform the steps of: a calculation processing step of processing digital information obtained from the signal in which the physical quantity is measured, and calculating digital information to be sent to the DA converter; a selection processing step of selecting either the lowest bit of the digital information to be transmitted to the DA converter to be maintained or to be the lowest bit + 1; and a processing step of outputting the digital information including the selected lowest bit to the DA converter.

ADVANTAGEOUS EFFECTS OF INVENTION

According to the present invention, the lowest bit of the digital information to be transmitted to the DA converter is maintained at the lowest bit or changed to the lowest bit +1, and is output to the DA converter. Therefore, it is possible to output a signal including the lowest bit that cannot be represented by the resolution of the DA converter or a minute value between the lowest bits +1 in the analog signal related to the conversion by the DA converter. Therefore, an analog signal having a resolution higher than the original resolution of the DA converter can be output.

Drawings

Fig. 1 is a schematic configuration diagram of a measurement device according to an embodiment.

Fig. 2 is a block diagram showing a functional configuration of a signal processing device according to embodiment 1.

Fig. 3 is a diagram illustrating processing performed by the signal processing device according to embodiment 1.

Fig. 4 is a diagram showing an example of processing performed by the arithmetic processing unit of the control unit according to embodiment 1.

Fig. 5 is a diagram showing an example of processing performed by quantization processing means of the control unit in embodiment 1.

Fig. 6 is a block diagram showing a functional configuration of a signal processing device according to embodiment 2.

Fig. 7 is a diagram (1) for explaining the processing of the signal processing device according to embodiment 2.

Fig. 8 is a diagram (2) for explaining the processing of the signal processing device according to embodiment 2.

Fig. 9 is a diagram (3) for explaining the processing of the signal processing device according to embodiment 2.

Fig. 10 is a graph showing a Δ Σ output waveform corresponding to fig. 7.

Fig. 11 is a graph showing a Δ Σ output waveform corresponding to fig. 8.

Fig. 12 is a graph showing a Δ Σ output waveform corresponding to fig. 9.

Fig. 13 is a diagram showing an example of processing performed by quantization processing means of the control unit according to embodiment 2.

Fig. 14 is a block diagram showing a functional configuration of a signal processing device according to embodiment 3.

Fig. 15 is a diagram showing an example of processing performed by quantization processing means of the control unit according to embodiment 3.

Detailed Description

Embodiment 1.

Fig. 1 is a schematic diagram showing the configuration of a measurement apparatus according to embodiment 1. Fig. 2 is a block diagram showing a functional configuration of a signal processing device according to embodiment 1. The configuration of the measurement device 100 and the signal processing device 40 will be described with reference to fig. 1 and 2.

The measurement device 100 is a sensor such as a capacitance sensor that measures a physical quantity such as pressure from a change in capacitance. As shown in fig. 1, the measurement device 100 includes a detector 10, an analog processing circuit 20, an AD converter (analog-digital converter) 30, a signal processing device 40, a DA converter (digital-analog converter) 70, and a low-pass filter 80.

The detector 10 outputs a detection signal indicating a change in the physical quantity to the analog processing circuit 20. For example, when measuring pressure by a capacitance type pressure sensor, the detector 10 has a diaphragm that bends in accordance with the pressure applied thereto, and outputs a detection signal indicating a change in capacitance due to displacement of the diaphragm to the analog processing circuit 20.

The analog processing circuit 20 amplifies the detection signal output from the detector 10, removes noise, and outputs the signal to the AD converter 30. The AD converter 30 converts the analog signal output from the analog processing circuit 20 into a digital signal and outputs the digital signal to the signal processing device 40. The signal processing device 40 performs signal processing on the digital signal and outputs the processed digital signal. Here, the signal processing speed in the signal processing device 40 is described as being sufficiently fast with respect to a change in a physical quantity to be measured. The physical quantity is not random and varies continuously. The signal processing device 40 can follow the change of the physical quantity. The processing and the like performed by the signal processing device 40 will be described in detail later.

The DA converter 70 is a data output destination of the signal processing device 40. The DA converter 70 converts the digital signal output from the signal processing device 40 into an analog signal, and outputs the analog signal to the low-pass filter 80. The low-pass filter 80 reduces the frequency component higher than the cutoff frequency, smoothes the analog signal output from the DA converter 70, and outputs the smoothed analog signal.

The signal processing device 40 is constituted by, for example, a microcomputer, and performs processing such as arithmetic processing on data included in the digital signal output from the AD converter 30, and outputs the digital signal including the data related to the processing to the DA converter 70. As shown in fig. 2, the signal processing device 40 includes a control unit 50, a storage unit 60, and a timer unit 65.

The timer unit 65 includes a 1 st timer 66 and a 2 nd timer 67. The 1 st timer 66 performs timer output to the arithmetic processing unit 51 every signal value generation cycle, and causes the arithmetic processing unit 51 to generate a signal value based on the digital signal transmitted from the AD converter 30. The 2 nd timer 67 performs timer output to the quantization processing section 52 every generation value calculation cycle, and causes the quantization processing section 52 to calculate a generation value based on the signal value generated by the calculation processing section 51. Here, the signal value generation period is longer than the generation value calculation period. In addition, it is not necessary to synchronize the 1 st timer 66 with the 2 nd timer 67.

The control unit 50 includes an arithmetic processing unit 51 and a quantization processing unit 52. The arithmetic processing unit 51 has a physical quantity arithmetic unit 51a and a signal value generation unit 51 b. The physical quantity computing unit 51a processes a digital signal input from the outside, performs a predetermined computation or the like, and generates data representing a value of a physical quantity which is output to the signal value generating unit 51 b. For example, when the measuring apparatus 100 measures pressure, a detection signal including a pressure value as a physical quantity is output from the detector 10 as a digital signal. In this case, the physical quantity computing unit 51a processes the digital signal to generate data of the pressure value. Here, the physical quantity computation means 51a may be omitted when used without computing the value of the physical quantity included in the digital signal.

The signal value generating unit 51b generates data of a signal value based on the data representing the value of the physical quantity generated by the physical quantity computing unit 51 a. Here, the signal value generating unit 51b can generate a signal value that is expressed up to a value that is finer than a value that can be subjected to DA conversion processing by the DA converter 70 based on resolution. The value of a portion of the signal values that can be subjected to DA conversion processing is taken as a convertible signal value. The signal value can be converted into digital information to be sent to the DA converter 70.

The quantization processing unit 52 performs generation processing on a generated value matching the resolution of the DA converter 70 based on the signal value generated by the signal value generating unit 51b, and outputs a digital signal including data of the generated value. The quantization processing unit 52 performs the following processing: of the signal values generated by the signal value generating unit 51b, one of the transformable signal value and the transformable signal value +1 is set as a generated value based on a minute value which cannot be expressed by the resolution of the DA converter 70 other than the transformable signal value. Here, the quantization processing section 52 according to embodiment 1 performs an operation using the Δ Σ method, and generates a generated value that selects either the convertible signal value or the convertible signal value + 1. The generated value is thus a value that varies between the transformable signal value and the transformable signal value + 1. The quantization processing unit 52 in embodiment 1 includes a subtraction processing unit 52a, an integration unit 52b, and a quantization unit 52 c.

The subtraction processing section 52a subtracts the previous generated value from the signal value generated by the signal value generating section 51b to obtain a difference value. However, in the 1 st operation, the subtraction processing section 52a uses 0 as an initial value of the generated value. The integrating unit 52b integrates the difference values obtained by the subtracting unit 52a to obtain an integrated value.

The quantization unit 52c performs quantization processing on the integrated value obtained by the integration unit 52b, thereby calculating a generated value. Then, the digital signal containing the data of the generated value is sent to the DA converter 70. In embodiment mode 1, the quantization unit 52c generates a transformable signal value or a transformable signal value +1 as a generated value by quantization processing.

More specifically, the quantizing unit 52c calculates the convertible signal value +1 as the generated value if the integrated value is equal to or greater than a predetermined threshold value, and the quantizing unit 52c calculates the convertible signal value as the generated value if the integrated value is less than the threshold value. In embodiment 1, when a minute value that cannot be represented by the resolution of the DA converter 70 is represented by a 10-ary system, a value that can be rounded is set as a threshold value. However, the threshold value is not limited to this, and the setting can be arbitrarily changed.

The storage unit 60 stores various information such as an operation program of the control unit 50 as data. The operation program includes a signal processing program for causing the signal processing device 40 configured by a computer such as a microcomputer to function as the arithmetic processing unit 51 and the quantization processing unit 52.

Here, the control Unit 50 may be configured by an arithmetic device such as a CPU (Central Processing Unit) and software that realizes the various functions described above in cooperation with such an arithmetic device. The storage unit 60 may be constituted by a RAM (Random Access Memory), a ROM (Read Only Memory), a PROM (Programmable Read Only Memory) such as a flash Memory, or an HDD (Hard Disk Drive).

Fig. 3 is a diagram illustrating processing performed by the signal processing device according to embodiment 1. Here, 3425.456 in the 10-ary scale is assumed as a signal value, and the description is given. In the example of fig. 3, the subtraction processing section 52a obtains a difference value between the signal value and the generated value calculated in the previous generated value calculation cycle. Here, the initial value of the generated value is 0.

The integrating unit 52b integrates the difference values every generated value operation period to obtain an integrated value. The differential values in the example of fig. 3 repeat occasionally 0.456 and-0.544. Therefore, the integration value found by the integrating unit 52b repeats increasing and decreasing irregularly.

The quantization unit 52c determines whether or not the integrated value is equal to or greater than a threshold value every generated value calculation period. Then, when the value equal to or smaller than the decimal point in the integrated value is equal to or larger than the threshold value (here, 0.50), the quantizing unit 52c outputs the convertible signal value +1 as the generated value, and when the value equal to or smaller than the decimal point in the integrated value is smaller than the threshold value, the quantizing unit 52c outputs the convertible signal value as the generated value. Therefore, as shown in fig. 3, the generated values output by the quantization unit 52c irregularly repeat 3425 (D61 at 16 system) and 3426 (D62 at 16 system). In fig. 3, the quantization unit 52c outputs 3425 and 3426 of the generated values output during the period in which the generated value operation cycle is 25

times

14 and 11 times, respectively. When the number of times of the generation value operation period increases, the analog signal output through the low-pass filter 80 converges to 3425.456.

In embodiment 1, the quantization processing unit 52 performs continuous arithmetic operations even if the signal value generated by the signal value generating unit 51b changes. Fig. 3 shows an example in which the signal value changes in the 26 th and subsequent generation value calculation cycles.

The integrating unit 52b integrates the difference values every generated value operation period to obtain an integrated value. With regard to the differential value in the example of fig. 3, in the 26 th generation value operation cycle, the differential value is 2.756, but thereafter, 0.756 and-0.244 are occasionally repeated. Then, as shown in fig. 3, the generated values output by the quantization unit 52c are irregularly repeated 3427 (D63 at 16) and 3428 (D64 at 16). In fig. 3, the quantization unit 52c outputs 3427 and 3428 of the generated values output during the period in which the generated value operation cycle is 15 times, 3 times and 12 times, respectively. The generated value immediately after the change of the signal value deviates from the signal value, but when the number of times of the generated value calculation cycle increases, the analog signal output through the low-pass filter 80 converges to 3427.756.

Fig. 4 is a diagram showing an example of processing performed by the arithmetic processing unit of the control unit according to embodiment 1. Next, a flow of processing performed by the arithmetic processing unit 51 will be described with reference to fig. 4. The arithmetic processing unit 51 performs a calculation processing step. When an interrupt is inserted from the 1 st timer 66 (step S1), the physical quantity operation unit 51a of the operation processing unit 51 generates data representing the value of the physical quantity from the digital signal transmitted from the AD converter 30 (step S2). Further, the signal value generating unit 51b of the arithmetic processing unit 51 generates data of the signal value to be output to the DA converter 70 based on the data representing the value of the physical quantity generated by the physical quantity computing unit 51a (step S3). The arithmetic processing unit 51 repeats the above processing every signal value generation cycle.

Fig. 5 is a diagram showing an example of processing performed by quantization processing means of the control unit in embodiment 1. Next, a flow of processing performed by the quantization processing unit 52 will be described based on fig. 5. Here, as described above, the processing using the Δ Σ method will be described. When an interrupt is inserted from the 2 nd timer 67 (step S11), the subtraction processing unit 52a takes in the signal value generated by the signal value generating unit 51b (step S12). Then, the subtraction processing section 52a subtracts the previous generated value from the signal value, and calculates a differential value (step S13).

The integrating means 52b reads the integrated value generated in the previous generated value operating period from the storage unit 60, integrates the difference value calculated by the subtracting means 52a into the integrated value generated in the previous generated value operating period, and calculates a new integrated value. The integrating unit 52b stores the calculated integrated value in the storage unit 60 so that the integrated value is used for calculation of the integrated value in the next generated value calculation cycle (step S14).

The quantization unit 52c performs quantization processing on the integrated value obtained by the integration unit 52b, thereby calculating a generated value. The order in which the generated values are operated on is performed in the aforementioned order. The quantization means 52c stores the calculated generated value in the storage unit 60 so that the calculated generated value is used for calculation of the difference value in the next generated value calculation cycle (step S15). Then, the quantization unit 52c outputs the generated value calculated by the quantization process to the DA converter 70 (step S16). The quantization processing unit 52 repeats the above processing every generation value operation cycle.

As described above, the quantization processing unit 52 of the signal processing device 40 according to embodiment 1 performs quantization processing that selects either the lowest bit or the lowest bit +1 that varies depending on the resolution of the DA converter 70. Then, the digital signal including the generated value calculated by the quantization processing performed by the quantization processing unit 52 is output to the DA converter 70. Therefore, an analog signal including a value finer than a value that can be represented by the resolution of the DA converter 70 can be output. Therefore, the resolution of the DA converter 70 can be improved while substantially suppressing the product cost, and the performance of the measurement apparatus 100 can be improved.

In the signal processing device 40 according to embodiment 1, the control unit 50 performs an operation based on the delta-sigma modulation scheme, thereby enabling quantization processing with high accuracy. In this case, the quantization processing means 52 of the control unit 50 includes the subtraction means 52a and the integration means 52b, and performs an operation based on the Δ Σ modulation scheme, and the quantization means 52c performs quantization, thereby realizing quantization processing.

Embodiment 2.

Fig. 6 is a block diagram showing a functional configuration of a signal processing device according to embodiment 2. In fig. 6, the functional configuration to which the same reference numerals as in fig. 2 are added performs the same processing and the like as in embodiment 1.

The quantization processing unit 52 of embodiment 2 has a dividing unit 52 e. The dividing unit 52e divides the signal value generated by the arithmetic processing unit 51 into a value of an upper bit corresponding to the resolution of the DA converter 70 as the convertible signal value in embodiment 1 and a value of the remaining lower bit, and outputs these values by the number of times indicated by the lower bit. That is, the number m of upper bits (m is a natural number) is determined according to the resolution of the DA converter 70 so that the number m of upper bits is, for example, 10 when the resolution of the DA converter 70 is 10 bits, and 12 when the resolution of the DA converter 70 is 12 bits.

Here, when the number of lower bits is n (n is a natural number), the number of lower bits expressed is n (2) th power of 2 (2)ⁿ) And (4) seed preparation. For example, when the lower bits are 4 bits, the number of bits expressed by the lower bits is 16 (2) which is 0 to 15⁴) And (4) seed preparation. That is, the number of times of the number represented by the lower bits is a number of times corresponding to the number of times that the lower bits can be represented by the 10 th system, and specifically, is an n-th power of 2 (2)ⁿ) Next, the process is carried out.

The subtraction processing section 52a subtracts the previous converted value from the value of the lower bit divided by the dividing section 52e to obtain a difference value. The conversion value is a value obtained by multiplying the number of the numbers represented by the lower bits by the quantization value. That is, in the case where the lower-order bit is n bits, the subtraction processing section 52a will 2ⁿThe quantized value is multiplied by the reference value to obtain a conversion value.

The integrating unit 52b integrates the difference values obtained by the subtracting unit 52a to obtain an integrated value. The integrating unit 52b integrates the number of pieces of the generated value calculation period represented by the lower bits for each piece of the digital information.

The quantization unit 52c quantizes the integration value obtained by the integration unit 52b to generate a quantized value, and outputs the generated quantized value to the subtraction processing unit 52a and the addition unit 52 f. In embodiment 2, the quantization unit 52c outputs 0 or 1 corresponding to the lowest bit (the lowest byte) of the upper bits as a quantized value.

Here, in the quantization processing section 52 of embodiment 2, the subtraction processing section 52a, the integration section 52b, and the quantization section 52c are the lower bit processing section 52d that calculates the lower bits.

The adder 52f adds the value of the upper bit output from the divider 52e and the quantization value output from the quantization processor 52, and outputs the resultant value to the DA converter 70, with the sum of the value of the upper bit and the quantization value being the resultant value. The counting unit 52g increments the count value i, and counts the number of times of the number indicated by the lower bit.

Fig. 7 to 9 are diagrams illustrating processing performed by the signal processing device according to embodiment 2. Fig. 7 shows the case where the signal value is D61.9 in the 16 th system (3425.5625 in the 10 th system). Fig. 8 shows a case where the signal value is d61.a in 16-ary (3425.625 in 10-ary). Fig. 9 shows a case where the signal value is d61.b in 16-ary (3425.6875 in 10-ary). Specific processing contents performed by the quantization processing unit 52 and the addition unit 52f in embodiment 2 will be described with reference to fig. 7 to 9.

Fig. 7 to 9 show examples in which the dividing section 52e divides a 16-bit signal value into an upper bit value of 12 bits and a remaining lower bit value of 4 bits. Since the lower bits are 4 bits, the number of bits expressed by the lower bits is 16 (2)⁴). Therefore, the dividing unit 52e outputs the value of the 16 th upper-order bit to the adding unit 52f and the value of the 16 th lower-order bit to the subtracting unit 52a in accordance with the generated value operation cycle. The initial value of the quantization value is set to 0.

In the example of fig. 7, the dividing unit 52e divides the signal value D61.9 into the upper bit value D61 (integer part) and the lower bit value 0.9 (fractional part), and outputs the values 16 times. The subtraction processing section 52a obtains a difference value by the following equation (1) every time the value of the lower bit is output from the dividing section 52 e. Further, the quantized value in expression (1) is a quantized value or an initial value generated by the quantization unit 52c in the previous generated value operation period.

[ formula 1]

Difference value is the value of the lower bit-the previous quantization value x the number of the numbers represented by the lower bit

…(1)

The integrating unit 52b integrates the difference values every generated value operation period to obtain an integrated value. The differential values in the example of fig. 7 repeat 9 and-7 aperiodically. Therefore, the integration value found by the integrating unit 52b repeats increasing and decreasing irregularly.

The quantization unit 52c determines whether or not the integrated value is equal to or greater than a threshold value every generated value calculation period. Then, when the integrated value is equal to or greater than the threshold value, the quantizing section 52c outputs 1 as a quantized value, and when the integrated value is smaller than the threshold value, the quantizing section 52c outputs 0 as a quantized value. Therefore, as shown in fig. 7, the quantized value output by the quantization unit 52c irregularly repeats 0 and 1. As can be seen from fig. 7, in the case where the signal value is D61.9, the quantization unit 52c outputs 0 as a quantized value 7 times and 1 9 times.

The adder 52f adds the value of the upper bit output from the divider 52e and the quantization value output from the quantizer 52c at intervals of the generated value operation cycle, calculates the generated value, and outputs the generated value to the DA converter 70. Since the signal processing device 40 according to embodiment 2 employs an operation using the Δ Σ method, the generated value is also referred to as Δ Σ output. As is clear from fig. 7, when the signal value is D61.9, the adding section 52f outputs D61 as the generated value 7 times and D62 9 times. Further, D61 in 16 scale corresponds to 3425 in 10 scale, and D62 in 16 scale corresponds to 3426 in 10 scale.

In the example of fig. 8, the dividing unit 52e divides the signal value D61A into the upper bit value D61 and the lower bit value 0.a, and outputs the values 16 times. Since fig. 8 has the same configuration as fig. 7, the description of the processing performed by each part is appropriately omitted or simplified.

The differential values in the example of fig. 8 repeat a and-6 irregularly, and accordingly the integrated value repeats increasing and decreasing irregularly. As can be seen from fig. 8, when the signal value is d61.a, the quantization unit 52c outputs 0 and 16 times and 10 times as quantized values. That is, in the case where the signal value is D61.a, the quantization unit 52c outputs 1 more times than when the signal value is D61.9. Therefore, the number of times of outputting D62 as the generated value by the addition unit 52f is 1 more than the case where the signal value is D61.9.

In the example of fig. 9, the dividing unit 52e divides the signal value D61.b into the upper bit value D61 and the lower bit value 0.B, and outputs the values 16 times. Fig. 9 is the same configuration as fig. 7 and 8, and therefore the explanation of the processing performed by each part is appropriately omitted or simplified.

The differential values in the example of fig. 9 repeat B and-5 irregularly, and the integrated values increase and decrease irregularly in accordance therewith. As can be seen from fig. 9, in the case where the signal value is d61.b, the quantization unit 52c outputs 0 and 1 as

quantized values

5 and 11 times, respectively. That is, in the case where the signal value is d61.b, the quantization unit 52c outputs 1 more times than when the signal value is d 61.a. Therefore, the adding unit 52f outputs D62 as the generated value 1 more times than the case where the signal value is D61A.

Fig. 10 is a graph showing a Δ Σ output waveform corresponding to fig. 7. Fig. 11 is a graph showing a Δ Σ output waveform corresponding to fig. 8. Fig. 12 is a graph showing a Δ Σ output waveform corresponding to fig. 9. In fig. 10 to 12, the horizontal axis represents time, and the vertical axis represents a generated value.

Referring to fig. 10 to 12, the items known from fig. 7 to 9 can be visually confirmed. That is, as is clear from fig. 10, 11, and 12, as the count value increases by 1, the average value of the generated values slightly increases within the range of the lowest bit among the 12 bits.

Here, in each of fig. 7 to 9, the average values of the generated values are compared in the 10-system. When the signal value is D61.9 as in fig. 7, the average value of the generated values 16 times is "3425.5625", and is the same as the signal value. When the signal value is d61.a as shown in fig. 8, the average value of the generated values 16 times is "3425.625", and is the same as the signal value. When the signal value is d61.b as in fig. 9, the average value of the generated values 16 times is "3425.6875", and is the same as the signal value.

In this way, the signal processing device 40 outputs the digital signal including the generated value by the number of times represented by the lower bits, and thus can substantially make a minute value, which cannot be represented by the resolution of the DA converter 70, between integers, an analog signal.

Fig. 13 is a diagram showing an example of processing performed by quantization processing means of the control unit according to embodiment 2. Next, a flow of processing performed by the quantization processing unit 52 will be described based on fig. 13. Here, the signal value generation processing performed by the arithmetic processing unit 51 is the same processing as that described in embodiment 1.

When an interrupt is inserted from the 2 nd timer 67 (step S21), the counting unit 52g determines whether the count value i that counts the number of times is i-0 (step S22). When the counting section 52g determines that i is 0, the dividing section 52e outputs the value of the upper bit to the adding section 52f and the value of the lower bit to the subtracting section 52a (step S23).

The subtraction processing section 52a multiplies the number of numbers represented by the lower bits by the previous quantization value to obtain a conversion value. Then, the subtraction processing section 52a subtracts the converted value from the value of the lower bit to obtain a difference value (step S24). Next, the integrating section 52b obtains an integrated value which is a value obtained by integrating the difference values obtained by the subtracting section 52a (step S25). In the first processing, the integrating unit 52b directly takes the difference value as an integrated value.

Next, the quantizing unit 52c determines whether or not the integrated value is equal to or greater than a threshold value (step S26). When the integrated value is equal to or greater than the threshold value (step S26/yes), the quantizing section 52c outputs 1 as a quantized value to the subtracting section 52a and the adding section 52f (step S27). On the other hand, if the integrated value is smaller than the threshold value (step S26/no), the quantizing unit 52c outputs 0 to the subtraction processing unit 52a and the adding unit 52f as a quantized value (step S28).

The adding section 52f adds the value of the upper bit outputted from the dividing section 52e to the quantization value outputted from the quantization section 52c, and calculates the resultant value (step S29). Then, the addition unit 52f outputs the generated value to the DA converter 70 (step S30).

The counter 52g increments the counter value i by 1, i +1 (step S31). Then, the counting unit 52g determines whether the count value i is i-16 (step S32). When the counter unit 52g determines that i is not 16, the process ends. On the other hand, when it is determined that i is 16, counting section 52g returns the count value i to 0 (step S33), and ends the process. The quantization processing unit 52 repeats the above processing every generation value operation cycle.

As described above, the signal processing device 40 according to embodiment 2 divides a signal value as digital information into a value of an upper bit and a value of a lower bit, and obtains 2 the sum of a quantized value indicating the magnitude of the value of the lower bit and the value of the upper bitⁿAnd then, outputting. Therefore, since the analog signal including the value between the integer and the decimal point or less is substantially output, the measurement device 100 can output a signal having a value obtained at a desired resolution even if the resolution of the DA converter 70 is low.

That is, the signal processing device 40 can use 2ⁿThe entirety of the generated values indicates the size of the value of the lower bit in the count value as digital information. That is, as shown in fig. 7 to 12, the signal processing device 40 can use 2ⁿThe individual generated values accurately transmit the values of the lower bits of the count value that cannot be expressed by the resolution of the DA converter 70 to the DA converter 70. Therefore, the measurement device 100 can measure the pressure or the like with the accuracy equivalent to that in the case where a DA converter having high resolution and relatively high cost is mounted. That is, according to the measurement device 100, the resolution in the DA conversion can be increased while suppressing the cost of the DA converter 70.

More specifically, the quantization processing unit 52 subtracts the converted value from the value of the lower bit by the number of times indicated by the lower bit to obtain a difference value, integrates the difference value to obtain an integral value, quantizes the integral value, and generates a quantized value. As shown in fig. 7 to 9, the difference value at each time takes a positive value or a negative value in accordance with the value of the lower bit of the count value, and the integrated value increases or decreases in accordance with the change in the difference value. Therefore, the magnitude of the value of the lower bit is reflected in the generated value which is the sum of the value of the upper bit and the quantized value obtained by quantizing the integrated value, and therefore the DA converter 70 can perform processing at the resolution equivalent to that of the high-resolution DA converter.

In addition, the subtraction processing unit 52a uses the quantized value generated by the quantization unit 52c in the previous generated value operation period for the operation of the differential value. That is, the subtraction processing section 52a subtracts, from the value of the lower bit, the converted value obtained by multiplying the number of the numbers indicated by the lower bit by the first 1 quantization value, and thereby obtains the difference value. Therefore, if the value of the lower bit is larger than the previous converted value, the differential value is a positive value, and if the value of the lower bit is smaller than the previous converted value, the differential value is a negative value. In this way, the generated value of each time is determined based on the magnitude relationship between the value of the lower bit and the previous converted value, and therefore the value of the lower bit can be reflected in the generated value with high accuracy.

Further, the quantizing unit 52c determines whether or not the number of times represented by the lower bits has elapsed and the integrated value is equal to or greater than the threshold, and outputs 1 as the quantized value if the integrated value is equal to or greater than the threshold, and outputs 0 as the quantized value if the integrated value is smaller than the threshold. Therefore, the signal processing device 40 can generate two generated values differing by 1 in magnitude irregularly in accordance with the value of the lower bit, and can expand the resolution in the DA conversion of the measurement device 100. Here, although the threshold value can be changed as appropriate, if the threshold value is set to the same value as the number of the lower bits, the value of the lower bits can be reflected more accurately on the generated value.

The measurement device 100 includes a signal processing device 40, a DA converter 70 as a data output destination of the signal processing device 40, and a low-pass filter 80 for smoothing an analog signal output from the DA converter 70. Therefore, according to the measurement device 100, it is possible to output an analog signal generated by increasing the resolution in the DA conversion to the outside.

Embodiment 3.

Fig. 14 is a block diagram showing a functional configuration of a signal processing device according to embodiment 3. In fig. 14, the functional configuration to which the same reference numerals as in fig. 6 are added performs the same processing and the like as in embodiment 2. As shown in fig. 14, in embodiment 3, the storage unit 60 includes a quantized value storage unit 61. The quantized value storage unit 61 stores, as data in a table format, a relationship between values of lower bits and an array of the number of quantized values. Then, the quantized value determining unit 52h performs a process of determining a quantized value based on the value of the lower bit divided by the dividing unit 52e and the data of the quantized value storage section 61.

As described in embodiment 2, for example, when the lower bits are 4 bits, the numerical values that the lower bits can represent are 0 to F in the 16 th order (0 to 15 in the 10 th order). Then, the number of the lower bits is counted as a number of times, and the difference value, the integral value, and the quantization value are counted as a number of times, thereby calculating a generated value. Here, as shown in fig. 7 to 9, when the value of the lower bit is determined, the difference value and the integration value are uniformly determined. Then, the arrangement of the quantized values of the several quantities is also determined.

For example, as shown in fig. 7, when the value of the lower bit is 9, the difference value obtained by the 1 st operation is 9, and the integrated value is 9. At this time, the quantization value is 1. The difference value obtained by the 2 nd calculation is-7, and the integrated value is 2. At this time, the quantization value is 0. Therefore, the arrangement of the quantization values when the lower bit value is 9 is "1010101101010101".

Therefore, data in which the values (0 to F) of the lower bits and the arrangement of the quantization values of the number of times (16 times) are associated with each other is stored in advance in the quantization value storage unit 61. Then, the quantized value determining unit 52h determines the value of the lower bit divided by the dividing unit 52e, and reads the data of the quantized value corresponding to the determined value of the lower bit from the quantized value storage unit 61. Then, the quantized value determining unit 52h outputs "0" or "1" as a quantized value to the adding unit 52f every generated value operation period based on the data of the quantized value.

Fig. 15 is a diagram showing an example of processing performed by quantization processing means of the control unit according to embodiment 3. Next, a flow of processing performed by the quantization processing unit 52 will be described based on fig. 15. Here, the signal value generation processing performed by the arithmetic processing unit 51 is the same processing as that described in embodiment 1.

When an interrupt is inserted from the 2 nd timer 67 (step S41), the counting unit 52g determines whether the count value i that counts the number of times is i-0 (step S42). When the counting section 52g determines that i is 0, the dividing section 52e divides the value of the upper bit and the value of the lower bit, outputs the value of the upper bit to the adding section 52f, and outputs the value of the lower bit to the quantized value determining section 52h (step S43). The quantized value determining unit 52h determines the value of the lower bit divided by the dividing unit 52e (step S44). The quantized-value determining section 52h reads the i-th quantized value from the data of the array of quantized values corresponding to the determined value of the lower bit as data, and outputs the quantized value read to the adding section 52f (step S45).

The adding section 52f adds the value of the upper bit outputted from the dividing section 52e to the quantized value outputted from the quantized value determining section 52h, and calculates the resultant value (step S46). Then, the addition unit 52f outputs the generated value to the DA converter 70 (step S47).

The counter 52g increments the counter value i by 1, i +1 (step S48). Then, the counting unit 52g determines whether the count value i is i-16 (step S49). When the counter unit 52g determines that i is not 16, the process ends. On the other hand, when it is determined that i is 16, counting section 52g returns the count value i to 0 (step S50), and ends the process. The quantization processing unit 52 repeats the above processing every generation value operation cycle.

As described above, the signal processing device 40 according to embodiment 3 includes the quantized value storage unit 61 that stores data in which the lower bit value and the array of the quantized values of the number of times are associated with each other in the storage unit 60. Further, there is a quantized value determination unit 52h that outputs the determined quantized value to the addition unit 52f based on the data of the quantized value storage section 61. Therefore, even if the values of the lower bits are not subtracted or accumulated, the quantized values can be obtained. Therefore, the configuration of the signal processing device 40 is simplified, and the processing speed can be increased.

Embodiment 4.

Embodiments 1 to 3 are preferred specific examples of the signal processing device, the measurement device, the signal processing method, and the signal processing program, but are not limited to these examples. For example, the number m of upper bits is not limited to the above example, and may be set in accordance with the resolution of the DA converter 70 included in the measurement device 100. In the above description, the pressure sensor is exemplified as the measurement device 100, but the present invention is not limited thereto. The measurement device 100 may be various sensors such as a temperature sensor, a humidity sensor, an optical sensor, and an acceleration sensor, or may be a measurement device such as a flow meter and a calorimeter.

The lower bit processing means 52d in embodiment 2 has 1 set of the subtraction processing means 52a and the integration means 52b, and performs the Δ Σ modulation once, but is not limited to this. The two sets of the subtraction processing means 52a and the integration means 52b may be provided, and may be configured in a two-stage configuration, and quantization may be performed by performing quadratic Δ Σ modulation. Further, 3 sets of the subtraction processing means 52a and the integration means 52b may be provided, and the quantization may be performed in 3 stages, with three-time Δ Σ modulation, or the like, or may be performed in n stages, with n-time Δ Σ modulation.

Description of the symbols

The device comprises a detector 10, an analog processing circuit 20, an AD converter 30, a signal processing device 40, a control unit 50, an arithmetic processing unit 51, a physical quantity arithmetic unit 51a, a signal value generating unit 51b, a quantization processing unit 52, a subtraction processing unit 52a, an integrating unit 52b, a quantization unit 52c, a lower bit processing unit 52d, a dividing unit 52e, an adding unit 52f, a counting unit 52g, a quantization value judging unit 52h, a storage unit 60, a quantization value storage unit 61, a timer 65, a timer 1 st 66, a timer 2 nd 67, a converter 70DA, a low-pass filter 80, and a measuring device 100.

Claims

1.A signal processing device for processing digital information obtained from a signal obtained by measuring a physical quantity and outputting the processed digital information to a DA converter,

the signal processing device includes a control unit that performs processing for selecting either the lowest bit of the digital information to be transmitted to the DA converter or the lowest bit that varies by +1, and outputs the selected lowest bit to the DA converter.

2. The signal processing apparatus of claim 1,

the control unit performs an operation based on delta-sigma modulation, and sets or changes the lowest bit to either the lowest bit or the lowest bit + 1.

3. The signal processing apparatus according to claim 1 or 2,

the control unit includes:

a subtraction processing unit that subtracts a value output to the DA converter in a previous generated value operation cycle from data based on a signal value of the digital information to obtain a difference value;

an integration unit configured to integrate the difference value obtained by the subtraction unit to obtain an integrated value; and

and a quantization unit configured to quantize the integration value obtained by the integration unit and output a value such that the lowest bit becomes the lowest bit or the lowest bit +1 to the DA converter.

4. The signal processing apparatus according to claim 1 or 2,

the control unit includes:

a dividing unit that divides data based on the signal value of the digital information into a value of an upper bit corresponding to a resolution of the DA converter and a value of the remaining lower bit, and outputs the values as many times as the number indicated by the lower bit;

a lower bit processing unit that acquires the value of the lower bit from the dividing unit, generates a quantized value indicating the magnitude of the value of the lower bit, and outputs the quantized value; and

and an adder that obtains a generated value that is a sum of the value of the upper bit and the quantization value and outputs the obtained value to the DA converter.

5. The signal processing apparatus of claim 4,

the lower bit processing unit includes:

a subtraction processing unit configured to subtract a conversion value obtained by multiplying the quantization value by the number of the lower bits from the value of the lower bits to obtain a difference value;

and a quantization unit configured to quantize the integration value obtained by the integration unit, generate the quantized value, and output the quantized value.

6. The signal processing apparatus of claim 5,

the subtraction processing unit uses the quantized value generated by the quantization unit in a previous generated value operation period for the operation of the differential value.

7. The signal processing apparatus of claim 5,

the quantization unit outputs 1 as the quantized value if the integrated value is equal to or greater than a predetermined threshold value,

if the integrated value is smaller than the threshold value, the quantization unit outputs 0 as the quantization value.

8. The signal processing apparatus of claim 7,

the threshold value is the same as the number of the numbers represented by the lower bits.

9. The signal processing apparatus according to claim 1 or 2,

the signal processing device includes a storage unit for storing data,

the control unit includes:

a quantization value determination unit that acquires the value of the lower bit from the division unit, determines a quantization value based on the value of the lower bit from the data stored in the storage unit, and outputs the quantization value; and

an adder for obtaining a generated value which is a sum of the value of the upper bit and the quantization value and outputting the obtained value to the DA converter,

the storage unit has a quantized value storage unit that stores a relationship between the value of the lower bit and the arrangement of the number of times of the quantized value.

10. The signal processing apparatus of claim 3,

the signal processing device includes an arithmetic processing unit that performs arithmetic processing on the digital information obtained from a signal obtained by measuring a physical quantity, and generates data of the signal value.

11. A measurement device is characterized by comprising:

the signal processing apparatus according to any one of claims 1 to 10;

the DA converter as a data output destination of the signal processing device; and

and a low-pass filter for smoothing the analog signal output from the DA converter.

12. A signal processing method comprising:

a calculation processing step of processing digital information obtained from a signal in which the physical quantity is measured, and calculating the digital information to be transmitted to the DA converter;

a selection processing step of selecting either the lowest bit of the digital information to be transmitted to the DA converter, while maintaining the lowest bit or becoming the lowest bit + 1; and

a processing step of outputting the digital information including the selected lowest bit to the DA converter.