CN112951715A - Groove gate structure and preparation method of groove type field effect transistor structure - Google Patents
Groove gate structure and preparation method of groove type field effect transistor structure Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Abstract
The invention provides a trench gate structure and a preparation method of the trench field effect transistor structure, wherein the preparation method of the trench gate structure comprises the following steps: providing a semiconductor substrate, forming a first dielectric material layer, forming a grid material layer, etching to form a device grid, forming a second dielectric material layer, and forming a side wall epitaxial material layer. According to the scheme, the preparation of the device grid and the grid dielectric layer is completed firstly, the side wall epitaxial layer is formed later, namely the groove for preparing the device grid is formed later, compared with the scheme that the grid groove is formed by etching firstly, and then the device grid is filled in the grid groove, the problem of grid groove etching is solved, especially the groove etching under the condition that AR is larger, meanwhile, the defect of device grid filling is also solved, and the problems that the sealing is easy to occur in advance in the filling process, the filling effect is poor and the like are solved.
Description
Technical Field
The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a trench gate structure and a preparation method of a trench field effect transistor structure.
Background
MOSFET (Power Metal Oxide Semiconductor Field-effect Transistor) is widely applied in the fields of 4C (Communication, Computer, Consumer, automobile) and the like due to the advantages of high switching speed, good frequency performance, high input impedance, small driving Power, good temperature characteristic, no secondary breakdown problem and the like. The trench power MOSFET device is formed by a plurality of MOSFET cells, each MOSFET cell is called a cell, and the pitch (pitch) between cells directly affects the important electrical parameter of the power MOSFET, i.e., the drain-source on-state resistance Rdson. The vertical double-diffusion metal-oxide-semiconductor field effect transistor (VDMOS) has the advantages of a bipolar transistor and a common MOS device, and the VDMOS is an ideal power device regardless of switching application or linear application, and is mainly applied to motors, inverters, uninterruptible power supplies, electronic switches, hi-fi stereos, automobile electrical appliances, electronic ballasts and the like. VDMOS is classified into two types, enhancement type and depletion type.
Compared with a common power device, the application of the power MOSFET is often limited in the field of low-power application, and is quite limited in the field of high-power application such as power grid control and rail transit, so that in order to expand the application field of the power MOSFET, the on-state current of the power MOSFET needs to be increased, and the power MOSFET can be realized by reducing the area of a cell, so that more cells are designed on the same area, but with the reduction of the cell size, the problem of the device preparation process is also brought, for example, a hole with a high aspect ratio is difficult to effectively etch (high AR trench) by adopting the existing process, a hole is difficult to effectively fill, for example, polysilicon filling in the groove-type gate forming process, and a hole filling process is also easy to seal in advance.
Therefore, it is necessary to provide a trench gate structure and a method for fabricating a trench field effect transistor structure to solve the above-mentioned problems in the prior art.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a trench gate structure and a method for manufacturing a trench field effect transistor structure, which are used to solve the problems in the prior art that a deep trench is difficult to be etched effectively and a material is difficult to be filled effectively in the trench.
In order to achieve the above and other related objects, the present invention provides a method for manufacturing a trench gate structure, the method comprising the steps of:
providing a semiconductor substrate, and forming a first dielectric material layer on the semiconductor substrate;
forming a gate material layer on the first dielectric material layer;
etching the grid material layer to form a device grid on the first medium material layer;
forming a second dielectric material layer on at least the exposed outer wall of the device grid; and
and forming a side wall epitaxial material layer on the semiconductor substrate, wherein the side wall epitaxial material layer is at least formed on the outer wall of the second medium material layer.
Optionally, before forming the sidewall epitaxial material layer, the method further includes: and removing the first dielectric material layer on the semiconductor substrate around the device grid to form a bottom grid dielectric layer between the device grid and the semiconductor substrate, wherein the side wall epitaxial material layer is formed on the surface of the semiconductor substrate.
Optionally, the first dielectric material layer on the semiconductor substrate around the device gate is removed by using a BOE etching method.
Optionally, the second dielectric material layer is further formed above the device gate, the sidewall epitaxial material layer is formed on an outer wall of the second dielectric material layer and extends to above the device gate, and the step of forming the sidewall epitaxial material layer further includes: and removing the second dielectric material layer above the device grid to form a side wall grid dielectric layer, and removing the side wall epitaxial material layer above the device grid to form a side wall epitaxial layer, wherein the side wall epitaxial layer, the side wall grid dielectric layer and the upper surface of the device grid are flush.
Optionally, the thickness of the first dielectric material layer is greater than the thickness of the second dielectric material layer.
Optionally, the material of the first dielectric material layer comprises silicon oxide, and the forming method of the first dielectric material layer comprises a chemical vapor deposition method or a wet thermal oxidation method; the material of the second dielectric material layer comprises silicon oxide, and the forming method of the second dielectric material layer comprises a dry thermal oxidation method.
The invention also provides a preparation method of the trench type field effect transistor structure, which comprises the following steps:
providing a semiconductor substrate, and forming a bottom epitaxial layer on the semiconductor substrate;
forming a first dielectric material layer on the bottom epitaxial layer;
forming a gate material layer on the first dielectric material layer;
etching the grid material layer to form a device grid on the first medium material layer;
forming a second dielectric material layer on at least the exposed outer wall of the device grid;
forming a side wall epitaxial material layer on the bottom epitaxial layer, wherein the side wall epitaxial material layer is at least formed on the outer wall of the second medium material layer;
forming a body region in the sidewall epitaxial material layer around the device gate, and forming a source adjacent to the second dielectric material layer in the body region; and
and preparing a source electrode structure electrically connected with the source electrode and the body region on the side wall epitaxial material layer, and preparing a drain electrode structure on one side of the semiconductor substrate, which is far away from the bottom epitaxial layer.
Optionally, before forming the sidewall epitaxial material layer, the method further includes: and removing the first dielectric material layer on the bottom epitaxial layer around the device grid to form a bottom grid dielectric layer between the device grid and the bottom epitaxial layer, wherein the side wall epitaxial material layer is formed on the surface of the bottom epitaxial layer.
Optionally, the second dielectric material layer is further formed over the device gate, and the sidewall epitaxial material layer is formed on an outer wall of the second dielectric material layer and extends to a position over the device gate, where the step of forming the sidewall epitaxial material layer further includes: and removing the second dielectric material layer above the device grid to form a side wall grid dielectric layer, and removing the side wall epitaxial material layer above the device grid to form a side wall epitaxial layer, wherein the side wall epitaxial layer, the side wall grid dielectric layer and the upper surface of the device grid are flush.
Optionally, the thickness of the first dielectric material layer is greater than the thickness of the second dielectric material layer.
Optionally, the doping type of the bottom epitaxial layer is the same as that of the sidewall epitaxial material layer, and the doping concentration of the bottom epitaxial layer is different from that of the sidewall epitaxial material layer.
As described above, according to the trench gate structure and the method for manufacturing the trench field effect transistor structure of the present invention, the device gate and the gate dielectric layer are manufactured first, and then the sidewall epitaxial layer is formed, that is, the trench for manufacturing the device gate is formed later.
Drawings
Fig. 1 shows a process flow diagram for manufacturing a trench gate structure according to the present invention.
Fig. 2 is a schematic structural diagram illustrating a first dielectric material layer formed in the trench gate structure preparation provided by the present invention.
Fig. 3 is a schematic structural diagram illustrating a gate material layer formed in the trench gate structure preparation process provided by the present invention.
Fig. 4 is a schematic structural diagram illustrating a device gate formed in the trench gate structure fabrication process provided by the present invention.
Fig. 5 is a schematic structural diagram illustrating a second dielectric material layer formed in the trench gate structure preparation provided by the present invention.
Fig. 6 is a schematic structural diagram illustrating the formation of a bottom gate dielectric layer in the preparation of the trench gate structure provided by the present invention.
Fig. 7 is a schematic structural diagram illustrating the formation of a sidewall epitaxial material layer in the preparation of the trench gate structure provided by the present invention.
Fig. 8 is a schematic view illustrating the formation of a sidewall epitaxial layer and a sidewall gate dielectric layer in the preparation of the trench gate structure provided in the present invention.
Fig. 9 is a schematic diagram of a trench fet structure according to the present invention.
Description of the element reference numerals
100 semiconductor substrate
100a semiconductor substrate
100b bottom epitaxial layer
101 first dielectric material layer
102 layer of gate material
103 device gate
104 second dielectric material layer
105 bottom gate dielectric layer
106 layers of sidewall epitaxial material
107 side wall gate dielectric layer
108 sidewall epitaxial layer
109 body region
110 source electrode
110 layer of insulating material
112 source electrode structure
113 drain electrode structure
S1-S5
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.
The first embodiment is as follows:
as shown in fig. 1 to 8, the present invention provides a method for manufacturing a trench gate structure, the method comprising the steps of:
providing a semiconductor substrate, and forming a first dielectric material layer on the semiconductor substrate;
forming a gate material layer on the first dielectric material layer;
etching the grid material layer to form a device grid on the first medium material layer;
forming a second dielectric material layer on at least the exposed outer wall of the device grid; and
and forming a side wall epitaxial material layer on the semiconductor substrate, wherein the side wall epitaxial material layer is at least formed on the outer wall of the second medium material layer.
The following describes the method for fabricating the trench gate structure in detail with reference to the accompanying drawings.
As shown in S1 in fig. 1 and fig. 2, a semiconductor substrate 100 is provided, and a first dielectric material layer 101 is formed on the semiconductor substrate 100, wherein the semiconductor substrate 100 may be a single material layer or a structure including two or more stacked material layers, in one example, the semiconductor substrate 100 may include a semiconductor substrate (e.g., a silicon substrate) and an epitaxial layer formed on the semiconductor substrate, so as to prepare a semiconductor device structure based on the semiconductor substrate, and the structure and the constituent material of the semiconductor substrate 100 may be selected according to actual device requirements.
In addition, the first dielectric material layer 101 may be a silicon oxide material layer, and may also be a high-dielectric-constant dielectric layer, but is not limited thereto, in a preferred example, the first dielectric material layer 101 may be formed by a Chemical Vapor Deposition (CVD) process, and in an example, the first dielectric material layer 101 is subsequently used as a part for forming a gate dielectric layer. In another example, the first dielectric material layer 101 may be formed by using an existing thermal oxidation process, which may be a dry thermal oxidation process or a wet thermal oxidation process, and preferably, by using a wet thermal oxidation process, wherein an oxide layer grown by using CVD and wet oxidation is relatively loose, which is beneficial for removing a part of the first dielectric material layer 101 in a subsequent process, for example, for removing an oxide layer based on BOE, and the removal rate is faster than that of the oxide layer in the dry thermal oxidation process.
As shown in S2 of fig. 1 and fig. 3, a gate material layer 102 is formed on the first dielectric material layer 101, wherein the gate material layer 102 is made of a material including, but not limited to, polysilicon, and the formation process thereof includes, but not limited to, a chemical vapor deposition process. In the present invention, a gate electrode for forming a device on the first dielectric material layer 101 is formed on the basis of the gate material layer 102.
As shown in S3 in fig. 1 and fig. 4, the gate material layer 102 is etched to form a device gate 103 on the first dielectric material layer 101, wherein the device gate 103 may be formed by a photolithography-etching process, a photoresist layer may be formed on the gate material layer 102, and then patterned to form a pattern of the required device gate, and then the gate material layer 102 is etched based on the patterned photoresist to form the device gate 103, wherein the number and layout of the device gates 103 may be selected according to actual requirements.
As shown in S4 in fig. 1 and fig. 5, a second dielectric material layer 104 is formed at least on the exposed outer wall of the device gate 103, wherein the material of the second dielectric material layer 104 may be a silicon oxide material layer, and may also be a high-k dielectric layer, but is not limited thereto, in an alternative example, the second dielectric material layer 104 is formed by a thermal oxidation process, in a preferred example, a dry oxidation process is used, and a dry thermal oxidation process is used, in addition, the second dielectric material layer 104 may also be simultaneously formed on the top surface of the device gate 103, and in another example, the second dielectric material layer 104 may also be simultaneously formed on the first dielectric material layer around the device gate 103.
As an example, as shown in fig. 6, the method for manufacturing a trench gate structure further includes the steps of: the first dielectric material layer 101 on the semiconductor substrate 100 around the device gate 103 is removed to form a bottom gate dielectric layer 105 between the device gate 103 and the semiconductor substrate 100, preferably, the present invention removes this portion of the first dielectric material layer 101 after forming the second dielectric material layer 104, which is beneficial to prevent the second dielectric material layer 104 (for example, formed by dry oxidation) from being formed directly on the semiconductor substrate 100 and is beneficial to prevent the problem that the gate side oxide may be completely eaten away due to the removal of the later-formed dry oxidation layer, and the subsequently-formed sidewall epitaxial material layer 106 is formed on the surface of the semiconductor substrate 100, where the bottom gate dielectric layer 105 is a portion of the gate dielectric layer of the device gate 103.
In an optional example, the first dielectric material layer 101 on the semiconductor substrate 100 around the device gate 103 is removed by using a BOE etching method, where BOE refers to Buffered Oxide Etch, and the BOE is formed by mixing hydrofluoric acid (49%) with water or ammonium fluoride and water, and the BOE removal is beneficial to improving the stability of the Oxide layer removal rate, but other methods may also be used.
As shown in S5 of fig. 1 and fig. 7-8, a sidewall epitaxial material layer 106 is formed on the semiconductor substrate 100, and the sidewall epitaxial material layer 106 is further formed at least on an outer wall of the second dielectric material layer 104. The material of the sidewall epitaxial material layer 106 includes, but is not limited to, a doped monocrystalline silicon material layer, wherein an epitaxial process may be first used to form an intrinsic epitaxial layer on the upper surface of the semiconductor substrate 100, and then doped by implanting dopant ions into the intrinsic epitaxial layer through an ion implantation process; in another example, an epitaxial process may also be used to epitaxially form a doped material layer directly on the upper surface of the semiconductor substrate 100. In one example, the sidewall epitaxial material layer 106 is selected to be an N-type single crystal silicon epitaxial layer.
As an example, the second dielectric material layer 104 is further formed above the device gate 103, and the sidewall epitaxial material layer 106 is formed on an outer wall of the second dielectric material layer 104 and extends above the device gate 103, as shown in fig. 7, the step of forming the sidewall epitaxial material layer 106 further includes: removing the second dielectric material layer 104 above the device gate 103 to form a sidewall gate dielectric layer 107, removing the sidewall epitaxial material layer 106 above the device gate 103 to form a sidewall epitaxial layer 108, exposing the top of the device gate 103, wherein the sidewall epitaxial layer 108, the sidewall gate dielectric layer 107 and the upper surface of the device gate 103 are flush, and the sidewall gate dielectric layer 107 and the bottom gate dielectric layer 105 formed based on the first dielectric material layer 101 form a gate dielectric layer of the device gate 103.
In an example, the thickness of the first dielectric material layer 101 is greater than that of the second dielectric material layer 104, so that the thickness of the obtained bottom gate dielectric layer 105 is greater than that of the sidewall gate dielectric layer 107, and a gate dielectric layer with a thickened bottom is obtained, which can reduce the risk of breakdown of a bottom gate oxide layer and is beneficial to resisting a higher voltage at the bottom; in addition, in an example, the thickness of the first dielectric material layer 101 may be controlled by process parameters, on one hand, the semiconductor substrate 100 may be protected during the process of etching the gate material layer 102 to form the device gate 103, so that a part of the first dielectric material layer 102 remains on the surface of the semiconductor substrate 100 after etching, and on the other hand, the thickness of the first dielectric material layer 101 is controlled, so as to facilitate removing the first dielectric material layer 101 around the device gate 103 after forming the second dielectric material layer 104, and in an example, facilitate performing BOE etching. In an optional example, the thickness of the first dielectric material layer 101 is in a range between 500 and 2000A, and may be 1000A and 1500A, the thickness of the second dielectric material layer 104 is in a range between 250 and 1500A, and may be 500A and 1000A, and the thicknesses of the first dielectric material layer 101 and the second dielectric material layer 104 may be selected according to actual requirements, and are not limited thereto.
Through the scheme, the preparation of the device grid 103, the side wall grid dielectric layer 107 and the bottom grid dielectric layer 105 is firstly completed, the side wall epitaxial layer 108 is formed later, namely, the groove for preparing the device grid 103 is formed later, and compared with the scheme that the grid groove is formed by etching firstly and then the device grid is filled in the grid groove, the method solves the problem of grid groove etching, particularly the etching of the groove under the condition that the AR is larger, simultaneously, the defect of device grid filling is also solved, and the problems that the sealing is easy to occur in advance in the filling process, the filling effect is poor and the like are solved.
Example two:
as shown in fig. 9 and referring to fig. 1-8, the present invention further provides a method for manufacturing a trench field effect transistor structure, the method comprising the steps of:
providing a semiconductor substrate 100a, and forming a bottom epitaxial layer 100b on the semiconductor substrate 100 a;
forming a first dielectric material layer 101 on the bottom epitaxial layer 100 b;
forming a gate material layer 102 on the first dielectric material layer 101;
etching the gate material layer 102 to form a device gate 103 on the first dielectric material layer 101;
forming a second dielectric material layer 104 on at least the exposed outer wall of the device gate 103;
forming a sidewall epitaxial material layer 106 on the bottom epitaxial layer 100b, wherein the sidewall epitaxial material layer 106 is further formed at least on an outer wall of the second dielectric material layer 104;
forming a body region 107 in the sidewall epitaxial material layer 106 around the device gate 103, and forming a source 110 adjacent to the second dielectric material layer 104 in the body region 109; and
a source electrode structure 112 electrically connected to both the source 110 and the body 109 is formed on the sidewall epitaxial material layer 106, and a drain electrode structure 113 is formed on a side of the semiconductor substrate 100a away from the bottom epitaxial layer 100 b.
As an example, before forming the sidewall epitaxial material layer 106, the method further includes: removing the first dielectric material layer 104 on the bottom epitaxial layer 100b around the device gate 103 to form a bottom gate dielectric layer 105 between the device gate 103 and the bottom epitaxial layer 100b, and forming the sidewall epitaxial material layer 106 on the surface of the bottom epitaxial layer 100 b.
As an example, the second dielectric material layer 104 is further formed over the device gate 103, and the sidewall epitaxial material layer 106 is formed on an outer wall of the second dielectric material layer 104 and extends over the device gate 103, wherein the step of forming the sidewall epitaxial material layer 106 further includes: removing the second dielectric material layer 104 above the device gate 106 to form a sidewall gate dielectric layer 107, and removing the sidewall epitaxial material layer 106 above the device gate 103 to form a sidewall epitaxial layer 108, wherein the sidewall epitaxial layer 108, the sidewall gate dielectric layer 107 and the upper surface of the device gate 103 are flush.
As an example, the thickness of the first dielectric material layer 101 is greater than the thickness of the second dielectric material layer 104.
It should be noted that, the trench field effect transistor structure provided in this embodiment includes the semiconductor substrate 100a, the bottom epitaxial layer 100b, the sidewall epitaxial layer 108, the bottom gate dielectric layer 105, the sidewall gate dielectric layer 107, and the device gate 103, and the above structures and their preparation are the same as the trench gate structure in the embodiment, and specific description may refer to embodiment one, which is not repeated herein, where the semiconductor substrate 100a and the bottom epitaxial layer 100b constitute the semiconductor substrate 100 in embodiment one, and in addition, in this embodiment, the preparation of the trench field effect transistor structure further includes a step of preparing a body region 109, a source 110, a source electrode structure 112, and a drain electrode structure 113, and in addition, an insulating material layer 111 may be prepared on the sidewall epitaxial layer 108, and the source electrode structure 112 is electrically connected to the source 110 and the body region 109 through the insulating material layer 111 The above structure and the preparation thereof can be prepared by the existing process, and are not described herein again.
In addition, as an example, the doping types of the bottom epitaxial layer 100b and the sidewall epitaxial material layer 106 are the same, and the doping concentrations of the bottom epitaxial layer 100b and the sidewall epitaxial material layer 108 formed on the basis of the sidewall epitaxial material layer 106 are different, where the doping concentrations of the bottom epitaxial layer 100b and the sidewall epitaxial layer 108 formed on the basis of the sidewall epitaxial material layer 106 constitute an epitaxial layer of the field effect transistor structure of this embodiment, and the doping concentrations of the two can be selected according to requirements, so that the breakdown voltage and the on-resistance of the device can be optimized through the doping of the two, and of course, the doping concentrations of the bottom epitaxial layer 100b and; in one example, the doping concentration of the bottom epitaxial layer 100b and the sidewall epitaxial layer 108 is different from the doping concentration of the semiconductor substrate 100 a.
In summary, according to the trench gate structure and the method for manufacturing the trench field effect transistor structure of the present invention, the device gate and the gate dielectric layer are manufactured first, and then the sidewall epitaxial layer is formed, that is, the trench for manufacturing the device gate is formed later. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (11)
1. A preparation method of a trench gate structure is characterized by comprising the following steps:
providing a semiconductor substrate, and forming a first dielectric material layer on the semiconductor substrate;
forming a gate material layer on the first dielectric material layer;
etching the grid material layer to form a device grid on the first medium material layer;
forming a second dielectric material layer on at least the exposed outer wall of the device grid; and
and forming a side wall epitaxial material layer on the semiconductor substrate, wherein the side wall epitaxial material layer is at least formed on the outer wall of the second medium material layer.
2. The method of claim 1, further comprising the step of, before forming the sidewall epitaxial material layer: and removing the first dielectric material layer on the semiconductor substrate around the device grid to form a bottom grid dielectric layer between the device grid and the semiconductor substrate, wherein the side wall epitaxial material layer is formed on the surface of the semiconductor substrate.
3. The method of claim 2, wherein the first dielectric material layer on the semiconductor substrate around the device gate is removed by a BOE etching method.
4. The method of claim 1, wherein the second dielectric material layer is further formed over the device gate, the sidewall epitaxial material layer is formed on an outer wall of the second dielectric material layer and extends over the device gate, and the step of forming the sidewall epitaxial material layer further comprises: and removing the second dielectric material layer above the device grid to form a side wall grid dielectric layer, and removing the side wall epitaxial material layer above the device grid to form a side wall epitaxial layer, wherein the side wall epitaxial layer, the side wall grid dielectric layer and the upper surface of the device grid are flush.
5. The method of claim 1, wherein the thickness of the first dielectric material layer is greater than the thickness of the second dielectric material layer.
6. The method for preparing a trench gate structure according to any one of claims 1 to 5, wherein the material of the first dielectric material layer comprises silicon oxide, and the forming method of the first dielectric material layer comprises a chemical vapor deposition method or a wet thermal oxidation method; the material of the second dielectric material layer comprises silicon oxide, and the forming method of the second dielectric material layer comprises a dry thermal oxidation method.
7. A preparation method of a trench type field effect transistor structure is characterized by comprising the following steps:
providing a semiconductor substrate, and forming a bottom epitaxial layer on the semiconductor substrate;
forming a first dielectric material layer on the bottom epitaxial layer;
forming a gate material layer on the first dielectric material layer;
etching the grid material layer to form a device grid on the first medium material layer;
forming a second dielectric material layer on at least the exposed outer wall of the device grid;
forming a side wall epitaxial material layer on the bottom epitaxial layer, wherein the side wall epitaxial material layer is at least formed on the outer wall of the second medium material layer;
forming a body region in the sidewall epitaxial material layer around the device gate, and forming a source adjacent to the second dielectric material layer in the body region; and
and preparing a source electrode structure electrically connected with the source electrode and the body region on the side wall epitaxial material layer, and preparing a drain electrode structure on one side of the semiconductor substrate, which is far away from the bottom epitaxial layer.
8. The method of claim 7, further comprising the step of, prior to forming the sidewall epitaxial material layer: and removing the first dielectric material layer on the bottom epitaxial layer around the device grid to form a bottom grid dielectric layer between the device grid and the bottom epitaxial layer, wherein the side wall epitaxial material layer is formed on the surface of the bottom epitaxial layer.
9. The method of claim 7, wherein the second dielectric material layer is further formed over the device gate, and the sidewall epitaxial material layer is formed on an outer wall of the second dielectric material layer and extends over the device gate, wherein the step of forming the sidewall epitaxial material layer further comprises: and removing the second dielectric material layer above the device grid to form a side wall grid dielectric layer, and removing the side wall epitaxial material layer above the device grid to form a side wall epitaxial layer, wherein the side wall epitaxial layer, the side wall grid dielectric layer and the upper surface of the device grid are flush.
10. The method of claim 7 wherein the first dielectric material layer has a thickness greater than a thickness of the second dielectric material layer.
11. The method of any of claims 7-10, wherein the bottom epitaxial layer and the sidewall epitaxial material layer have the same doping type and different doping concentrations.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115881523A (en) * | 2023-02-08 | 2023-03-31 | 合肥晶合集成电路股份有限公司 | Groove type grid and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101836282A (en) * | 2007-08-20 | 2010-09-15 | 格罗方德半导体公司 | Mos structures that exhibit lower contact resistance and methods for fabricating the same |
| CN103035501A (en) * | 2012-09-19 | 2013-04-10 | 上海华虹Nec电子有限公司 | Preparation method for polycrystalline silicon groove grid and capable of avoiding holes |
| CN103035500A (en) * | 2012-06-04 | 2013-04-10 | 上海华虹Nec电子有限公司 | Formation method of trench gate |
| CN110061007A (en) * | 2018-01-18 | 2019-07-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
-
2019
- 2019-12-10 CN CN201911260880.5A patent/CN112951715B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101836282A (en) * | 2007-08-20 | 2010-09-15 | 格罗方德半导体公司 | Mos structures that exhibit lower contact resistance and methods for fabricating the same |
| CN103035500A (en) * | 2012-06-04 | 2013-04-10 | 上海华虹Nec电子有限公司 | Formation method of trench gate |
| CN103035501A (en) * | 2012-09-19 | 2013-04-10 | 上海华虹Nec电子有限公司 | Preparation method for polycrystalline silicon groove grid and capable of avoiding holes |
| CN110061007A (en) * | 2018-01-18 | 2019-07-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115881523A (en) * | 2023-02-08 | 2023-03-31 | 合肥晶合集成电路股份有限公司 | Groove type grid and manufacturing method thereof |
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