CN107452806A - Longitudinal double-diffused metal oxide semiconductor field-effect tube with composite dielectric layer and preparation method of longitudinal double-diffused metal oxide semiconductor field-effect tube - Google Patents

Longitudinal double-diffused metal oxide semiconductor field-effect tube with composite dielectric layer and preparation method of longitudinal double-diffused metal oxide semiconductor field-effect tube Download PDF

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CN107452806A
CN107452806A CN201710623812.5A CN201710623812A CN107452806A CN 107452806 A CN107452806 A CN 107452806A CN 201710623812 A CN201710623812 A CN 201710623812A CN 107452806 A CN107452806 A CN 107452806A
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region
layer
drift region
oxide semiconductor
metal oxide
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CN201710623812.5A
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段宝兴
曹震
吕建梅
师通通
杨银堂
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西安电子科技大学
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Abstract

The invention provides a longitudinal double-diffused metal oxide semiconductor field-effect tube (VDMOS) with a composite dielectric layer (Composite Dielectric Layer, CDL) and a preparation method of the longitudinal double-diffused metal oxide semiconductor field-effect tube. According to the device, a composite layer of a semi-insulated polycrystalline silicon (SIPOS) layer and a high-dielectric constant (High K) dielectric is mainly formed on the side wall of a drift region at the lower part of a gate electrode. When the device is shut off, an SIPOS column and a High-K dielectric layer have uniform electric fields, so that electric field distribution in the drift region of the device is uniform through electric field modulation. Meanwhile, the SIPOS column and the High-K dielectric layer exhaust the drift region in an auxiliary manner in common, so that the exhaust capacity of the drift region of the device is greatly improved, the doping concentration of the drift region of the device is increased and the on resistance of the device is reduced. When the device is opened, a majority carrier accumulation layer is arranged on the side wall of the drift region, so that the on resistance of the device is further reduced.

Description

一种具有复合介质层纵向双扩散金属氧化物半导体场效应管及其制作方法 One kind of vertical double diffused metal oxide semiconductor field effect transistor composite dielectric layer and manufacturing method thereof having

技术领域 FIELD

[0001] 本发明涉及半导体器件领域,特别是涉及一种沟槽(Trench)型的纵向双扩散金属氧化物半导体场效应管。 [0001] The present invention relates to semiconductor devices, and more particularly, to a trench (Trench) type vertical double diffused metal oxide semiconductor field effect transistor.

背景技术 Background technique

[0002] 随着功率M0SFET器件代表新型功率半导体器件迅速发展,功率半导体器件广泛的应用于计算机、照明、消费类电子、汽车电子、工业驱动等领域。 [0002] With the rapid development of power M0SFET devices on behalf of new power semiconductor devices, power semiconductor devices widely used in computers, lighting, consumer electronics, automotive electronics, industrial drives and other fields. 功率半导体器件是绿色低功耗节能环保的核心器件。 The power semiconductor device is a low-power energy saving green core components. 在1985年由D.Ueda等人提出了沟槽(Trench) M0S结构。 In 1985, he proposed a trench (Trench) M0S structure consists D.Ueda et al. 采用U型沟槽结构使得器件的导通沟道由横向变为纵向,有效地消除了JFET的电阻,大大增加了原胞密度,提高了器件的电流处理能力。 The U-groove structure such that the device becomes turned on by the lateral longitudinal channel, effectively eliminating the JFET resistance, greatly increasing the cell density of the original, the improved current handling capability of the device. 然而在功率器件高压应用领域内,随着器件击穿电压的升高,功率VDM0S外延层厚度不断增加,漂移区掺杂浓度逐渐降低,导致器件的导通电阻会随着器件击穿电压的2.5次急剧增加,使得器件的导通损耗增大。 However, in the high voltage power device applications, with the increase of the breakdown voltage of the device, the power VDM0S epitaxial layer thickness increased, the drift region doping concentration decreases, resulting in device on-resistance will increase as the device breakdown voltage is 2.5 times increased dramatically, such that the conduction loss of the device is increased.

发明内容 SUMMARY

[0003] 本发明提出了一种具有复合介质层(Composite Dielectric Layer,CDL)纵向双扩散金属氧化物半导体场效应管(VDMOS),旨在优化VDMOS器件击穿电压与比导通电阻的矛盾关系。 [0003] The present invention proposes a contradictory relationship having a composite dielectric layer (Composite Dielectric Layer, CDL) vertical double diffused metal oxide semiconductor field effect transistor (VDMOS), designed to optimize the ratio of the breakdown voltage of the VDMOS device on-resistance .

[0004] 本发明的技术方案如下: [0004] aspect of the present invention is as follows:

[0005] 一种具有复合介质层纵向双扩散金属氧化物半导体场效应管,包括: [0005] A composite dielectric layer having a vertical double diffused metal oxide semiconductor field effect transistor, comprising:

[0006] 半导体材料的衬底,兼作漏区; [0006] substrate of a semiconductor material, also serves as a drain region;

[0007] 在衬底上外延生长形成的漂移区; [0007] The drift region formed by epitaxial growth on the substrate;

[0008] 在所述漂移区上表面掺杂形成的左、右两处基区; [0008] The doped surface formed on the left drift region, the right two base region;

[0009] 在所述基区上部掺杂分别形成的源区和沟道衬底接触; [0009] The source region and the channel doping of the substrate are formed in an upper portion in contact with said base region;

[0010] 在所述源区和沟道衬底接触上表面形成的源极; [0010] source surface formed on the source region and the channel substrate contact electrode;

[0011] 在所述漏区下表面形成的漏极; [0011] surface of the drain in the drain region;

[0012] 有别于现有VDMOS的是: [0012] Unlike existing VDMOS are:

[0013]所述衬底以及漂移区的材料是元素半导体材料(即第一代半导体材料);在所述左、右两处基区之间刻蚀有沟槽,沟槽沿纵向穿过漂移区至衬底漏区;沟槽的深宽比根据器件漂移区的长度和宽度确定,漂移区的长度根据器件的击穿电压要求确定; [0013] The material of the substrate and the drift region of semiconductor material is an element (i.e., a first-generation semiconductor material); the left and right between the two trenches etched with the base region, the trench along the longitudinal direction through the drift a drain region to the substrate region; aspect ratio of the trench and the width of the device according to the length of the drift region is determined, the length of the drift region is determined according to the breakdown voltage requirements;

[0014] 在所述沟槽的侧壁依次形成有栅绝缘层、具有掺氧的半绝缘多晶硅层,使半绝缘多晶硅层纵向两端与器件的栅漏两端相连;半绝缘多晶硅层纵向表面对应于基区为重掺杂区域,在该重掺杂区域表面形成栅极; [0014] are sequentially formed on the gate insulating layer, a polysilicon layer having oxygen-doped semi-insulating, so that a semi-insulating polycrystalline silicon layer connected to both ends of the longitudinal ends of the device gate-drain in a side wall of the trench; longitudinal surface of the semi-insulating polycrystalline silicon layer corresponding to the base region is heavily doped region, a gate is formed in the heavily doped surface region;

[0015] 在半绝缘多晶硅层的沟槽内填充High K介质,High K介质与漂移区纵向等高。 [0015] High K dielectric filled trench in the semi-insulating polysilicon layer, the longitudinal contour High K dielectric and the drift region.

[0016] 在以上方案的基础上,本发明还作了如下优化: [0016] Based on the above aspect, the present invention made the following optimization:

[0017] High K材料的相对介电常数是100〜2000。 [0017] High K relative permittivity material is 100~2000.

[0018]横向上High K介质的宽度(也即表面成为半绝缘多晶硅层的沟槽的宽度)为0.2〜 5um〇 [0018] High K dielectric transverse width (i.e. width of the groove surface becomes semi-insulating polycrystalline silicon layer) is 0.2~ 5um〇

[0019] 栅绝缘层的厚度根据阈值电压设定,典型值为0.02〜0. lwn。 [0019] The thickness of the gate insulating layer is set to a threshold voltage, typically 0.02~0. Lwn.

[0020] 击穿电压要求600V时,外延生长的漂移区厚度(也即前述漂移区的长度)为25〜50 um〇 [0020] When the breakdown voltage requirements 600V, thickness of the drift region (i.e., the length of the drift region) is grown epitaxially 25~50 um〇

[0021] 元素半导体材料衬底的掺杂浓度为一般元素半导体单晶材料制备的浓度,典型值为1 X l〇13cm-3〜1 X 1015cm_3。 [0021] doping concentration of the element of the semiconductor material of the substrate is generally prepared at a concentration of elemental semiconductor single crystal material, typically 1 X l〇13cm-3~1 X 1015cm_3.

[0022]元素半导体材料优选硅材料或者锗材料,当然也可以是其他元素半导体材料。 [0022] semiconductor material, preferably silicon or germanium elemental materials, of course, other elements may be semiconductor materials. [0023]半绝缘多晶硅层的掺氧比例为15%〜35%,其相应电阻率为109〜l〇uD • cm。 An oxygen blending ratio of [0023] semi-insulating polycrystalline silicon layer is 15% ~ 35%, which corresponds to a resistivity of 109~l〇uD • cm. [0024]半绝缘多晶硅层的厚度为〇. 2〜1.5wn。 Thickness [0024] The semi-insulating polycrystalline silicon layer is square. 2~1.5wn.

[0025] 当击穿电压要求600V时,则深宽比为15:1〜25:1;击穿电压要求200V时,则深宽比为5:1〜10:1〇 [0025] When the breakdown voltage requirements 600V, the aspect ratio of 15: 1~25: 1; breakdown voltage requirements 200V, the aspect ratios of 5: 1~10: 1〇

[0026]半绝缘多晶硅层中所述重掺杂区域的掺杂浓度为1〇18〜l〇2〇cra3。 [0026] The semi-insulating polycrystalline silicon layer in the doping concentration of the heavily doped region is 1〇18~l〇2〇cra3.

[GG27] —种制作上述具有复合介质层纵向双扩散金属氧化物半导体场效应管的方法,包括以下步骤: [GG27] - methods of the above composite dielectric layer having a vertical double diffused metal oxide semiconductor field effect transistor fabrication, comprising the steps of:

[0028] 1)取元素半导体材料的衬底同时作为漏区; Substrate [0028] 1) take the same time as an element of a drain semiconductor material region;

[0029] 2)在衬底上形成外延层作为漂移区; [0029] 2) a drift region of the epitaxial layer is formed on a substrate;

[0030] 3)在漂移区上部以离子注入或扩散形成基区; [0030] 3) In an ion implantation or diffusion region formed in the upper portion of the drift region group;

[0031] 4)在基区刻蚀沟槽,使沟槽向下穿过漂移区至漏区; [0031] 4) etching trenches in the base region of the trench through the drift region down to the drain region;

[0032] 5)在沟槽侧壁上形成栅绝缘层; [0032] 5) forming a gate insulating layer on the trench sidewalls;

[0033] 6)在栅绝缘层外淀积形成半绝缘多晶硅层并掺氧; [0033] 6) depositing a gate insulating layer is formed on the outer semi-insulating layer and an oxygen-doped polysilicon;

[0034] 7)在沟槽内纵向对应于漂移区的区域填充High K介质; [0034] 7) in the longitudinal groove region corresponding to the drift region is filled High K medium;

[0035] 8)在基区上掺杂形成源区和沟道衬底接触; [0035] 8) doped base region is formed on a substrate contact a source region and a channel;

[0036] 9)对沟槽内半绝缘多晶硅层表面纵向对应于基区的区域进行重掺杂,并淀积多晶硅形成栅极; [0036] 9) on the surface of semi-insulating polysilicon layer within the trench region corresponding to the longitudinal direction of the heavily doped base region, and forming a gate polysilicon is deposited;

[0037] 1〇)源区和沟道衬底接触表面形成源极; [0037] 1〇) a source region and a channel forming a source contact surface of the substrate;

[0038] 11)漏区表面形成漏极。 [0038] 11) a drain region formed in the surface of the drain.

[0039] 本发明技术方案的有益效果如下: [0039] Advantageous effects of the technical solution of the present invention are as follows:

[0040]利用深沟槽技术在VDM0S器件栅电极下方的漂移区侧壁上形成半绝缘多晶硅(SIP0S)层半绝缘多晶硅(SIPOS)层和高介电常数(High K)介质的复合层,侧壁形成的SIP0S柱两端为高浓度掺杂区域,并分别连接器件的栅电极和漏电极(接至漏区可视为与漏电极连接),SIPOS柱中间空隙填充High K介质层。 [0040] The use of deep trench technology to form a semi-insulating polycrystalline silicon (SIP0S) semi-insulating polycrystalline silicon layer (the SIPOS) layer and a high dielectric constant (High K) a composite dielectric layer on sidewalls of the drift region beneath the gate electrode VDM0S device, the side SIP0S ends column wall is formed heavily doped region, and a drain respectively and a gate electrode connected to the source device (connected to the drain region connected to the drain electrode may be considered), the SIPOS column filled intermediate space high K dielectric layer. 在器件关断时,SIPOS和High K组成的复合介质层上具有均匀的电场,通过电场调制作用使得器件漂移区上的整体电场变得均匀, 同时复合介质层增加器件耗尽能力(SIPOS柱与High K介质层共同辅助耗尽漂移区),比单纯的只有SIPOS层或只有High K层的情况器件的耗尽能力增强,即大幅度提高了器件漂移区的掺杂浓度,在器件导通时具有较低的导通损耗。 When the device is turned off, a uniform electric field having a composite dielectric layer consisting of SIPOS and High K, so that the overall effect of electric field modulation by the electric field on the device drift region becomes uniform, while increasing the ability of the composite dielectric layer depletion device (SIPOS column and High K dielectric layer depletion auxiliary common drift region), enhanced ability than a simple case only the depletion layer of the device or only a High K SIPOS layer, i.e., greatly improved the doping concentration of the drift region of the device, when the device is turned on having lower conduction losses. 在器件开启时,复合介质层在器件漂移区上积累更多的多数载流子,器件的导通电阻进一步降低。 When the device is turned on, the composite dielectric layer to accumulate more majority carriers in the drift region of the device, to further reduce the on-resistance of the device.

[0041]总之,基于元素半导体材料的CBL VDM0S器件相比传统的VDM0S器件,在相同漂移区长度的情况下,CBL VDM0S器件具有更高的耐压和更低的导通损耗,CBL VDM0S器件具有更好的性能。 [0041] In summary, compared to the traditional devices based CBL VDM0S device VDM0S elemental semiconductor material, in the case of the same length of the drift region, CBL VDM0S devices with higher withstand voltage and lower conduction losses, CBL VDM0S device having better performance.

附图说明 BRIEF DESCRIPTION

[0042]图1为本发明实施例的结构示意图(正视图),器件结构沿图中虚线镜像对称。 [0042] FIG. 1 is a schematic structural diagram (front view) of the present embodiment of the invention, the device structure in mirror symmetry broken line in FIG. [0043] 附图标号说明: [0043] Reference numerals:

[0044] 1源极;2-極绝缘层;3-半绝缘多晶桂层;4-概极;5-High K介质;6-漏极;7-漏区; 8-漂移区;9-基区;10-沟道衬底接触;11-源区。 [0044] a source electrode; 2- insulator layer; 3- Gui semi-insulating polycrystalline layer; 4- Almost electrode; 5-High K medium; 6- drain; 7- drain regions; 8- drift region; 9- base region; 10- channel substrate contact; 11- source region.

具体实施方式 Detailed ways

[0045]如图1所示,该具有复合介质层纵向双扩散金属氧化物半导体场效应管包括: [0045] As shown in FIG. 1, the composite having a vertical double diffused metal oxide semiconductor field effect transistor dielectric layer comprises:

[0046]元素半导体材料(娃材料)衬底作为漏区7,掺杂浓度可为一般元素半导体单晶材料的浓度,典型值为1 X 1013cnf3〜丨x 10i5cm_3; [0046] The elemental semiconductor material (material Wa) substrate is used as a drain region 7, the concentration of the doping concentration may be a single-crystal material is generally a semiconductor element, typically 1 X 1013cnf3~ Shu x 10i5cm_3;

[0047]位于衬底上的外延层形成的漂移区8; [0047] The epitaxial layer situated on the substrate 8 formed in the drift region;

[0048]在所述漂移区上掺杂形成的基区9; [0048] The base doping in the drift region 9 is formed;

[0049]在基区上刻蚀沟槽,沟槽向下穿过漂移区至衬底漏区; [0049] The etching groove on the base region, the drift region trenches through the drain region down to the substrate;

[0050]在沟槽侧壁上形成的栅绝缘层2,厚度根据器件的阈值电压设定,典型值为〇. 02〜 0.lum; [0050] The gate is formed on the trench sidewall insulating layer 2, the thickness is set according to the threshold voltage of the device, typically square 02~ 0.lum.;

[0051]在栅绝缘层外淀积形成的具有掺氧的半绝缘多晶硅层3;半绝缘多晶硅层的厚度为o.2〜1.5_;半绝缘多晶硅层的摻氧比例为15%〜35%,其相应电阻率为109〜10nQ • cm;半绝缘多晶硅层中重掺杂区域的掺杂浓度为1 o18〜1 〇2〇cm3; [0051] The semi-insulating polycrystalline silicon layer 3 has an outer oxygen-doped gate insulating layer is formed by deposition; thickness of the semi-insulating polysilicon layer o.2~1.5_; oxygen-doped semi-insulating polycrystalline silicon layer proportion of 15% ~ 35% , which corresponds to a resistivity of 109~10nQ • cm; semi-insulating polycrystalline silicon layer is heavily doped region doping concentration of 1 o18~1 〇2〇cm3;

[0052] 在沟槽内纵向对应于漂移区8的区域内填充High K介质5,相对介电常数为100〜 1000;横向上High K介质的宽度为〇.2〜5um; [0052] The longitudinal direction corresponds to the region in the trench in the drift region 8 filled with High K medium 5, a relative dielectric constant 100~ 1000; High K transverse width 〇.2~5um medium;

[0053] 在基区上掺杂分别形成源区11和沟道衬底接触10; [0053] doped region are formed on the base region 11 and the source-channel substrate contact 10;

[0054] 对半绝缘多晶硅层3表面纵向对应于基区的区域进行高浓度掺杂(例如1 〇18〜 102°cnf3)并形成栅极4;。 [0054] The surface region 3 corresponds to the longitudinal area of ​​the base semi-insulating polysilicon layer is doped with a high concentration (e.g. 1 〇18~ 102 ° cnf3) and forming a gate electrode 4 ;.

[0055]在源区11和沟道衬底接触10上形成源极1。 [0055] is formed on the source region 11 and the channel substrate 10 in contact with the source electrode 1.

[0056]利用深沟槽技术在VDMOS器件漂移区的侧壁上形成SIP0S层,使其两端分别连接器件的栅电极和漏电极(接至漏区可视为与漏电极连接)AIPOS层中间空隙部分填充High K 材料。 [0056] With the technique for forming deep trenches SIP0S layer on sidewalls of the drift region of the VDMOS device, both ends thereof are connected to the gate electrode of the device and the drain electrode (connected to the drain region may be regarded as connected to the drain electrode) intermediate layer AIPOS High K material filling space portion. 在器件关断时SIP0S和High K组成的复合介质层上具有均匀的电场,通过电场调制作用使得器件漂移区上的整体电场变得均匀,同时复合介质层增加器件耗尽能力,比单纯的只有SIP0S层或只有High K层的情况器件的耗尽能力增强,即大幅度提高了器件漂移区的掺杂浓度在器件导通时具有较低的导通损耗。 Having a composite dielectric layer when the device is turned off and High K SIP0S consisting uniform electric field, an electric field through modulation of the electric field on the device so that the entire drift region becomes uniform, while the composite dielectric layer increases the capacity of the depletion device, only a simple ratio SIP0S depletion layer or only a case where the device capability High K enhancement layer, i.e., greatly improved the doping concentration of the drift region of the device having a lower conduction losses when the device is turned on. 在器件开启时复合介质层在器件漂移区上积累更多的多数载流子,器件的导通电阻进一步降低。 Composite dielectric layer to accumulate more majority carriers in the drift region of the device when the device is turned on, to further reduce the on-resistance of the device.

[0057]以⑽勾道VDMOS为例,具体可以通过以下步骤进行制备: [0057] In an example ⑽-channel VDMOS, may specifically be prepared by the following steps:

[0058] 1)元素半导体材料的衬底作为漏区; Substrate [0058] 1) elemental semiconductor material as a drain region;

[0059] 2)在衬底漏区的外延层上形成N型漂移区; [0059] 2) N-type drift region formed in the epitaxial layer on the drain region of the substrate;

[0060] 3)在N型漂移区上通过离子注入或扩散形成P型基区; [0060] 3) by ion implantation or diffusion of P-type base region formed on the N type drift region;

[0061] 4)在P型基区上刻蚀沟槽,沟槽下方穿过漂移区至衬底漏区;沟槽的深宽比根据器件的漂移区的长度和宽度来确定,漂移区的长度根据击穿电压要求确定;击穿电压要求600V时,则深宽比为15:1〜25:1;击穿电压要求200V时,则深宽比为5: [0061] 4) etching the trench P-type base region, through the drift region to the drain region of the substrate below the trench; aspect ratio of the trench is determined according to the length and width of the drift region of the device, the drift region length is determined by the breakdown voltage requirements; breakdown voltage requirements 600V, the aspect ratio of 15: 1~25: 1; breakdown voltage requirements 200V, the aspect ratios of 5:

[0062] 5)在沟槽侧壁上形成栅绝缘层; [0062] 5) forming a gate insulating layer on the trench sidewalls;

[0063] 6)在栅绝缘层外淀积一层薄的SIP0S层并掺氧; [0063] 6) depositing a thin layer on the outer SIP0S and the gate insulating layer doped with oxygen;

[0064] 7)在沟槽内的纵向漂移区区域内填充High K介质材料; [0064] 7) in the longitudinal direction of the drift zone region trench is filled High K dielectric material;

[0065] 8)在基区通过离子注入分别形成源区和沟道衬底接触; [0065] 8) a source region of the channel is formed by ion implantation of the substrate and contacting the base region, respectively;

[0066] 9)在沟槽内即基区外侧区域通过离子注入对SIP0S层进行高浓度掺杂; [0066] 9) within the trench i.e. outer region of the base layer is SIP0S heavily doped by ion implantation;

[0067] 10)沟槽内部基区区域淀积多晶硅形成栅电极; [0067] 10) inner trench region is deposited a polysilicon base region forming a gate electrode;

[0068] 11)器件表面淀积钝化层,并刻蚀接触孔; [0068] 11) surface of the device is deposited a passivation layer, and etching the contact hole;

[0069] 12)淀积金属并刻蚀形成源极和栅电极; [0069] 12) is deposited and etched to form the source metal and the gate electrode;

[0070] 13)在衬底漏区上形成漏电极。 [0070] 13) a drain electrode formed on the substrate in the drain region. _ _

[0071] 经Sentaurus仿真,本发明提出的新型器件的性能较之于传统器件大幅度提升,当两种器件具有相等的击穿电压时,新型器件的导通电阻降低了60%。 [0071] Sentaurus by simulation, the performance of the new device proposed by the present invention is greatly improved compared to a conventional device, when the two devices has a breakdown voltage equal to the on-resistance of the new device is reduced by 60%.

[0072]当然,本发明中的VDM0S也可以为P型沟道,其结构与N沟道VDM0S等同,这些均应视为属于本申请权利要求的保护范围,在此不再赘述。 [0072] Of course, in the present invention may be VDM0S channel P-type, N-channel structure VDM0S equivalents, which should be regarded as being within the scope of the claims, and is not repeated herein.

[0073]以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明技术原理的前提下,还可以做出若干改进和替换,这些改进和替换的方案也落入本发明的保护范围。 [0073] The above are only preferred embodiments of the present invention, it should be noted that those of ordinary skill in the art, in the art without departing from the principles of the present invention is provided, you can make various modifications and substitutions, these modifications and alternative arrangements may also fall within the scope of the present invention. ~ ~

Claims (10)

1. 一种具有复合介质层纵向双扩散金属氧化物半导体场效应管,包括: 半导体材料的衬底,兼作漏区; 在衬底上外延生长形成的漂移区; 在所述漂移区上表面掺杂形成的左、右两处基区; 在所述基区上部掺杂分别形成的源区和沟道衬底接触; 在所述源区和沟道衬底接触上表面形成的源极; 在所述漏区下表面形成的漏极; 其特征在于: 所述衬底以及漂移区的材料是元素半导体材料;在所述左、右两处基区之间刻蚀有沟槽,沟槽沿纵向穿过漂移区至衬底漏区;沟槽的深宽比根据器件漂移区的长度和宽度确定, 漂移区的长度根据器件的击穿电压要求确定; 在所述沟槽的侧壁依次形成有栅绝缘层、具有掺氧的半绝缘多晶硅层,使半绝缘多晶硅层纵向两端与器件的栅漏两端相连;半绝缘多晶硅层纵向表面对应于基区为重掺杂区域,在该重掺杂区域形成栅 A vertical double diffused metal oxide semiconductor field effect transistor composite dielectric layer, comprising: a substrate of a semiconductor material, also serves as a drain region; a drift region formed by epitaxial growth on a substrate; surface aeration in the drift region hybrid formed left and right two base region; doped source regions are formed in an upper portion of said substrate contact region and a channel base; source surface formed on the source region and the channel substrate contact electrode; in said drain regions formed on the surface of the lower drain; wherein: said substrate material is an element and the drift region of semiconductor material; left in the etched trench between the right two base region along the trench longitudinally through the drift region to the drain region of the substrate; the aspect ratio of trench width and the length of the drift region of the device is determined, the length of the drift region is determined according to the breakdown voltage requirements of the device; sequentially formed in the sidewall of said trench a gate insulating layer, a polysilicon layer having oxygen-doped semi-insulating, so that a semi-insulating polycrystalline silicon layer is connected to the longitudinal ends of the device gate-drain ends; semi-insulating polycrystalline silicon layer corresponding to the base surface of the longitudinal region is heavily doped region, the weight forming a gate region doped ; 在半绝缘多晶硅层的沟槽内填充High K介质,High K介质与漂移区纵向等高。 ; High K dielectric filled trench in the semi-insulating polysilicon layer, the longitudinal contour High K dielectric and the drift region.
2. 根据权利要求1所述的具有复合介质层纵向双扩散金属氧化物半导体场效应管,其特征在于:High K材料的相对介电常数是1〇〇〜2000。 According to claim composite dielectric layer having a vertical double diffused metal oxide semiconductor field effect transistor of claim 1, wherein: a relative dielectric constant of the material is High K 1〇〇~2000.
3. 根据权利要求2所述的具有复合介质层纵向双扩散金属氧化物半导体场效应管,其特征在于:横向上High K介质的宽度是0.2〜5wn。 3. The composite dielectric layer having a vertical double diffused metal oxide semiconductor field effect transistor according to claim 2, wherein: the transverse width of the medium is High K 0.2~5wn.
4. 根据权利要求1所述的具有复合介质层纵向双扩散金属氧化物半导体场效应管,其特征在于:栅绝缘层的厚度根据阈值电压设定,典型值为0.02〜0. lwn。 According to claim having a vertical double diffused metal oxide semiconductor field effect composite dielectric layer pipe of claim 1, wherein: thickness of the gate insulating layer according to the threshold voltage is set, typically 0.02~0 lwn..
5. 根据权利要求1所述的具有复合介质层纵向双扩散金属氧化物半导体场效应管,其特征在于:击穿电压要求600V时,在衬底上外延生长25〜50wn厚的所述漂移区。 According to claim 1 having a composite dielectric layer vertical double diffused metal oxide semiconductor field effect transistor, wherein: the breakdown voltage requirements of the drift region 600V, grown epitaxially on a substrate in a thickness 25~50wn .
6. 根据权利要求1所述的具有复合介质层纵向双扩散金属氧化物半导体场效应管,其特征在于:所述衬底的掺杂浓度典型值为1 X 1013cm_3〜1 X l〇15cnf3。 According to claim having a vertical double diffused metal oxide semiconductor field effect composite dielectric layer pipe of claim 1, wherein: the doping concentration of the substrate is typically 1 X 1013cm_3~1 X l〇15cnf3.
7. 根据权利要求1所述的具有复合介质层纵向双扩散金属氧化物半导体场效应管,其特征在于:所述元素半导体材料为硅材料或者锗材料。 According to claim composite dielectric layer having a vertical double diffused metal oxide semiconductor field effect transistor of claim 1, wherein: said elemental semiconductor material is silicon or germanium material.
8. 根据权利要求1所述的具有复合介质层纵向双扩散金属氧化物半导体场效应管,其特征在于:半绝缘多晶硅层的掺氧比例为15%〜35%,其相应电阻率为109〜10UQ • cm。 According to claim 1 having a vertical double diffused metal oxide semiconductor field effect transistor composite dielectric layer, wherein: the ratio of oxygen-doped semi-insulating polycrystalline silicon layer is 15% ~ 35%, which corresponds to a resistivity of 109~ 10UQ • cm.
9. 根据权利要求8所述的具有复合介质层纵向双扩散金属氧化物半导体场效应管,其特征在于:半绝缘多晶硅层的厚度为0.2〜1.5um。 According to claim 8 having a vertical double diffused metal of the composite dielectric layer of oxide semiconductor field effect transistor, wherein: thickness of the semi-insulating polysilicon layer is 0.2~1.5um.
10.—种制作权利要求1所述具有复合介质层纵向双扩散金属氧化物半导体场效应管的方法,包括以下步骤: 1) 取元素半导体材料的衬底同时作为漏区; 2) 在衬底上形成外延层作为漂移区; 3) 在漂移区上部以离子注入或扩散形成基区; 4) 在基区刻蚀沟槽,使沟槽向下穿过漂移区至漏区; 5) 在沟槽侧壁上形成栅绝缘层; 6) 在栅绝缘层外淀积形成半绝缘多晶硅层; 7) 在沟槽内纵向对应于漂移区的区域填充High K介质; 8) 在基区上掺杂形成源区和沟道衬底接触; 9) 对沟槽内半绝缘多晶硅层表面纵向对应于基区的区域进行重掺杂,并淀积多晶硅形成栅极; 10) 源区和沟道衬底接触表面形成源极; 11) 漏区表面形成漏极。 The method has a longitudinal double diffused metal oxide semiconductor field-effect transistor of the composite dielectric layer 10.- fabricating claim 1, comprising the steps of: a) a semiconductor substrate material, while taking the element region as a drain; 2) in the substrate forming an epitaxial layer on a drift region; 3) at the upper portion of the drift region is formed by ion implantation or diffusion of the base region; 4) etching the trench in the base region, through the drift region of the trench down to the drain region; 5) in the groove the gate insulating layer is formed on the sidewall of the groove; 6) depositing a gate insulating layer is formed on the outer semi-insulating polycrystalline silicon layer; 7) in the trench longitudinal direction corresponds to the drift region a region filled with High K medium; 8) on the base-doped region forming a source region and a channel substrate contact; 9) on the surface of the semi-insulating polysilicon layer within the trench region corresponding to the longitudinal direction of the heavily doped base region, and forming a gate polysilicon is deposited; 10) a source region and a channel substrate forming a source contact surface; 11) forming a drain surface of the drain region.
CN201710623812.5A 2017-07-27 2017-07-27 Longitudinal double-diffused metal oxide semiconductor field-effect tube with composite dielectric layer and preparation method of longitudinal double-diffused metal oxide semiconductor field-effect tube CN107452806A (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4914058A (en) * 1987-12-29 1990-04-03 Siliconix Incorporated Grooved DMOS process with varying gate dielectric thickness
CN102779836A (en) * 2012-07-13 2012-11-14 电子科技大学 Longitudinal power device for low-ratio on-resistance employing groove structure with high dielectric constant

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4914058A (en) * 1987-12-29 1990-04-03 Siliconix Incorporated Grooved DMOS process with varying gate dielectric thickness
CN102779836A (en) * 2012-07-13 2012-11-14 电子科技大学 Longitudinal power device for low-ratio on-resistance employing groove structure with high dielectric constant

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