CN112951141A

CN112951141A - Drive circuit and display panel

Info

Publication number: CN112951141A
Application number: CN202110219221.8A
Authority: CN
Inventors: 杨秀琴; 刘健明; 赵鹏; 王会明; 马京; 贺新月
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Display Lighting Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Display Lighting Co Ltd
Priority date: 2021-02-26
Filing date: 2021-02-26
Publication date: 2021-06-11

Abstract

The invention provides a driving circuit and a display panel, and relates to the technical field of display. The driving circuit provided by the embodiment of the disclosure comprises a power supply sub-circuit, a voltage regulation sub-circuit and a voltage generation sub-circuit, wherein the voltage regulation sub-circuit is connected between the power supply sub-circuit and the voltage generation sub-circuit; the voltage regulation sub-circuit comprises a voltage conversion sub-circuit and a time-sharing control sub-circuit; wherein the voltage conversion sub-circuit is configured to convert a first voltage provided by the power supply sub-circuit into at least two stages of second voltages; the voltage values of the second voltages of all levels are different; the time-sharing control sub-circuit responds to the frame starting signal, and the time-sharing control voltage conversion sub-circuit outputs the corresponding second voltage to the voltage generation sub-circuit; the voltage generation sub-circuit is configured to generate a driving voltage corresponding thereto from the second voltage.

Description

Drive circuit and display panel

Technical Field

The invention belongs to the technical field of display, and particularly relates to a driving circuit and a display panel.

Background

With the development of display industry technology, large-size, high-resolution, high-refresh-rate display panels are gradually taking the mainstream. However, in a display panel with a large size, a high resolution, and a high refresh rate, the charging time of a single sub-pixel is short, and usually the driving circuit is disposed at one side of the display panel, and the data line extends from the driving circuit side to the opposite side of the driving circuit to transmit the data voltage.

Disclosure of Invention

The present invention is directed to at least one of the technical problems in the prior art, and provides a driving circuit, which can output driving voltages with different magnitudes at different time intervals, and when the driving circuit is applied to a display panel, the driving circuit can output different driving voltages to a sub-pixel farther from the driving circuit and a sub-pixel closer to the driving circuit, so as to reduce the charging difference between different sub-pixels and improve the charging uniformity of the display panel.

In a first aspect, an embodiment of the present disclosure provides a driving circuit, including a power supply sub-circuit, a voltage regulation sub-circuit, and a voltage generation sub-circuit, where the voltage regulation sub-circuit is connected between the power supply sub-circuit and the voltage generation sub-circuit;

the voltage regulation subcircuit comprises a voltage conversion subcircuit and a time-sharing control subcircuit; wherein the content of the first and second substances,

the voltage conversion sub-circuit is configured to convert a first voltage provided by the power supply sub-circuit into at least two stages of second voltages; the voltage values of the second voltages at all levels are different;

the time-sharing control sub-circuit responds to a frame starting signal and controls the voltage conversion sub-circuit to output the corresponding second voltage to the voltage generation sub-circuit in a time-sharing mode;

the voltage generation sub-circuit is configured to generate a driving voltage corresponding to the second voltage according to the second voltage.

According to the driving circuit provided by the embodiment of the disclosure, after the first voltage is converted into the multi-stage second voltage through the voltage regulating sub-circuit, the multi-stage second voltage is output to the voltage generating sub-circuit in different time periods, so that the voltage generating sub-circuit generates the corresponding driving voltages in different time periods, and therefore, when the driving circuit is applied to the display panel, the gradually reduced driving voltages can be output to each row of sub-pixels from the side far away from the driving circuit to the side close to the driving circuit, so that the charging difference among different sub-pixels can be reduced, and the overall charging uniformity of the display panel is improved.

In some examples, the power supply sub-circuit is a power management integrated sub-circuit; the voltage regulator sub-circuit is an analog voltage regulator sub-circuit, the voltage converter sub-circuit is an analog voltage converter sub-circuit, and the time-sharing control sub-circuit is a first time-sharing control sub-circuit; the voltage generating sub-circuit is a gamma sub-circuit;

the analog voltage conversion sub-circuit is configured to convert a first analog voltage provided by the power management integrated sub-circuit into at least two stages of second analog voltages; the voltage values of the second analog voltages at all levels are different;

the first time-sharing control sub-circuit responds to a frame starting signal and controls the analog voltage conversion sub-circuit to output the corresponding second analog voltage to the gamma sub-circuit in a time-sharing mode;

the gamma sub-circuit is configured to output a plurality of gamma voltages corresponding thereto according to the second analog voltage.

In some examples, the analog-to-voltage conversion sub-circuit includes n series-connected first resistors; wherein n is the number of second analog voltages of each stage, and n is more than or equal to 2;

when n is 2, the first end of the 1 st first resistor is connected with the power management integrated sub-circuit, and the second end of the 1 st first resistor is connected with the first end of the 2 nd first resistor; the second end of the 2 nd first resistor is connected with a reference voltage end; the first end of the 1 st first resistor is used as the output end of the 1 st-stage second analog voltage, and the first end of the 2 nd first resistor is used as the output end of the 2 nd-stage second analog voltage;

when n is more than 2, the first end of the 1 st first resistor is connected with the power management integrated sub-circuit, the second end of the 1 st first resistor is connected with the first end of the 2 nd first resistor, and the first end of the 1 st first resistor is used as the output end of the 1 st-stage second analog voltage; the first end of the nth first resistor is connected with the second end of the (n-1) th first resistor, and the second end of the nth first resistor is connected with a reference voltage end; the first end of the mth first resistor is connected with the second end of the (m-1) th first resistor, and the second end of the mth first resistor is connected with the first end of the (m +1) th first resistor; the first end of the mth first resistor is used as the output end of the mth-level second analog voltage; wherein 1< m < n.

In some examples, the first time-sharing control circuit includes n first timers and n first transistors; the first timers correspond to the first transistors one to one;

when n is 2, the input end of the 1 st first timer is connected with the frame start signal end, and the output end is connected with the input end of the 2 nd first timer and the control electrode of the first transistor corresponding to the input end; the output end of the 2 nd first timer is connected with the control electrode of the corresponding first transistor;

when n is more than 2, the input end of the 1 st first timer is connected with a frame starting signal end, and the output end of the 1 st first timer is connected with the input end of the 2 nd first timer and the control electrode of the first transistor corresponding to the input end of the 2 nd first timer;

the input end of the mth first timer is connected with the output end of the (m-1) th first timer, and the output end of the mth first timer is connected with the input end of the (m +1) th first timer and the control electrode of the first transistor corresponding to the input end of the (m +1) th first timer;

the input end of the nth first timer is connected with the output end of the (n-1) th first timer, and the output end of the nth first timer is connected with the control electrode of the corresponding first transistor;

the first stage of each first transistor is connected with the output end of the corresponding stage of second analog voltage, and the second stage of each first transistor is connected with the gamma sub-circuit.

In some examples, further comprising: and the source driving sub-circuit is connected with the gamma sub-circuit and is configured to output a source driving voltage corresponding to the gamma voltage output by the gamma sub-circuit.

In some examples, the power supply sub-circuit is a power management integrated sub-circuit; the voltage regulation subcircuit is a grid-on voltage regulation subcircuit, the voltage conversion subcircuit is a grid-on voltage conversion subcircuit, and the time-sharing control subcircuit is a second time-sharing control subcircuit; the voltage generation sub-circuit is a level conversion sub-circuit;

the gate-on voltage conversion sub-circuit is configured to convert a first gate-on voltage provided by the power management integrated sub-circuit into at least two stages of second gate-on voltages; the voltage values of the second gate turn-on voltages of all levels are different;

the second time-sharing control sub-circuit responds to a frame starting signal and controls the gate starting voltage conversion sub-circuit to output the corresponding second gate starting voltage to the level conversion sub-circuit in a time-sharing mode;

the level shift sub-circuit is configured to output a gate shift voltage corresponding thereto according to the second gate-on voltage.

In some examples, the gate-on voltage conversion sub-circuit includes n second resistors connected in series; wherein n is the number of second gate turn-on voltages of each stage, and n is more than or equal to 2;

when n is 2, the first end of the 1 st second resistor is connected with the power management integrated sub-circuit, and the second end is connected with the first end of the 2 nd second resistor; the second end of the 2 nd second resistor is connected with a reference voltage end; the first end of the 1 st second resistor is used as the output end of the 1 st-stage second gate starting voltage, and the first end of the 2 nd second resistor is used as the output end of the 2 nd-stage second gate starting voltage;

when n is larger than 2, the first end of the 1 st second resistor is connected with the power management integrated sub-circuit, the second end of the 1 st second resistor is connected with the first end of the 2 nd second resistor, and the first end of the 1 st second resistor is used as the output end of the 1 st-stage second gate turn-on voltage; the first end of the nth second resistor is connected with the second end of the (n-1) th second resistor, and the second end is connected with a reference voltage end; the first end of the mth second resistor is connected with the second end of the (m-1) th second resistor, and the second end of the mth second resistor is connected with the first end of the (m +1) th second resistor; the first end of the mth second resistor is used as the output end of the mth second gate starting voltage; wherein 1< m < n.

In some examples, the second timing control circuit includes n second timers and n second transistors; the second timers correspond to the second transistors one to one;

when n is 2, the input end of the 1 st second timer is connected with the frame start signal end, and the output end is connected with the input end of the 2 nd second timer and the control electrode of the second transistor corresponding to the input end; the output end of the 2 nd second timer is connected with the control electrode of the corresponding second transistor;

when n is greater than 2, the input end of the 1 st second timer is connected with a frame starting signal end, and the output end of the 1 st second timer is connected with the input end of the 2 nd second timer and the control electrode of the second transistor corresponding to the input end of the 2 nd second timer;

the input end of the mth second timer is connected with the output end of the (m-1) th second timer, and the output end of the mth second timer is connected with the input end of the (m +1) th second timer and the control electrode of the second transistor corresponding to the input end of the (m +1) th second timer;

the input end of the nth second timer is connected with the output end of the (n-1) th second timer, and the output end of the nth second timer is connected with the control electrode of the corresponding second transistor;

the first stage of each second transistor is connected with the output end of the corresponding first-stage second gate starting voltage, and the second stage of each second transistor is connected with the level conversion sub-circuit.

In some examples, further comprising: a timing control sub-circuit and a level shift sub-circuit;

the time sequence control sub-circuit is connected with the power supply sub-circuit and the level conversion sub-circuit; the level conversion sub-circuit is connected with the time-sharing control sub-circuit; the level conversion sub-circuit generates the frame starting signal according to an initial frame starting signal output by the time sequence control sub-circuit.

In a second aspect, an embodiment of the present disclosure further provides a display panel including the driving circuit.

Drawings

Fig. 1 is a schematic structural diagram of an embodiment of a display panel provided in the present disclosure;

fig. 2 is a schematic structural diagram of an embodiment of a driving circuit provided in the present disclosure;

FIG. 3 is an architecture diagram of an embodiment of a driving circuit provided by the embodiments of the present disclosure;

fig. 4 is a circuit structure diagram of an embodiment of a driving circuit provided in the embodiment of the present disclosure;

FIG. 5 is an architecture diagram of another embodiment of a driver circuit provided by an embodiment of the present disclosure;

FIG. 6 is a waveform diagram of another embodiment of a driving circuit provided by the embodiments of the present disclosure;

fig. 7 is a circuit configuration diagram of another embodiment of the driving circuit provided in the embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be described in further detail with reference to the accompanying drawings, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The shapes and sizes of the various elements in the drawings are not to scale and are merely intended to facilitate an understanding of the contents of the embodiments of the invention.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

The disclosed embodiments are not limited to the embodiments shown in the drawings, but include modifications of configurations formed based on a manufacturing process. Thus, the regions illustrated in the figures have schematic properties, and the shapes of the regions shown in the figures illustrate specific shapes of regions of elements, but are not intended to be limiting.

It should be noted that, for convenience of description, the first direction and the second direction are taken as a row direction (X direction) parallel to the lower side of the display substrate, the second direction is taken as a column direction (Y direction) parallel to the right side of the display substrate, and the first direction and the second direction are perpendicular or approximately perpendicular to each other.

Referring to fig. 1, a specific structure of an exemplary display panel is given, taking the display panel 1 as an example, the display panel 1 includes a plurality of sub-pixels arranged in an array, wherein each three sub-pixels with different colors constitute a pixel unit; for example, the pixel unit includes a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. The display panel 1 includes a plurality of DATA lines DATA extending in a first direction (e.g., X direction in fig. 1) and a plurality of GATE lines GATE extending in a second direction (e.g., Y direction in fig. 1), the GATE lines GATE and the DATA lines DATA being arranged to cross and define sub-pixels at crossing positions; the color of the sub-pixels in the same column is the same, every three adjacent sub-pixels along a first direction (X direction in the figure) form a pixel unit, and the three sub-pixels in each pixel unit are respectively a red sub-pixel R, a green sub-pixel G and a blue sub-pixel B; the sub-pixels in each pixel unit in the same row are connected with the same grid line GATE, the sub-pixels in each pixel unit in the same column are connected with the same data line, at least one of the left side and the right side of the display panel can be provided with a GATE Driver on Array (GOA), a plurality of grid lines GATE are connected with a GOA, and the GOA outputs a GATE driving signal to the plurality of grid lines GATE.

On the lower side of the display panel, a plurality of connectors (shown as COFs) are provided, each of which is connected to a plurality of DATA lines DATA, a source driving Circuit S-IC (not shown in fig. 1) is provided on the plurality of connectors, the plurality of connectors are connected to a row direction Printed Circuit board X-PCB, the row direction X-PCB is connected to a driving board 10 through a Flexible Printed Circuit (FPC), and a driving Circuit is provided on the driving board 10. The driving circuit outputs a GATE-on voltage to the GOA, the GOA outputs a GATE driving signal according to the GATE-on voltage to sequentially turn on the GATE lines GATE, the driving circuit provides a source driving voltage to the S-IC to cause the S-IC to output a DATA voltage to the DATA lines DATA, and each DATA line DATA loads the DATA voltage to a row of subpixels corresponding to the turned-on GATE lines GATE. In general, the driving board 10 is disposed at one side of the display panel 1, for example, as shown in fig. 1, the driving board 10 is disposed at the lower side of the display panel 1, in one frame, the GOA drives each row of gate lines to be sequentially refreshed from the opposite side (hereinafter, referred to as DPO side) of the driving circuit to the side (hereinafter, referred to as DP side) close to the driving circuit, for a row of sub-pixels close to the DPO side and a row of sub-pixels close to the DP side, because there is a difference in line length and time for the DATA line DATA to transmit the DATA voltage from the DP side to the row of sub-pixels, the DATA voltage received by the sub-pixels close to the DPO side is smaller than the DATA voltage received by the sub-pixels close to the DP side under the same gray scale, and thus there is a difference in charging rate of each row of sub-pixels on the DP side and the DPO side of the display panel, and the display quality.

In order to solve the above problem, the embodiments of the present disclosure provide a driving circuit, which may be disposed on a driving board 10 as shown in fig. 1, and the specific structure of the driving circuit is described in detail below.

In a first aspect, referring to fig. 2, an embodiment of the present disclosure provides a driving circuit including a power supply sub-circuit 101, a voltage regulation sub-circuit 103, and a voltage generation sub-circuit 103, wherein the voltage regulation sub-circuit 102 is connected between the power supply sub-circuit 101 and the voltage generation sub-circuit 103.

Specifically, the voltage regulation sub-circuit 102 includes a voltage conversion sub-circuit 1021 and a time-sharing control sub-circuit 1022, the voltage conversion sub-circuit 1021 being connected between the power supply sub-circuit 101 and the voltage generation sub-circuit 103, and the time-sharing control sub-circuit 1022 being connected to the voltage conversion sub-circuit 1021. Wherein the power supply sub-circuit 101 provides a first voltage; the voltage conversion sub-circuit 1021 is configured to convert the first voltage provided by the power supply sub-circuit 101 into at least two stages of second voltages, and the voltage values of the stages of second voltages are different; the time-division control sub-circuit 1022 outputs the corresponding second voltage to the voltage generation sub-circuit 101 by the time-division control voltage conversion sub-circuit 1021 in response to the frame start signal STV; the voltage generation sub-circuit 101 is configured to generate a drive voltage corresponding to the second voltage from the second voltage.

In the driving circuit provided by the embodiment of the disclosure, after the first voltage is converted into the multi-level second voltage by the voltage regulating sub-circuit 102, the multi-level second voltage is outputted to the voltage generating sub-circuit 103 in different time periods, so that the voltage generating sub-circuit 103 generates corresponding driving voltages in different time periods, and therefore, when the driving circuit is applied to the display panel, in the process that each row of GATE lines GATE is refreshed from the DPO side to the DP side, the time-sharing control sub-circuit 1022 controls the voltage converting sub-circuit 1021 to output the gradually reduced multi-level second voltage, and correspondingly, the ground voltage generating sub-circuit 103 outputs the gradually reduced multi-level driving voltages, so that the driving voltage received by each sub-pixel at the DPO side can be greater than the driving voltage received by each pixel at the DP side, and further, the charging difference between different sub-pixels can be reduced, and the charging uniformity of the whole display panel can.

It should be noted that the voltage values of the second voltages of the respective stages are different, in some examples, the voltage values of the second voltages of the respective stages may be sequentially decreased, and the second voltage of the 1 st stage is equal to the first voltage, and the second voltages of the subsequent stages are sequentially decreased.

In the display panel, the driving Circuit on the driving board 10 may include a Power Management Integrated Circuit (PMIC), a gamma sub-Circuit (P-GMA), a Timing Controller (T-CON), and a Level Shifter (LS), the driving board 10 may further include an interface (RX)104 for connecting an external Circuit, and the voltage regulator sub-Circuit 102 may be Integrated on the driving board 10 or may be externally disposed outside the driving board 10, which is not limited herein. RX 104 receives an input voltage Vin and transmits the input voltage Vin to PMIC, and PMIC outputs an analog voltage (including an operating analog voltage AVDD and a non-operating analog voltage HAVDD) and transmits the analog voltage to a gamma sub-circuit; the gamma sub-circuit generates corresponding multi-channel gamma voltages according to the analog voltage and transmits the gamma voltages to the gate drive circuit S-IC, the T-CON receives initial interface DATA of a V-by-One interface standard through the RX 104, interface DATA containing a time sequence signal is generated according to a corresponding TV universal standard interface for TV (Universal Serial interface for TV) interface protocol and transmitted to the S-IC, and the S-IC is connected with the gamma voltages and the time sequence signal to generate DATA voltages and transmits the DATA voltages to each DATA line DATA; the PMIC outputs a GATE turn-on voltage (including a turn-on voltage VGH and a turn-off voltage VGL) from an input voltage Vin and transmits the GATE turn-on voltage to the level shift sub-circuit, the T-CON outputs a GATE timing signal G-T to the level shift circuit, the level shift circuit outputs a GATE shift voltage G-S to a GOA in the display panel 1 by combining the GATE turn-on voltage and the GATE timing signal, and the GOA generates a GATE driving signal according to the GATE shift voltage G-S and transmits the GATE driving signal to each GATE line GATE. In addition, the PMIC is also used to transmit a common voltage VCOM to a common electrode within the display panel.

Based on the above, to improve the charge difference of the sub-pixel on the DPO side and the sub-pixel on the DP side, improvement can be mainly made by two ways:

first, the gamma voltage is gradually increased from the DP side to the DPO side. Specifically, in the refresh time of one frame, taking the refresh direction of the display panel from the DPO side to the DP side as an example, the driving circuit outputs a gradually decreasing gamma voltage to the S-IC, so that the S-IC outputs a gradually decreasing DATA voltage, and thus the DATA voltage received by each row of sub-pixels is gradually decreased from the DPO side to the DP side at the same gray level, thereby eliminating the charging difference caused by the parasitic inductance and the line resistance of the DATA line DATA.

In the second method, the gate transition voltage is gradually increased from the DP side to the DPO side. Specifically, in the refresh time of one frame, taking the refresh direction of the display panel from the DPO side to the DP side as an example, the driving circuit outputs a gradually decreasing GATE-on voltage to the level shifter circuit, and the level shifter circuit outputs a gradually decreasing GATE-shift voltage to the GOA according to the GATE-on voltage, so that the GOA outputs a gradually decreasing GATE driving signal.

Of course, in combination with the first and second modes, the driving circuit may output the gradually decreasing gamma voltage to the S-IC and the gradually decreasing gate conversion voltage to the GOA during the refresh time of one frame, which is not limited herein.

In some examples, referring to fig. 3-4, the power supply sub-circuit 101 may be a PMIC, for example, in a manner one; the voltage regulation sub-circuit 102 may be an analog voltage regulation sub-circuit, the voltage conversion sub-circuit 1021 may be an analog voltage conversion sub-circuit 1021a, and the time-sharing control sub-circuit 1022 may be a first time-sharing control sub-circuit 1022 a; the voltage generating sub-circuit 103 may be a gamma sub-circuit 103 a. The analog voltage conversion sub-circuit 1021a is configured to convert a first analog voltage AVDD1 provided by the PMIC 101 into at least two stages of second analog voltages AVDD2, the voltage values of the stages of second analog voltages AVDD2 being different. The first time-division control sub-circuit 1022a controls the analog voltage conversion sub-circuit 1021a to output the corresponding second analog voltage AVDD2 to the gamma sub-circuit 103 in response to the frame start signal STV. The gamma sub-circuit 103 is configured to output a plurality of gamma voltages corresponding to the second analog voltage AVDD according to the second analog voltage AVDD. If the first analog voltage AVDD1 output by the PMIC is a working analog voltage, the second analog voltage AVDD2 of each stage is gradually reduced, and the voltage value of the 1 st-stage second analog voltage AVDD2 is equal to the first analog voltage AVDD 1; if the second analog voltage AVDD2 output by the PMIC is a non-operating voltage, the second analog voltage AVDD2 of each stage gradually increases, and the voltage value of the 1 st stage second analog voltage AVDD2 is equal to the first analog voltage AVDD 1.

In some examples, referring to fig. 4, in particular, in the present embodiment, the analog voltage regulating sub-circuit 102a includes an analog voltage converting sub-circuit 1021a and a first timing control sub-circuit 1022 a.

Specifically, the analog voltage conversion sub-circuit 1021a includes n first resistors R1 connected in series. Wherein n is the number of the second analog voltages AVDD2 of each stage, n is an integer, and n is greater than or equal to 2.

For convenience of description, the 1 st to nth first resistors R1 will be referred to as R1-1, R1-2 … … R1-n, respectively; the generated 1 st-nth-stage second analog voltages AVDD2 are respectively denoted as AVDD2-1, AVDD2-2 … … AVDD 2-n. In the drawings, n-4 is taken as an example, but the invention is not limited.

When n is 2, the first end of the 1 st first resistor R1-1 is connected with the PMIC 101, and the second end of the 1 st first resistor R1-1 is connected with the first end of the 2 nd first resistor R1-2; the second end of the 2 nd first resistor R1-2 is connected with a reference voltage end, and the reference voltage end provides a reference voltage GND; correspondingly, when n is 2, the analog-voltage conversion sub-circuit 1021a outputs two stages of the second analog voltage AVDD2, specifically, the first end of the 1 st first resistor R1-1 is used as the output end of the 1 st stage second analog voltage AVDD2-1, and the first end of the 2 nd first resistor R1-2 is used as the output end of the 2 nd stage second analog voltage AVDD2-2, in order to ensure that the voltage of the second analog voltage AVDD2 of each stage is greater than the reference analog voltage, the resistance value of the 2 nd first resistor R1-2 is much greater than that of the 2 nd first resistor R1-1, for example, 6 Ω may be selected for R1-1, and 1000 Ω may be selected for R1-2, which is not limited herein.

When n is greater than 2, the first end of the 1 st first resistor R1-1 is connected with the PMIC 101, and the second end of the 1 st first resistor R1-1 is connected with the first end of the 2 nd first resistor R1-2; the first end of the nth first resistor R1-n is connected with the second end of the nth-1 first resistor R1- (n-1), the second end of the nth first resistor R1-n is connected with a reference voltage end, and the reference voltage end provides a reference voltage GND; the mth first resistor R1-m is a resistor positioned between the head and the tail, the first end of the mth first resistor R1-m is connected with the second end of the (m-1) th first resistor R1- (m-1), and the second end of the mth first resistor R1-m is connected with the first end of the (m +1) th first resistor R1- (m + 1); the first end of the mth first resistor R1-m is used as the output end of the mth-stage second analog voltage AVDD 2-m; wherein m is an integer and 1< m < n. That is, the first analog voltage AVDD1 generated by the PMIC 101 is input to the analog voltage converting sub-circuit 1021a, and a path between the output terminal of the 1 st-stage second analog voltage AVDD2-1 and the input terminal receiving the first analog voltage AVDD1 has no resistance, so that the size of the 1 st-stage second analog voltage AVDD2-1 is equal to the first analog voltage AVDD1, and then the first analog voltage AVDD1 outputs a stage of second analog voltage AVDD2 after passing through each first resistor, so that the second analog voltage AVDD2 is gradually reduced. Taking n as an example of 4, the resistance values of the 1 st to 4 th first resistors R1-1 to R1-4 may be 6 Ω, and 1000 Ω, respectively, and the voltage values of the 1 st to 4 th second analog voltages AVDD2-1 to AVDD2-4 may be 17.5V, 17.4V, 17.3V, and 17.2V, respectively, but the present invention is not limited thereto.

In some examples, referring to fig. 4, in particular, the first timing control circuit 1022a includes n first timers a1 and n first transistors T1, the first timers a1 corresponding to the first transistors T1 one by one.

For convenience of description, the 1 st to nth first timers A1 will be hereinafter referred to as A1-1, A1-2 … … A1-n, respectively; the 1-nth first transistors T1 are denoted as T1-1, T1-2 … … T1-n, respectively.

When n is 2, the input terminal of the 1 st first timer T1-1 is connected to a frame start signal terminal, which outputs a frame start signal STV, generally, the frame start signal terminal is a level shift circuit, and the output terminal of the 1 st first timer a1-1 is connected to the input terminal of the 2 nd first timer a1-2 and the control electrode of the first transistor T1-1 corresponding to the 1 st first timer a 1-1; the output terminal of the 2 nd first timer A1-2 is connected to the gate of the first transistor T1-2 corresponding to the 2 nd first timer A1-2.

When n > 2, the input terminal of the 1 st first timer a1-1 is connected to the frame start signal terminal, the frame start signal terminal outputs the frame start signal STV, generally, the frame start signal terminal is a level shift circuit, and the output terminal of the 1 st first timer a1-1 is connected to the input terminal of the 2 nd first timer a1-2 and the gate of the first transistor T1-1 corresponding to the 1 st first timer a 1-1.

The input end of the mth first timer A1-m is connected with the output end of the (m-1) th first timer A1- (m-1), and the output end of the mth first timer A1-m is connected with the input end of the (m +1) th first timer A1- (m +1) and the control electrode of the first transistor T1-m corresponding to the (m +1) th first timer A1- (m + 1); wherein m is an integer and 1< m < n.

An input terminal of the nth first timer A1-n is connected to an output terminal of the nth-1 first timer A1- (n-1), and an output terminal of the nth first timer A1-n is connected to a gate of the corresponding first transistor T1-n of the nth first timer A1-n. A first pole of each first transistor T1 is connected to the output terminal of the corresponding stage of the second analog voltage AVDD2, and a second pole of each first transistor T1 is connected to the gamma sub-circuit 103 a.

In a frame, refreshing each row of sub-pixels from a direction from a DPO side to a DP side, a T-CON outputting an initial frame start signal to an LS circuit, the LS circuit converting a frame start signal STV according to the initial frame start signal and outputting to a1 st first timer a1-1 of a first timing control circuit 1022a, the 1 st first timer a1-1 turning on a first transistor T1-1 connected to the 1 st first timer a1-1 within a preset period, so that an output terminal of a1 st-stage second analog voltage AVDD2-1 connected to a first pole of the first transistor T1-1 is gated, and the 1 st-stage second analog voltage AVDD2-1 is transmitted to a gamma sub-circuit 103; after the 1 st first timer a1-1 finishes timing, a signal for starting timing is transmitted to a2 nd first timer a1-2, the 2 nd first timer a1-2 starts a first transistor T1-2 connected to the 2 nd first timer a1-2 within a preset time period, so that an output end of a2 nd-level second analog voltage AVDD2-2 connected to a first pole of the first transistor T1-2 is gated, the 2 nd-level second analog voltage AVDD2-2 is transmitted to the gamma sub-circuit 103 … …, and so on, the preset time period of each first timer a1 is preset, that is, the first timers a1 can be clocked one by one, and corresponding second analog voltages are output to the gamma sub-circuit within the preset time period of each first timer a 1.

In some examples, the driving circuit provided by the embodiment of the present disclosure further includes a source driving sub-circuit S-IC, the source driving sub-circuit S-IC is connected to the gamma sub-circuit, the source driving sub-circuit S-IC receives the gamma voltage output by the gamma sub-circuit and outputs a source driving voltage corresponding to the gamma voltage according to the gamma voltage, and when the gamma voltage increases, the data voltage at each gray level increases accordingly.

In some examples, referring to fig. 5-7, for example, the power supply sub-circuit 101 is a PMIC; the voltage regulation sub-circuit 102 is a gate-on voltage regulation sub-circuit 102b, the voltage conversion sub-circuit 1021 is a gate-on voltage conversion sub-circuit 1021b, and the time-sharing control sub-circuit 1022 is a second time-sharing control sub-circuit 1022 b; the voltage generation sub-circuit 103 is a level shift sub-circuit 103 b; the gate-on voltage conversion sub-circuit 1021a is configured to convert a first gate-on voltage VGH1 provided by the PMIC 101 into at least two stages of second gate-on voltages VGH 2; the voltage values of the second gate turn-on voltages VGH2 of all stages are different; the second timing control sub-circuit 1022b outputs the corresponding second gate-on voltage VGH2 to the level shift sub-circuit 103b in response to the frame start signal STV, the timing control gate-on voltage shift sub-circuit 1021 b. The level shift sub-circuit 103b is configured to output a gate shift voltage G-S corresponding to the second gate-on voltage VGH2 according to the second gate-on voltage VGH 2. If the first gate start voltage VGH1 output by the PMIC is the start voltage, the second gate start voltage VGH2 of each stage is gradually reduced, and the voltage value of the 1 st stage second gate start voltage VGH2 is equal to the first gate start voltage VGH 1; if the second gate-on voltage VGH2 output by the PMIC is the off voltage, the second gate-on voltage VGH2 of each stage gradually increases, and the voltage value of the 1 st stage second gate-on voltage VGH2 is equal to the first gate-on voltage VGH 1.

In some examples, referring to fig. 7, in particular, in the present embodiment, the gate-on voltage adjusting sub-circuit 102b includes a gate-on voltage converting sub-circuit 1021b and a second timing control sub-circuit 1022 b. The gate-on voltage conversion sub-circuit 1021b includes n second resistors R2 connected in series. Wherein n is the number of the second gate turn-on voltages VGH2 of each stage, n is an integer, and n is greater than or equal to 2.

For convenience of description, the 1 st to nth second resistors R2 are hereinafter referred to as R2-1, R2-2 … … R2-n, respectively; the generated 1-n stage second gate-on voltages VGH2 are respectively denoted as VGH2-1, VGH2-2 … … VGH 2-n. In the drawings, n-4 is taken as an example, but the invention is not limited.

When n is 2, the first end of the 1 st second resistor R2-1 is connected with the PMIC 101, and the second end of the 1 st second resistor R2-1 is connected with the first end of the 2 nd second resistor R2-2; the second end of the 2 nd second resistor R2-2 is connected with a reference voltage end, and the reference voltage end provides a reference voltage GND; correspondingly, when n is 2, the gate-on voltage conversion sub-circuit 1021b outputs the two-stage second gate-on voltage VGH2, specifically, the first end of the 1 st second resistor R2-1 is used as the output end of the 1 st stage second gate-on voltage VGH2-1, and the first end of the 2 nd second resistor R2-2 is used as the output end of the 2 nd stage second gate-on voltage VGH2-2, in order to ensure that the voltage of the second gate-on voltage VGH2 of each stage is greater than the reference analog voltage, the resistance value of the 2 nd second resistor R2-2 is much greater than that of the 2 nd second resistor R2-1, for example, 6 Ω may be selected for R1-1, and 1000 Ω may be selected for R1-2, which is not limited herein.

When n is greater than 2, the first end of the 1 st second resistor R2-1 is connected with the PMIC 101, and the second end of the 1 st second resistor R2-1 is connected with the first end of the 2 nd second resistor R2-2; the first end of the nth second resistor R2-n is connected with the second end of the nth-1 second resistor R2- (n-1), the second end of the nth second resistor R2-n is connected with a reference voltage end, and the reference voltage end provides a reference voltage GND; the mth second resistor R2-m is a resistor positioned between the head and the tail, the first end of the mth second resistor R2-m is connected with the second end of the (m-1) th second resistor R2- (m-1), and the second end of the mth second resistor R2-m is connected with the first end of the (m +1) th second resistor R2- (m + 1); the first end of the mth second resistor R2-m is used as the output end of the mth second gate turn-on voltage VGH 2-m; wherein m is an integer and 1< m < n. That is, the first gate-on voltage VGH1 generated by the PMIC 101 is input to the gate-on voltage conversion sub-circuit 1021b, and a path from the output terminal of the 1 st-stage second gate-on voltage VGH2-1 to the input terminal receiving the first gate-on voltage VGH1 has no resistance, so that the magnitude of the 1 st-stage second gate-on voltage VGH2-1 is equal to the first gate-on voltage VGH1, and then the first gate-on voltage VGH1 outputs a stage of second gate-on voltage VGH2 after passing through one second resistor R2, so that the second gate-on voltage VGH2 of each stage is gradually decreased.

In some examples, referring to fig. 4, in particular, the second timing control circuit 1022b includes n second timers a2 and n second transistors T2, and the second timers a2 are in one-to-one correspondence with the second transistors T2.

For convenience of description, the 1 st to nth second timers A2 will be hereinafter referred to as A2-1, A2-2 … … A2-n, respectively; the 1 st to nth second transistors T2 are denoted as T2-1, T2-2 … … T2-n, respectively.

When n is 2, the input terminal of the 1 st first timer T1-1 is connected to a frame start signal terminal, which outputs a frame start signal STV, generally, the frame start signal terminal is a level shifter circuit, and the output terminal of the 1 st second timer a2-1 is connected to the input terminal of the 2 nd second timer a2-2 and the control electrode of the second transistor T2-1 corresponding to the 1 st second timer a 2-1; the output terminal of the 2 nd second timer A2-2 is connected to the gate of the second transistor T2-2 corresponding to the 2 nd second timer A2-2.

When n > 2, the input terminal of the 1 st second timer a2-1 is connected to the frame start signal terminal, the frame start signal terminal outputs the frame start signal STV, generally, the frame start signal terminal is a level shift circuit, and the output terminal of the 1 st second timer a2-1 is connected to the input terminal of the 2 nd second timer a2-2 and the gate of the second transistor T2-1 corresponding to the 1 st second timer a 2-1.

The input end of the mth second timer A2-m is connected with the output end of the (m-1) th second timer A2- (m-1), and the output end of the mth second timer A2-m is connected with the input end of the (m +1) th second timer A2- (m +1) and the control electrode of the second transistor T2-m corresponding to the (m +1) th second timer A2- (m + 1); wherein m is an integer and 1< m < n.

The input terminal of the nth second timer A2-n is connected to the output terminal of the nth-1 second timer A2- (n-1), and the output terminal of the nth second timer A2-n is connected to the gate of the corresponding second transistor T2-n of the nth second timer A2-n. A first pole of each second transistor T2 is connected to the output terminal of the corresponding primary second gate-on voltage VGH2, and a second pole of each second transistor T2 is connected to the level shifter sub-circuit 103 b.

In a frame, refreshing each row of sub-pixels from the direction from the DPO side to the DP side, the T-CON outputting an initial frame start signal to the LS circuit, the LS circuit converting a frame start signal STV according to the initial frame start signal and outputting to the 1 st second timer a2-1 of the second timing control circuit 1022b, the 1 st second timer a2-1 turning on the second transistor T2-1 connected to the 1 st second timer a2-1 within a preset time period, the output terminal of the 1 st second gate on voltage VGH2-1 connected to the first pole of the second transistor T2-1 is gated, so that the 1 st second gate on voltage VGH2-1 is transmitted to the level conversion sub-circuit 103b and then output to the GOA by the level conversion sub-circuit 103b, and driving the gate line on the DPO side to be turned on; after the 1 st second timer a2-1 finishes timing, a signal for starting timing is transmitted to the 2 nd second timer a2-2, the 2 nd second timer a2-2 starts the second transistor T2-2 connected to the 2 nd second timer a2-2 within a preset time period, an output end of the 2 nd second gate-on voltage VGH2-2 connected to the first pole of the second transistor T2-2 is gated, so that the 2 nd second gate-on voltage VGH2-2 is transmitted to the level conversion sub-circuit 103b … …, and so on, the preset time period of each second timer a2 is preset, that is, the second timers a2 can be clocked one by one, and the corresponding second gate-on voltage VGH2 is output to the level conversion sub-circuit 103b within the preset time period of each second timer a 2.

Referring to fig. 6, taking as an example the driving circuit to which the voltage regulating sub-circuit 102 corresponds in the first and second ways, it can be seen that the gate driving signal Gout corresponding to the sub-pixels from the row 1 (DPO side) to the row 1621 (DP side), the second gate-on voltage VGH2 gradually decreases, and the gamma voltage γ (the gamma voltages at different periods are denoted as γ -1 to γ -4 in fig. 6) gradually decreases.

In some examples, the driving circuit may further include a timing control sub-circuit 104, the timing control sub-circuit 104 is connected to both the power supply sub-circuit 101 and the level shift sub-circuit 103b, and the level shift sub-circuit 103b is connected to the timing control sub-circuit 1022. The timing control sub-circuit 104 outputs an initial frame start signal to the level shift sub-circuit 103b, and the level shift sub-circuit 103b generates a frame start signal STV according to the initial frame start signal output by the timing control sub-circuit 104.

Referring to fig. 1, taking a display panel 1 as an example, the display panel 1 includes a plurality of sub-pixels arranged in an array, wherein each three sub-pixels with different colors form a pixel unit; for example, the pixel unit includes a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. The display panel 1 includes a plurality of DATA lines DATA extending in a first direction (e.g., X direction in fig. 1) and a plurality of GATE lines GATE extending in a second direction (e.g., Y direction in fig. 1), the GATE lines GATE and the DATA lines DATA being arranged to cross and define sub-pixels at crossing positions; the color of the sub-pixels in the same column is the same, every three adjacent sub-pixels along a first direction (X direction in the figure) form a pixel unit, and the three sub-pixels in each pixel unit are respectively a red sub-pixel R, a green sub-pixel G and a blue sub-pixel B; the sub-pixels in each pixel unit in the same row are connected with the same grid line GATE, the sub-pixels in each pixel unit in the same column are connected with the same data line, at least one of the left side and the right side of the display panel can be provided with a GATE Driver on Array (GOA), a plurality of grid lines GATE are connected with a GOA, and the GOA outputs a GATE driving signal to the plurality of grid lines GATE.

On the lower side of the display panel 1, a plurality of connectors (shown as COFs) are provided, each of which is connected to a plurality of DATA lines DATA, a source driving Circuit S-IC (not shown in fig. 1) is provided on the plurality of connectors, the plurality of connectors are connected to a row direction Printed Circuit board X-PCB, the row direction X-PCB is connected to a driving board 10 through a Flexible Printed Circuit (FPC), and a driving Circuit is provided on the driving board 10. The driving circuit outputs a GATE-on voltage to the GOA, the GOA outputs a GATE driving signal according to the GATE-on voltage to sequentially turn on the GATE lines GATE, the driving circuit provides a source driving voltage to the S-IC to cause the S-IC to output a DATA voltage to the DATA lines DATA, and each DATA line DATA loads the DATA voltage to a row of subpixels corresponding to the turned-on GATE lines GATE. The driving board 10 is disposed on one side of the display panel 1, for example, as shown in fig. 1, the driving board 10 is disposed on the lower side of the display panel 1, in one frame, the GOA drives each row of GATE lines to be sequentially refreshed from the opposite side (hereinafter, referred to as DPO side) of the driving circuit to the side close to the driving circuit (hereinafter, referred to as DP side), and under the regulation of the voltage regulating sub-circuit 102 in the driving circuit provided in the embodiment of the present disclosure, the S-IC outputs a gradually decreasing DATA voltage to each DATA line DATA, and/or the GOA outputs a gradually decreasing GATE driving signal to each GATE line GATE, so that the driving voltage received by each sub-pixel on the DPO side can be made larger than the driving voltage received by each pixel on the DP side, thereby reducing the charging difference between different sub-pixels and improving the charging uniformity of the entire display panel.

Alternatively, the display panel may be a liquid crystal display panel or an electroluminescent display panel, such as a liquid crystal panel, an OLED panel, a micro led panel, a MiniLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and any other product or component with a display function.

It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.

Claims

1. A driver circuit, comprising: the voltage regulator comprises a power supply sub-circuit, a voltage regulating sub-circuit and a voltage generating sub-circuit, wherein the voltage regulating sub-circuit is connected between the power supply sub-circuit and the voltage generating sub-circuit;

2. The driving circuit of claim 1, wherein the power supply sub-circuit is a power management integrated sub-circuit; the voltage regulator sub-circuit is an analog voltage regulator sub-circuit, the voltage converter sub-circuit is an analog voltage converter sub-circuit, and the time-sharing control sub-circuit is a first time-sharing control sub-circuit; the voltage generating sub-circuit is a gamma sub-circuit;

3. The driving circuit according to claim 2, wherein the analog voltage conversion sub-circuit comprises n first resistors connected in series; wherein n is the number of second analog voltages of each stage, and n is more than or equal to 2;

4. The drive circuit according to claim 3, wherein the first time-sharing control circuit includes n first timers and n first transistors; the first timers correspond to the first transistors one to one;

and the first pole of each first transistor is connected with the output end of the corresponding first-stage second analog voltage, and the second pole of each first transistor is connected with the gamma sub-circuit.

5. The drive circuit according to claim 2, further comprising: and the source driving sub-circuit is connected with the gamma sub-circuit and is configured to output a source driving voltage corresponding to the gamma voltage output by the gamma sub-circuit.

6. The driving circuit of claim 1, wherein the power supply sub-circuit is a power management integrated sub-circuit; the voltage regulation subcircuit is a grid-on voltage regulation subcircuit, the voltage conversion subcircuit is a grid-on voltage conversion subcircuit, and the time-sharing control subcircuit is a second time-sharing control subcircuit; the voltage generation sub-circuit is a level conversion sub-circuit;

7. The driving circuit according to claim 6, wherein the gate-on voltage converting sub-circuit comprises n second resistors connected in series; wherein n is the number of second gate turn-on voltages of each stage, and n is more than or equal to 2;

8. The drive circuit according to claim 7, wherein the second timing control circuit includes n second timers and n second transistors; the second timers correspond to the second transistors one to one;

9. The driving circuit according to claim 1, further comprising: a timing control sub-circuit and a level shift sub-circuit;

10. A display panel comprising the driver circuit according to any one of claims 1 to 9.