CN114220372A

CN114220372A - Level conversion circuit, power supply integrated circuit, display device, and level conversion method

Info

Publication number: CN114220372A
Application number: CN202111537986.2A
Authority: CN
Inventors: 张跃; 罗建猛
Original assignee: Huizhou Shiwei New Technology Co Ltd
Current assignee: Huizhou Shiwei New Technology Co Ltd
Priority date: 2021-12-15
Filing date: 2021-12-15
Publication date: 2022-03-22
Anticipated expiration: 2041-12-15
Also published as: CN114220372B

Abstract

The application provides a level shift circuit, power integrated circuit, display device and level shift method, wherein, level shift circuit is applied to display device, and display device includes control chip, and level shift circuit includes: the signal receiving port is used for receiving a control signal sent by the control chip; one end of the timer is connected with the signal receiving port, when the signal receiving port receives the control signal, the timer starts timing, and if the timing of the timer meets the preset time, the timer outputs the delayed control signal; and the conversion sub-circuit is connected with the other end of the timer and is used for converting the voltage of the control signal delayed by the timer into VGHD and outputting the VGHD. According to the embodiment of the application, the timer is additionally arranged in the conversion circuit to delay the control signal, and then the conversion sub-circuit converts and outputs the VGHD, so that the problem that the conventional level conversion circuit cannot output the VGHD voltage is solved.

Description

Level conversion circuit, power supply integrated circuit, display device, and level conversion method

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a level shift circuit, a power supply integrated circuit, a display device, and a level shift method.

Background

In the current technological development, different electronic products may involve different required input voltages, and the scan signal is generally converted from a high level state to a low level state or from a low level state to a high level state through a level conversion circuit. The existing partial display panel needs the level shifter to output the VGHD voltage due to the requirement of the GOA circuit.

However, the conventional level shift circuit cannot output the VGHD voltage, and a delay circuit needs to be added to convert VGH into VGHD through the delay circuit, thereby increasing the cost.

Disclosure of Invention

The embodiment of the application provides a level conversion circuit, a power supply integrated circuit, a display device and a level conversion method, and solves the problem that the conventional level conversion circuit cannot output VGHD voltage.

The embodiment of the application provides a level shift circuit, is applied to display device, display device includes control chip, level shift circuit includes:

the signal receiving port is used for receiving a control signal sent by the control chip;

one end of the timer is connected with the signal receiving port, when the signal receiving port receives the control signal, the timer starts timing, and if the timing of the timer meets the preset time, the timer outputs the delayed control signal;

and the conversion sub-circuit is connected with the other end of the timer and is used for converting the voltage of the control signal delayed by the timer into VGHD and outputting the converted voltage.

Optionally, the conversion sub-circuit includes a first branch and an output end, the first branch includes a first MOS transistor, a gate of the first MOS transistor is connected to the first end of the timer, a source of the first MOS transistor is connected to the high-voltage level, a drain of the first MOS transistor is connected to the output end, and a second end of the timer is connected to the output end.

Optionally, the conversion sub-circuit further includes a second branch circuit, where the second branch circuit includes a second MOS transistor, a gate of the second MOS transistor is connected to a third end of the timer, a source of the second MOS transistor is connected to the low-voltage level, a drain of the second MOS transistor is connected to the output terminal, and a second end of the timer is connected to the output terminal;

when the first MOS tube is disconnected, the second MOS tube is connected, and the voltage of the control signal is converted to a low-voltage level and then output.

Optionally, the conversion sub-circuit further includes a register, and the register is electrically connected to the timer and is used for configuring the preset time of the timer.

The embodiment of the present application further provides a level shift circuit, which is applied to a display device, where the display device includes a control chip, and the level shift circuit includes:

the signal receiving port is used for receiving the control signal delayed by the control chip;

and the conversion sub-circuit is electrically connected with the signal receiving port and is used for converting the voltage of the delayed control signal to VGHD and outputting the voltage.

An embodiment of the present application further provides a power integrated circuit, where the power integrated circuit includes:

a level shifter circuit, such as any one of the level shifters described above, configured to output VGHD;

the P-Gamma chip is used for outputting a Gamma signal;

the power management circuit is electrically connected with the level conversion circuit and is used for outputting a logic level and a reference level to the level conversion circuit; the power management circuit is electrically connected with the P-Gamma chip and used for providing power for the P-Gamma chip.

An embodiment of the present application further provides a display device, where the display device includes:

a display panel;

the power supply integrated circuit is as described above, and the power supply integrated circuit is electrically connected with the display panel.

The embodiment of the present application further provides a level shift method, which is applied to a display device, where the display device includes a display panel, a level shift circuit and a control chip that are electrically connected in sequence, where the level shift circuit includes a signal receiving port, a timer and a shift sub-circuit, and the level shift method includes:

controlling the signal receiving port to receive a control signal sent by the control chip;

when the signal receiving port receives the control signal, controlling the timer to start timing, and if the timing of the timer meets the preset time, controlling the timer to output the delayed control signal;

and controlling the conversion sub-circuit to convert the voltage of the delayed control signal into VGHD and output the VGHD.

The embodiment of the present application further provides a level conversion method, which is applied to a display device, where the display device includes a display panel, a level conversion circuit and a control chip that are electrically connected in sequence, where the level conversion circuit includes a signal receiving port and a conversion sub-circuit, and the level conversion method includes:

the control chip delays the control signal for a preset time and outputs the control signal;

controlling the signal receiving port to receive the delayed control signal of the control chip;

Optionally, before the controlling and controlling chip delays the control signal for a preset time and outputs the control signal, the method further includes:

and identifying the interface type of the display panel, and setting the preset time of the control signal delay according to the interface type.

The beneficial effect of this application lies in: the level shift circuit that this application embodiment provided is including the signal reception port that connects electricity in proper order, timer and conversion sub-circuit, when the control signal that signal reception port receiving control chip sent, the timer begins timing, then output the control signal after the time delay when the timer timing satisfies the preset time, and convert VGHD and output through the conversion sub-circuit with the voltage of the control signal after the time delay, this application embodiment carries out time delay earlier to control signal through increasing the timer in the conversion circuit and then converts VGHD and output through the conversion sub-circuit, the problem that current level shift circuit can't output VGHD voltage has been solved. Compared with the prior art, the delay circuit is not required to be additionally arranged, so that the circuit is simpler, and the cost is saved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the application, and that other drawings can be derived from these drawings by a person skilled in the art without inventive effort.

For a more complete understanding of the present application and its advantages, reference is now made to the following descriptions taken in conjunction with the accompanying drawings. Wherein like reference numerals refer to like parts in the following description.

Fig. 1 is a first structural schematic diagram of a level shift circuit provided in this embodiment;

fig. 2 is a schematic waveform diagram of the VGHD voltage and the VGH voltage in the level shift circuit shown in fig. 1.

Fig. 3 is a schematic diagram of a second structure of the level shifter circuit according to the present embodiment;

fig. 4 is a schematic structural diagram of the display device provided in this embodiment;

fig. 5 is a first flowchart of the level shifting method provided in this embodiment;

fig. 6 is a second flowchart of the level shifting method according to the present embodiment.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

The existing display panel needs to be compatible with an IPS screen or other high refresh rate screens, and part of the display panel needs to output VGHD voltage by a power management end due to the requirement of a GOA circuit. The existing level conversion circuit can not output VGHD voltage, a delay circuit is required to be added, the delay time of the delay circuit is determined by hardware design, the delay time is complex to change, and the BOM cost is high, so that the cost is increased. In addition, the delay circuit may cause a certain error in the high-low level transition, and the stability of the high-low level transition has a great influence on the display quality of the display panel.

Therefore, in order to solve the above-described problems, the present application proposes a level conversion circuit, a power supply integrated circuit, a display device, and a level conversion method. The present application will be further described with reference to the accompanying drawings and embodiments.

Referring to fig. 1, fig. 1 is a first structural schematic diagram of a level shift circuit according to the present embodiment, the present embodiment provides a level shift circuit 100 applied to a display device, the display device includes a control chip, the level shift circuit 100 includes a signal receiving port 10, a timer 20 and a shift sub-circuit 30, one end of the timer 20 is connected to the signal receiving port 10, and the other end of the timer 20 is connected to the shift sub-circuit 30.

The signal receiving port 10 is configured to receive a control signal sent by a control chip. When the signal receiving port 10 receives the control signal, the timer 20 starts timing, and if the timing of the timer 20 satisfies the preset time, the timer 20 outputs the delayed control signal. And is used for converting the voltage of the control signal delayed by the timer 20 to VGHD and outputting the converted voltage. In the embodiment of the application, the timer 20 is added in the conversion circuit to delay the control signal first, and then the conversion sub-circuit 30 converts and outputs the VGHD, so that the problem that the conventional level conversion circuit 100 cannot output the voltage of the VGHD is solved. Compared with the prior art, the delay circuit is not required to be additionally arranged, so that the circuit is simpler, and the cost is saved. In addition, in the embodiment, the timer 20 controls the delay time of the control signal, so that the high and low levels are more accurately switched, and in addition, the timer 20 controls the delay time of the control signal, hardware does not need to be changed according to the change of the delay time, and the cost is further reduced.

The converting sub-circuit 30 includes a first branch 311 and an output end 330, the first branch 311 includes a first MOS transistor 311, a gate of the first MOS transistor 311 is connected to a first end of the timer 20, a source of the first MOS transistor 311 is connected to the high voltage level VGH, a drain of the first MOS transistor 311 is connected to the output end 330, and a second end of the timer 20 is connected to the output end 330. When the control chip sends the control signal to the signal receiving port 10, the timer 20 starts timing, and when the timing of the timer 20 meets the preset time, the timer 20 outputs the control signal delayed by the preset time, and turns on the gate of the first MOS transistor 311 in the conversion sub-circuit 30 and the signal receiving port 10, so that the voltage domain of the control signal is converted to VGHD and then output through the output end 330.

It should be noted that the level shift circuit 100 is applicable to a case where a plurality of output terminals 330 output information when a plurality of signal receiving ports 10 receive control signals. Wherein the number of signal receiving ports 10 receiving the control signal is less than the number of output terminals 330 outputting the information.

Illustratively, when the control signals respectively received by the two signal receiving ports 10 may be CPV1 and CPV2, the output terminal 330 outputs CK1, CK2, CK3, CK4, CK5, CK6, CK7 and CK 8. When the control signal received by the signal receiving port 10 may be LC, the output terminal 330 outputs LC1 and LC 2.

It can be understood that, when the display screen needs to output the VGH level, the preset time of the timer 20 may be set to 0, and when the control chip sends the control signal to the signal receiving port 10, the timer 20 directly turns on the gate of the first MOS transistor 311 in the conversion sub-circuit 30 and the signal receiving port 10, so that the voltage domain of the control signal is converted to the VGH and then output through the output end 330. The level shift circuit 100 provided in the embodiment of the present application can convert the voltage of the control signal to VGHD for output, and also convert the voltage of the control signal to VGH for output, thereby implementing function multiplexing of LS _ OUT and saving LS _ OUT ports.

It should be noted that the voltage value of VGHD is equal to the voltage value of VGH, but the time of VGHD rising is delayed with respect to VGH. Specifically, referring to fig. 2, fig. 2 is a schematic waveform diagram of the VGHD voltage and the VGH voltage in the level shift circuit 100 shown in fig. 1. In some embodiments, the time for the VGHD to rise is between 20ms and 200ms relative to the delay of VGH. The specific delay time needs to be set according to different display panels, and specific limitation is not made here, and only the VGHD required by the output display panel needs to be satisfied.

In some embodiments, the converting sub-circuit 30 further includes a second branch circuit 320, the second branch circuit 320 includes a second MOS transistor 321, a gate of the second MOS transistor 321 is connected to the third terminal of the timer 20, a source of the second MOS transistor 321 is connected to the low voltage level VGL, a drain of the second MOS transistor 321 is connected to the output terminal 330, and a second terminal of the timer 20 is connected to the output terminal 330; when the first MOS transistor 311 is turned off, the second MOS transistor 321 is turned on, and the voltage of the control signal is converted to a low voltage level VGL and then output. When the display screen needs to output the VGL level, the preset time of the timer 20 may be set to 0, and when the control chip sends the control signal to the signal receiving port 10, the timer 20 directly turns on the gate of the second MOS transistor 321 in the conversion sub-circuit 30 and the signal receiving port 10, and turns off the gate of the first MOS transistor 311 and the signal receiving port 10, so that the voltage domain of the control signal is converted to the VGL and then output through the output end 330. The level shift circuit 100 provided in the embodiment of the present application can convert the voltage of the control signal to VGHD for output, and also can convert the voltage of the control signal to VGH for output, and also can convert the voltage of the control signal to VGL for output, thereby realizing function multiplexing of LS _ OUT, saving LS _ OUT ports, and being compatible with IPS screens or other high refresh rate screens.

The converting sub-circuit 30 further comprises a register 50, and the register 50 is electrically connected to the timer 20 and is used for setting the preset time of the timer 20. Different VGHD voltages can be needed by different display panels, and different VGHD voltages need different preset time for VGH delay, so that the VGHD needed by the display panels can be output. In the embodiment of the present application, after the register 50 stores the corresponding preset time, when the display panel corresponds to different display panels, the timer 20 outputs different preset times to the timer 20, so as to delay the preset time of the control signal, and output the VGHD voltage after the first MOS transistor 311 is connected to the signal receiving port 10. The embodiment of the application changes different preset times through the register 50, and compared with the prior art, the register 50 changes the design of the preset time, so that the operation is more flexible and convenient, the corresponding hardware is simpler, and the cost is reduced.

Referring to fig. 3, fig. 3 is a schematic diagram of a second structure of the level shifter circuit according to the present embodiment. The embodiment of the present application further provides a level shift circuit 100, where the level shift circuit 100 is applied to a display device, the display device includes a control chip, the level shift circuit 100 includes a signal receiving port 10 and a shift sub-circuit 30, the signal receiving port 10 is used to receive a control signal delayed by the control chip, and the shift sub-circuit 30 is electrically connected to the signal receiving port 10, and is used to convert a voltage of the delayed control signal to VGHD and output the VGHD. The conversion sub-circuit 30 is any one of the conversion sub-circuits 30 described above, and details thereof are described above and are not repeated herein.

The control chip may be a SOC or a TCON IC. Wherein, SOC is an abbreviation of System on Chip, and is interpreted as "Chip level System", usually abbreviated as "System on Chip". The TCON IC is a logic board, also called a screen driving board, and is a central control board. The control chip is a system or product formed by combining a plurality of integrated circuits with specific functions on one chip, and comprises a complete hardware system and embedded software carried by the hardware system. The control chip sets the time delay of the control signal, so that an additional time delay circuit is not needed, hardware facilities are reduced, and the cost is reduced.

It can be understood that, if the display panel needs the VGH voltage, the control chip directly outputs the control signal to the signal receiving port 10, so that the first MOS transistor 311 and the signal receiving port 10 are connected to output the VGH voltage. It should be noted that the delay time of the control signal needs to be set according to different display panels, and is not specifically limited herein, and the delay time is set according to actual conditions, and only needs to satisfy the voltage required by the output display panel.

It should be noted that the level shift circuit 100 can be applied to a case where one signal receiving port 10 receives a control signal and one output terminal 330 outputs information. Wherein the number of signal receiving ports 10 receiving the control signal is equal to the number of output terminals 330 outputting the information.

Illustratively, when the control signal received by one signal receiving port 10 may be STV, the output terminal 330 outputs STV. When the control signal received by one signal receiving port 10 may be ST, the output terminal 330 outputs ST. When the control signal received by one signal receiving port 10 may be Blink, the output 330 is Blink. Or when the control signal received by one signal receiving port 10 may be Reset, the output terminal 330 outputs Reset.

Referring to fig. 4, fig. 4 is a schematic structural diagram of the display device according to the present embodiment. The embodiment of the present application further provides a power integrated circuit 1000, where the power integrated circuit 1000 includes a level shift circuit 100, a P-Gamma chip 300, and a power management circuit 200. The level shifter circuit 100 is the level shifter circuit 100 described above, and the details thereof are not repeated here.

The level shifter 100 is used for outputting VGHD, and in some embodiments, the level shifter 100 is further used for outputting a GOA signal and the P-Gamma chip 300 is used for outputting a Gamma signal. The power management circuit 200 is electrically connected to the level shifter circuit 100 and is configured to output the logic level and the reference level to the level shifter circuit 100. The power management circuit 200 is electrically connected to the P-Gamma chip 300 and is configured to provide power to the P-Gamma chip 300.

In the embodiment of the present application, the level shifter circuit 100, the P-Gamma chip 300, and the power management circuit 200 are integrated on the power integrated circuit 1000, so that multiple functions can be realized, and the power integrated circuit 1000 is simpler and more portable.

Referring to fig. 4, the embodiment of the present application further provides a display device 1, where the display device 1 includes a display panel 2000, a power integrated circuit 1000, and a control chip 3000. The control chip 3000 is electrically connected to the level shift circuit 100, and inputs a control signal to the level shift circuit 100. The power integrated circuit 1000 is electrically connected to the display panel 2000, and the power integrated circuit 1000 is any one of the power integrated circuits 1000 described above, which is described above and will not be described herein again.

Referring to fig. 5, fig. 5 is a first flowchart of the level shifting method according to the present embodiment. The embodiment of the present application further provides a level shifting method, which is applied to a display device 1, where the display device 1 includes a display panel 2000, a control chip 3000 and a level shifting circuit 100, which are electrically connected in sequence, where the level shifting circuit 100 includes a signal receiving port 10, a timer 20 and a shifting sub-circuit 30, and the specific situation of the display device 1 is described above, and will not be described in detail herein. The specific flow of the level conversion method is as follows:

101. the control signal receiving port receives a control signal sent by the control chip.

The signal interface terminal receives control signals sent by the control chip 3000, wherein the control signals may be CPV1 and CPV2, and the control signals may also be LCs.

102. When the signal receiving port receives the control signal, the control timer starts to time. And if the timing of the timer meets the preset time, controlling the timer to output the delayed control signal.

When the signal receiving port 10 receives the control signal, the control timer 20 starts timing to delay the control signal. If the timing of the timer 20 satisfies the preset time, the timer 20 is controlled to output the delayed control signal. It should be noted that the preset time is set according to different practical situations of the display panel 2000, and is not limited in particular.

It can be understood that, when the control signal is delayed, it is necessary to first identify the interface type of the display panel 2000 and set a preset time for delaying the control signal according to the interface type. Illustratively, when the display panel 2000 needs to receive the VGH voltage, the timer 20 needs to be controlled to count 0.

103. And the control conversion sub-circuit converts the voltage of the delayed control signal into VGHD and outputs the VGHD.

When the timer 20 times to meet the preset time, the timer 20 outputs the delayed control signal, so that the converting sub-circuit 30 is turned on with the timer 20, and the voltage of the delayed control signal is converted to VGHD through the converting sub-circuit 30 and is output through the output port.

The level shift method is applicable to a case where a plurality of output terminals 330 output information when a plurality of signal receiving ports 10 receive control signals. Wherein the number of signal receiving ports 10 receiving the control signal is less than the number of output terminals 330 outputting the information.

Referring to fig. 6, fig. 6 is a second flowchart of the level shifting method according to the present embodiment. The embodiment of the present application further provides a level shifting method, which is applied to a display device 1, where the display device 1 includes a display panel 2000, a control chip 3000 and a level shifting circuit 100, which are electrically connected in sequence, where the level shifting circuit 100 includes a signal receiving port 10 and a shifting sub-circuit 30, and the specific situation of the display device 1 is described above, and will not be described in detail herein. The specific flow of the level conversion method is as follows:

201. and the control chip delays the control signal for a preset time and outputs the control signal.

The control chip 3000 delays the control signal for a preset time and outputs the delayed control signal. The setting time is set according to different actual conditions of the display panel 2000, and is not particularly limited herein.

It can be understood that, when the control signal is delayed, it is necessary to first identify the interface type of the display panel 2000 and set a preset time for delaying the control signal according to the interface type. Illustratively, when the display panel 2000 needs to receive the VGH voltage, the control chip 3000 needs to be controlled to delay the control signal for 0.

202. And the control signal receiving port receives the control signal delayed by the control chip.

The control signal receiving port 10 receives the delayed control signal from the control chip 3000, and inputs the delayed control signal to the first MOS transistor 311 in the conversion sub-circuit 30.

203. And the control conversion sub-circuit converts the voltage of the delayed control signal into VGHD and outputs the VGHD.

The voltage of the delayed control signal is converted to VGHD through the first MOS transistor 311 and the VGH voltage terminal in the conversion sub-circuit 30, and is output through the output port.

It should be noted that the level shifting method can be applied to a case where one signal receiving port 10 receives a control signal and one output terminal 330 outputs information. Wherein the number of signal receiving ports 10 receiving the control signal is equal to the number of output terminals 330 outputting the information.

The embodiment of the application provides a level conversion method, and corresponding delay can be performed on a control signal according to different voltages required by different display panels 2000, so that corresponding VGHD can be obtained, the level conversion mode is simpler and more accurate, the stability of high and low level conversion is improved, and the display quality of the display panels 2000 is remarkably improved.

A level shift circuit, a power supply integrated circuit, a display device, and a level shift method according to embodiments of the present application are described in detail above. The principles and embodiments of the present application have been described herein using specific guidelines, the above examples being provided only to aid in the understanding of the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. A level shift circuit is applied to a display device, the display device comprises a control chip, and the level shift circuit comprises:

2. The circuit of claim 1, wherein the converting sub-circuit comprises a first branch and an output terminal, the first branch comprises a first MOS transistor, a gate of the first MOS transistor is connected to the first terminal of the timer, a source of the first MOS transistor is connected to a high voltage level, a drain of the first MOS transistor is connected to the output terminal, and a second terminal of the timer is connected to the output terminal.

3. The level shift circuit of claim 2, wherein the shift sub-circuit further comprises a second branch circuit, the second branch circuit comprises a second MOS transistor, a gate of the second MOS transistor is connected to a third terminal of the timer, a source of the second MOS transistor is connected to a low voltage level, a drain of the second MOS transistor is connected to the output terminal, and a second terminal of the timer is connected to the output terminal;

4. The circuit of claim 1, wherein the conversion sub-circuit further comprises a register electrically connected to the timer for configuring the preset time of the timer.

5. A level shift circuit is applied to a display device, the display device comprises a control chip, and the level shift circuit comprises:

6. A power supply integrated circuit, comprising:

a level shift circuit as claimed in any one of claims 1 to 4 or claim 5, for outputting VGHD;

the P-Gamma chip is used for outputting a Gamma signal;

7. A display device, characterized in that the display device comprises:

a display panel;

a power supply integrated circuit as claimed in claim 6, the power supply integrated circuit being electrically connected to the display panel.

8. A level conversion method is applied to a display device, and is characterized in that the display device comprises a display panel, a level conversion circuit and a control chip which are electrically connected, wherein the level conversion circuit comprises a signal receiving port, a timer and a conversion sub-circuit, and the level conversion method comprises the following steps:

9. A level conversion method is applied to a display device, and is characterized in that the display device comprises a display panel, a level conversion circuit and a control chip which are electrically connected, wherein the level conversion circuit comprises a signal receiving port and a conversion sub-circuit, and the level conversion method comprises the following steps:

10. The method of claim 9, wherein before the controlling chip delays the controlling signal for a predetermined time and outputs the delayed controlling signal, the method further comprises: