CN112928088A - 与夹和部分地设置在夹下方的导线连接的半导体裸片 - Google Patents

与夹和部分地设置在夹下方的导线连接的半导体裸片 Download PDF

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Publication number
CN112928088A
CN112928088A CN202011409358.1A CN202011409358A CN112928088A CN 112928088 A CN112928088 A CN 112928088A CN 202011409358 A CN202011409358 A CN 202011409358A CN 112928088 A CN112928088 A CN 112928088A
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semiconductor device
clip
contact pad
semiconductor die
main face
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CN202011409358.1A
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M·帕维尔
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

一种半导体器件(10；20)包括：第一载体(11)；第一外部电接触部(12)和第二外部电接触部(13)；第一半导体裸片(14)，其包括：第一主面、与第一主面相反的第二主面、设置在第一主面上的第一接触焊盘(14.1)、设置在第二主面上的第二接触焊盘(14.2)和设置在第二主面上的第三接触焊盘(14.3)，其中，所述第一半导体裸片(14)包括垂直晶体管并以其第一主面设置在第一载体(11)上；夹(15)，其连接第二接触焊盘(14.2)和第二外部电接触部(13)；和第一导线(16)，其与第一外部电接触部(12)连接，其中，第一导线(16)至少部分地设置在夹(15)下方。

Description

与夹和部分地设置在夹下方的导线连接的半导体裸片
技术领域
本公开涉及一种半导体器件以及一种用于制造半导体器件的方法。本公开特别地涉及这样一种半导体器件，所述半导体器件包括两个主面上具有接触焊盘的半导体裸片、与接触焊盘中的一个连接的夹、以及导线，其中，导线至少部分地设置在夹下方。
背景技术
在半导体晶体管器件制造领域，半导体裸片技术的改进使得减小了半导体裸片的尺寸。这使得在裸片顶部上用于将夹焊接或烧结到源电极的空间较小。为了容纳栅极焊线或电流感测焊线，通常必须减小夹的尺寸。这减小了可用于封装体顶侧冷却的面积。
发明内容
本公开的第一方面涉及一种半导体器件，包括：第一载体；第一外部电接触部和第二外部电接触部；第一半导体裸片，其包括：第一主面、与第一主面相反的第二主面、设置在第一主面上的第一接触焊盘、设置在第二主面上的第二接触焊盘和设置在第二主面上的第三接触焊盘，其中，所述第一半导体裸片包括垂直晶体管并以其第一主面设置在第一载体上；夹，其连接第二接触焊盘和第二外部电接触部；和第一导线，其与第一外部电接触部连接，其中，第一导线至少部分地设置在夹下方。
本公开的第二方面涉及一种用于制造半导体器件的方法，包括：提供载体；提供第一和第二外部电接触部；提供半导体裸片，其包括第一主面、与第一主面相反的第二主面、设置在第一主面上的第一接触焊盘和设置在第二主面上的第二接触焊盘，其中，所述半导体裸片包括垂直晶体管；将半导体裸片以其第一主面设置在载体上；提供导线；将导线与第二个外部电接触部连接；提供夹；将夹连接在第二接触焊盘与第一外部电接触部之间；其中，连接导线在连接夹之前进行，所述方法被执行成使得导线与夹电隔离。
附图说明
所包括的附图可提供对实施例的进一步理解，并且附图被并入本说明书中并构成本说明书的一部分。附图示出了实施例，并且与说明书一起用于解释实施例的原理。通过参考以下详细说明，其它实施例和实施例的许多预期的优点将很容易理解，因为参考以下详细说明它们将变得更好理解。
附图的元件不一定相对于彼此成比例。相同的附图标记表示对应的相似部件。
图1A至1C示出了夹和外部电接触部的俯视图(A)、夹的从下面看的视图(B)以及半导体器件的沿图1A中标为A′-A的平面所作的剖视图(C)，在所述半导体器件中，带状形式的绝缘层设置在夹的一部分上。
图2A和2B示出了夹和外部电接触部的俯视图(A)以及半导体器件的沿图2A中标为A'-A的平面所作的剖视图(B)，在所述半导体器件中，绝缘体连接到导线的一部分。
图3A和3B以俯视图(A)和沿图3A中标为A′-A的平面所作的剖视图(B)示出了将包封材料施加到半导体器件上之后的图1A至1C的半导体器件，其中，包封材料被设置成使得夹的上主表面暴露于外部。
图4A和4B以俯视图(A)和沿图4A中标为A′-A的平面所作的剖视图(B)示出了将包封材料施加到半导体器件上之后的图2A和2B的半导体器件，其中，包封材料被设置成使得夹的上主表面暴露于外部。
图5A至5C示出了夹和外部电接触部的俯视图(A)、夹的从下面看的视图(B)以及半导体器件的沿图5A中标为A′-A的平面所作的剖视图(C)，在所述半导体器件中，闭环形式的绝缘层设置在夹的一部分上。
图6示出了封装的半导体器件的剖视图，所述半导体器件包括通过夹与第一半导体裸片电连接的第二半导体裸片，其中，两个半导体裸片均由MOSFET裸片构成。
图7示出了封装的半导体器件的剖视图，所述半导体器件包括第二半导体裸片，其中，第一半导体裸片是IC裸片，第二半导体裸片是MOSFET裸片，IC裸片的焊线被夹覆盖。
图8示出了封装的半导体器件的剖视图，所述半导体器件包括通过夹与第一半导体裸片电连接的第二半导体裸片，其中，两个半导体裸片均由MOSFET裸片构成，第二半导体裸片安装在第二载体上并通过第二焊线连接到外部电接触部，另外的绝缘层设置在第二载体的覆盖第二焊线的部分上，夹的上主面不暴露于外部。
图9示出了封装的半导体器件的剖视图，所述半导体器件类似于图8的半导体器件，不同之处在于，夹的上主面暴露于外部。
图10示出了用于说明根据第二方面的用于制造半导体器件的方法的流程图，其中，所述方法适于制造第一和第二方面的半导体器件。
图11A至11E示出了半导体器件的剖视侧视图的图示，以说明用于制造半导体器件的方法。
具体实施方式
本公开使得可以将焊线放置在裸片上，并且允许将大的夹放置在裸片之上，特别是放置在半导体MOSFET裸片或IGBT裸片的源极或发射极上。例如，这可以通过创建具有选择性减薄区域的夹来实现，焊线可以放置在所述减薄区域之下。为了确保焊线不与夹(处于源极或发射极电势下)形成电接触，可以在将夹组装到裸片上之前将电介质沉积到夹上，或者在组装夹之前将电介质覆盖到焊线上。电介质可以通过喷射或丝网印刷施加到夹上或通过其它分配过程施加。大的夹可以被包覆成型或暴露，以允许高效的双面冷却。
在下面的详细描述中，参考构成说明书的一部分的附图，在附图中通过图示的方式示出了可以实践本公开的特定实施例。在这方面，参考所描述附图的取向使用诸如“顶”、“底”、“前”、“后”、“前导”、“尾后”等方向性术语。因为实施例的构件可以以许多不同的取向定位，所以方向性术语用于说明的目的，而绝不是限制性的。应当理解，在不脱离本公开的范围的情况下，可以利用其它实施例并且可以进行结构或逻辑上的改变。因此，以下详细描述不应被理解为限制性的，本公开的范围由所附权利要求限定。
应当理解，除非另外特别指出，否则本文描述的各种示例性实施例的特征可以彼此组合。
如在本说明书中所采用的，术语“结合”、“附接”、“连接”、“耦合”和/或“电连接/电耦合”并不意味着元件或层必须直接接触在一起；而是可以在“结合”、“附接”、“连接”、“耦合”和/或“电连接/电耦合”的元件之间相应地设置居间元件或居间层。然而，根据本公开，上述术语还可以可选地具有特定含义，即元件或层直接接触在一起，即在“结合”、“附接”、“连接”、“耦合”和/或“电连接/电耦合”的元件之间相应地不设置居间元件或居间层。
此外，部件、元件或材料层形成在或位于表面“之上”中使用的词语“在...之上”在本文中可以用来表示部件、元件或材料层“间接地”位于(例如放置、形成、沉积等在)所述表面上，而允许一个或多个附加部件、元件或层布置在所述表面与所述部件、元件或材料层之间。然而，部件、元件或材料层形成在或位于表面“之上”中使用的词语“在...之上”还可以可选地具有所述部件、元件或材料层“直接地”位于(例如放置、形成、沉积等在)所述表面上、例如与所述表面直接接触的特定含义。
详细说明
图1A至1C示出了尚未被封装的半导体器件10，在所述半导体器件中，带状形式的绝缘层17设置在夹15的一部分上。
图1A至1C的半导体器件10包括：载体11；第一外部电接触部12和第二外部电接触部13；以及第一半导体裸片14，其包括第一主面和与第一主面相反的第二主面、设置在第一主面上的第一接触焊盘14.1、设置在第二主面上的第二接触焊盘14.2和设置在第二主面上的第三接触焊盘14.3，其中，半导体裸片14包括垂直晶体管并且以其第一主面设置在第一载体11上。半导体器件10还包括连接第二接触焊盘14.2和第二外部电接触部13的夹15以及连接在第三接触焊盘14.3与第一外部电接触部12之间的第一导线16，其中，第一导线16设置在夹15下方。
根据半导体器件10的一个实施例，第一导线16完全地设置在夹15下方。第一导线16也可以仅部分地设置在夹下方。
根据半导体器件10的一个实施例，第二接触焊盘14.2被夹15完全覆盖。第二接触焊盘14.2也可以未被夹15完全覆盖。
根据半导体器件10的一个实施例，夹15包括至少设置在第一导线16上方的区域中的腔。换句话说，夹15可以包括厚度不同的部分，其中，腔由相对较薄的区域形成。在图1C中，可以看到夹15的相对较厚的部分与第二接触焊盘14.2连接。该相对较厚的部分在图1B中标记为由黑色边框围绕的矩形区域15.2。夹15可以包括相对较薄的部分，所述相对较薄的部分位于图1B中的正方形区域外并因此形成周向腔。该相对较薄的部分的一部分位于第一导线16上方。也可能是，相对较薄的部分仅由位于导线上方的小矩形部分组成。
根据半导体器件10的一个实施例，绝缘层17设置在夹15的位于第一导线16上方的一部分上。如图1A至1C的实施例中所示，绝缘层17可以具有矩形带的形式，所述带设置在导线上方。如在图1A至1C的实施例中进一步示出的，绝缘层17可以设置形成在夹15中的腔的底部。绝缘层17的目的是防止第一导线16与夹15之间可能的短路。
根据半导体器件10的一个实施例，绝缘层17包括电介质、环氧型电介质、箔和膜中的一种或多种。
根据半导体器件10的一个实施例，绝缘层17具有处于2μm至100μm的范围内的厚度，其中，下限也可以是3μm、4μm、5μm、6μm、7μm、8μm、9μm或10μm，上限也可以是90μm、80μm、70μm、60μm或50μm，所述范围可以特别是5μm至30μm。
根据半导体器件10的一个实施例，载体11以及第一和第二外部电接触部12和13是引线框架的一部分。
图2A和2B示出了尚未被封装的半导体器件20，在所述半导体器件中，绝缘体27连接到第一导线26的一部分。
图2A和2B的半导体器件20以与图1A至1C的半导体器件10类似的方式构造，因此这里不再赘述。与图1A至1C的半导体器件10的区别在于，绝缘体27连接到第一导线16的一部分，其中，绝缘体27也连接到半导体裸片14的第二主面。在此，绝缘体27的目的也是用于防止第一导线16与夹15之间可能的短路。
根据图2A和2B的半导体器件20的一个实施例，绝缘体27还连接到半导体裸片14的侧面和载体11的主面。
根据图2A和2B的半导体器件20的一个实施例，绝缘体27包括电介质和环氧型电介质中的一种或多种。
图3A和3B示出了在将包封材料18施加到图1A至1C的半导体器件10之后获得的半导体器件30。包封材料18可以包括任何种类的树脂材料、特别是环氧树脂材料，并且可以通过例如传递模塑或压缩模塑来施加。如图3A和3B所示，包封材料18被施加成使得其覆盖夹15的侧面，并还填充到载体11、第一、第二外部电接触部12和13、半导体裸片14与夹15之间的内部空间中。更重要的是，包封材料18被施加成使得夹15的上主面暴露于外部。这允许用户在夹15的暴露的上表面上施加散热器，以散发在半导体器件的操作期间产生的热量。此外，还可以使载体11的下主面暴露于外部，从而热量也可以从载体11散发到安装有载体11的PCB或任何其它基体上(双面冷却)。
图4A和4B示出了在将包封材料28施加到图2A和2B的半导体器件20之后获得的半导体器件40。包封材料28以与前面关于包封材料18的段落中描述的相同的方式施加到半导体器件20，因此在此不再赘述。
图5A至5C示出了尚未被封装的半导体器件50。
图5A至5C的半导体器件50以与图1A至1C的半导体器件10类似的方式构造，因此在此不再重复这两个器件之间共有的细节。与图1A至1C的半导体器件10的不同之处在于，绝缘层57具有闭环的形式，所述闭环包括设置在第一导线16上方的部分。类似于图1A至1C的半导体器件10，图5A至5C的半导体器件50还包括周向腔15.1。绝缘层57设置在腔15.1的整个外周的底部上，特别是设置在与矩形区域15.2相邻的环上。环形绝缘层57可以被证明是有利的，因为它可以帮助将临时高压夹与半导体裸片14的下部区域额外地电隔离开。
图6示出了被封装的半导体器件60的剖视图。
图6的半导体器件60包括左侧部分和右侧部分，其中，左侧部分被构造成类似于图3A和3B所示的半导体器件30，因此，使用相同的附图标记，并且在此将不重复其描述。夹在这里用附图标记65表示。夹65还包括腔65.1和设置在该腔的底部上的绝缘层17。在右侧部分中，半导体器件60包括与夹65电连接并且通过夹65与作为第一半导体裸片的半导体裸片14电连接的第二半导体裸片64。第一半导体裸片14和第二半导体裸片64均由MOSFET裸片组成。特别地，两个MOSFET 14和64可以以半桥配置布置，其中，第一MOSFET(14；Q1)将输入电压连接到输出滤波器，第二MOSFET(64；Q2)将地连接到输出滤波器。这两个MOSFET 14和64产生占空比调制的方波，然后对其进行低通滤波，从而产生输出电压。用作同步整流器的第二MOSFET通常被称为“同步FET”，而具有低占空比的第一MOSFET被称为“控制FET”。
特别地，半导体器件60包括：第二载体61；第三外部电接触部62；第二半导体裸片64，其包括第一主面和与第一主面相反的第二主面、设置的在第一主面上的第一接触焊盘64.1，设置在第二主面上的第二接触焊盘64.2和设置在第二主面上的第三接触焊盘64.3，其中，第二半导体裸片64包括垂直晶体管并以其第一接触焊盘64.1连接到夹65。第一接触焊盘64.1是漏极(或集电极)接触焊盘，第二接触焊盘64.2是源(或发射极)接触焊盘。以这种方式，第二半导体裸片64与第一半导体裸片14串联连接，以构建半桥电路。
图7示出了封装的半导体器件70的剖视图。
图7的半导体器件70包括是IC裸片的第一半导体裸片和是MOSFET裸片的第二半导体裸片，并且IC裸片的焊线被夹覆盖。
特别地，图7的半导体器件70包括：第一载体71；第一外部电接触部72和第二外部电接触部(未示出)；第一半导体裸片74，其包括第一主面和与第一主面相反的第二主面、设置在第一主面上的第一接触焊盘74.1、设置在第二主面上的第二接触焊盘74.2，其中，第一半导体裸片74包括IC电路并以其第一接触焊盘74.1设置在第一载体71上。半导体器件70还包括：第二载体78；和第二半导体裸片77，其包括第一主面和与第一主面相反的第二主面、设置在第一主面上的第一接触焊盘77.1、设置在第二主面上的第二接触焊盘77.2和设置在第二主面上的第三接触焊盘77.3。半导体器件70还包括夹75，其中，第二半导体裸片77以其第一接触焊盘77.1连接到夹75，并且夹75连接到第二外部电接触部。
特别地，半导体器件70还包括焊线76，其中，焊线76中的第一个将第二接触焊盘74.2中的第一个与第一外部电接触部72连接，焊线76中的第二个将第二接触焊盘74.2中的第二个与第二载体78连接。两个焊线76都完全布置在夹75下方。夹75还包括腔75.1和设置在腔的底部上的绝缘层79。
特别地，半导体器件70可以如前所述是半桥电路的IC裸片74和同步FET裸片77的组合，其中，IC裸片74控制同步FET裸片77的栅极。
图8示出了封装的半导体器件80的剖视图。
图8的半导体器件80类似于图6的半导体器件60，也包括左侧部分和右侧部分，其中，左侧部分被构造成类似于图3A和3B所示的半导体器件30，因此使用相同的附图标记，并且在此将不再重复对相应元件的描述。夹在这里用附图标记85表示。在右侧部分中，半导体器件80包括第二半导体裸片84，所述第二半导体裸片84与夹85电连接，并且进一步通过夹85与第一半导体裸片14电连接。半导体裸片14和84由MOSFET裸片构成。特别地，两个MOSFET14和84可以再次以半桥配置布置，其中，第一MOSFET裸片14用作Q1晶体管，第二MOSFET裸片84用作Q2晶体管。
特别地，半导体器件80包括：第二载体81；第三外部电接触部82；第二半导体裸片84，其包括第一主面和与第一主面相反的第二主面、设置在第一主面上的第一接触焊盘84.1、设置在第二主面上的第二接触焊盘84..2和设置在第二主面上的第三接触焊盘(未示出)，其中，第二半导体裸片84包括垂直晶体管并以其第一接触焊盘84.1连接到夹85，并且以其第二接触焊盘84.2连接到第二载体81。第一接触焊盘84.1是漏极(或集电极)接触焊盘，第二接触焊盘84.2是源极(或发射极)接触焊盘。以这种方式，第二半导体裸片84与第一半导体裸片14串联连接，以构建半桥电路。
与图6的实施例不同的是，图8的半导体器件80包括第二焊线86，所述第二焊线86被实施用于将第二接触焊盘84.2连接到第三外部电接触部82。特别地，第二载体81包括凹部81.1和设置在凹部81.1的上表面上的第二绝缘层87。凹部81.1和第二绝缘层87设置在第二焊线86之下。
与图6的实施例的进一步不同之处在于，图8的半导体器件80包括包封材料88，所述包封材料88被施加成使得夹85被包覆成型，换句话说，夹85的上主面没有暴露于外部。
图9示出了封装的半导体器件90的剖视图。
图9的半导体器件90类似于图8的半导体器件80，因此主要使用相同的附图标记，并且在此将不再重复对相应元件的描述。与图8的半导体器件80的唯一区别在于，包封材料98被施加成使得夹85的上主面暴露于外部。由于第一和第二载体11和81的下主表面也暴露于外部，因此可以在用户侧进行双面冷却。
图10示出了用于说明根据第二方面的用于制造半导体器件的方法的流程图。
图10的方法100包括：提供载体(110)；提供第一和第二外部电接触部(120)；提供半导体裸片，其包括第一主面和与第一主面相反的第二主面、设置在第一主面上的第一接触焊盘和设置在第二主面上的第二接触焊盘，其中，半导体裸片包括垂直晶体管(130)；将半导体裸片以其第一主面设置在载体上(140)；提供导线(150)；将导线与第二外部电接触部连接(160)；提供夹(170)；将夹连接在第二接触焊盘与第一外部电接触部之间(180)，其中，连接导线在连接夹之前进行(190)。
根据图10的方法100的一个实施例，提供这样的夹，所述夹包括设置在夹的位于导线上方的部分上的绝缘层。
根据图10的方法100的一个实施例，所述方法还包括将绝缘体连接到导线的一部分，其中，绝缘体还连接到第一半导体裸片的第二主面。
图10的方法的其它实施例可以通过将其与以上结合第一方面的半导体器件所提及的实施例或特征中的任何一个组合来形成。
图11A至11E示出了半导体器件的剖视侧视图的图示，以说明用于制造半导体器件的方法，其中，示出了类似于图2中的一个的半导体器件的制造。
图11A示出了包括部分蚀刻的引线框架110的半导体器件的中间产品，所述引线框架110用作要制造的半导体器件的载体。中间产品还包括半导体裸片111，其包括第一上主面和与第一上主面相反的第二下主面、在第二下主面上的第一接触焊盘111.1和在第一上主面上的第二和第三接触焊盘111.2和111.3。半导体裸片111以其第一接触焊盘111.1安装在引线框架110的第一部分上。焊线112连接在第三接触焊盘111.3与引线框架110的第二部分之间。此外，绝缘体113被施加到焊线112的一部分上、第三接触焊盘111.3上、第一上主面的一部分上、半导体裸片111和第一接触焊盘111.1的侧面上、引线框架110的上主面的一部分上(包括在引线框架110的第一部分和第二部分之间形成在引线框架110中的凹部)。
图11B示出了将第一焊膏层114形成在第二接触焊盘111.2上并且将第二焊膏层115形成在引线框架110的第二部分上之后的中间产品。
图11C示出了将夹116施加到第一和第二焊膏层114和115随后进行回流工艺之后的中间产品。
图11D示出了将包封材料117施加到半导体器件上而使得其覆盖夹116的侧面并且还填充到引线框架110、半导体裸片111、夹116和绝缘体113之间的内部空间中之后的中间产品。此外，包封材料117被施加成使得夹116的上主面暴露于外部。
图11E示出了去除引线框架的一部分并从而产生两个分离的引线框架部分110.1和110.2之后的半导体器件。可以通过例如蚀刻或磨削来执行去除。
另外，尽管可能已经相对于几个实施方式中的一个实施方式公开了本公开的一个实施例的特定特征或方面，但是这种特征或方面可以与其它实施方式的一个或多个其它特征或方面组合，这对于任何给定的或特定的应用，可能是期望的和有利的。此外，对于在具体实施方式或权利要求书中使用的术语“包括”、“具有”、“带有”或其其它变体而言，这些术语旨在以类似于术语“包含”的方式是开放式包括。此外，应当理解，本公开的实施例可以以分立电路、部分集成电路或完全集成电路或编程装置实现。而且，术语“示例性”仅意味着示例，而不是最佳或最优的。还应当理解，为了简单和易于理解的目的，以彼此相对的特定尺寸示出了本文所描绘的特征和/或元件，而实际尺寸可能与本文所示出的明显不同。
尽管本文已经图示和描述了特定实施例，但是本领域普通技术人员可以理解，在不脱离本公开的范围的情况下，各种替代和/或等效实施方式可以替代所示出和描述的特定实施例。本申请旨在覆盖本文讨论的特定实施例的任何调整或变型。因此，本公开仅由权利要求及其等同物限制。

Claims (21)

1.一种半导体器件(10；20)，包括：
-第一载体(11)；
-第一外部电接触部(12)和第二外部电接触部(13)；
-第一半导体裸片(14)，其包括：第一主面、与第一主面相反的第二主面、设置在第一主面上的第一接触焊盘(14.1)、设置在第二主面上的第二接触焊盘(14.2)和设置在第二主面上的第三接触焊盘(14.3)，其中，所述第一半导体裸片(14)包括垂直晶体管并以其第一主面设置在第一载体(11)上；
-夹(15)，其连接第二接触焊盘(14.2)和第二外部电接触部(13)；和
-第一导线(16)，其与第一外部电接触部(12)连接，其中，第一导线(16)至少部分地设置在夹(15)下方。
2.根据权利要求1所述的半导体器件(10)，其中
第一导线(16)完全地设置在夹(15)下方。
3.根据权利要求1或2所述的半导体器件(10)，其中
第二接触焊盘(14.2)被夹(15)完全覆盖。
4.根据前述权利要求中任一项所述的半导体器件(10；20)，其中
夹(15)包括设置在导线(16)上方的腔(15.1)。
5.根据前述权利要求中任一项所述的半导体器件(10)，其中，所述半导体器件(10)还包括
-第一绝缘层(17)，其设置在夹(15)的位于导线(16)上方的部分上。
6.根据权利要求5所述的半导体器件(10)，其中
第一绝缘层(17)具有矩形带的形式，所述带设置在导线上方。
7.根据权利要求5所述的半导体器件(50)，其中
第一绝缘层(57)具有闭环的形式，所述闭环包括设置在导线(16)上方的部分。
8.根据前述权利要求中任一项所述的半导体器件(10；20)，其中
导线(16)连接在第三接触焊盘(14.3)与第一外部电接触部(12)之间。
9.根据前述权利要求中任一项所述的半导体器件(60)，其中，所述半导体器件(60)还包括
第二半导体裸片(64)，其与夹(15)电连接并借助于夹(15)与第一半导体裸片(14)电连接。
10.根据前述权利要求中任一项所述的半导体器件(70)，其中，所述半导体器件(70)还包括
第二半导体裸片(74)，其包括至少一个接触焊盘(74.2)，其中，导线(78)连接在所述至少一个接触焊盘(74.2)与第一外部电接触部(72)之间。
11.根据权利要求5-9中任一项所述的半导体器件(80；90)，其中，所述半导体器件(80；90)还包括
第二载体(81)；
第二绝缘层(87)，其设置在第二载体(81)上；
第二半导体裸片(84)，其设置在第二载体(81)上，第二半导体裸片(84)包括至少一个接触焊盘(84.2)；
第三外部电接触部(82)；和
第二导线(86)，其连接在所述至少一个接触焊盘(84.2)与第三外部电接触部(82)之间；
其中，第二绝缘层(87)设置在第二导线(86)之下。
12.根据权利要求5-11中任一项所述的半导体器件(10)，其中
第一绝缘层(17)包括电介质、环氧型电介质、箔和膜中的一种或多种。
13.根据权利要求5-12中任一项所述的半导体器件(10)，其中
第一绝缘层(17)的厚度处于2μm至100μm、特别是5μm至30μm的范围内。
14.根据权利要求1-4中任一项所述的半导体器件(20；30)，其中，所述半导体器件(20；30)还包括
-绝缘体(27)，其连接到导线(16)的一部分，其中，绝缘体(27)还连接到第一半导体裸片(14)的第二主面。
15.根据权利要求14所述的半导体器件(20；30)，其中
绝缘体(27)还连接到第一半导体裸片(12)的侧面和第一载体(11)的主面。
16.根据权利要求14或15所述的半导体器件(20；30)，其中
绝缘体(27)包括电介质和环氧型电介质中的一种或多种。
17.根据前述权利要求中任一项所述的半导体器件(30；40)，其中，所述半导体器件(30；40)还包括
包封材料(18；28)，其中
夹(15；25)包括远离半导体裸片(14)的主面，其中，包封材料(18；28)被设置成使得所述主面暴露于外部。
18.根据权利要求1-16中任一项所述的半导体器件(80)，其中，所述半导体器件(80)还包括
包封材料(84)，其中
夹(85)包括远离半导体裸片(12)的主面，其中，包封材料(84)被设置成使得所述主面不暴露于外部。
19.一种用于制造半导体器件的方法(100)，包括：
-提供载体(110)；
-提供第一和第二外部电接触部(120)；
-提供半导体裸片，其包括第一主面、与第一主面相反的第二主面、设置在第一主面上的第一接触焊盘和设置在第二主面上的第二接触焊盘，其中，所述半导体裸片包括垂直晶体管(130)；
-将半导体裸片以其第一主面设置在载体(140)上；
-提供导线(150)；
-将导线与第二个外部电接触部(160)连接；
-提供夹(170)；
-将夹连接在第二接触焊盘与第一外部电接触部(180)之间；
-其中，连接导线在连接夹之前进行(190)。
20.根据权利要求19所述的方法，其中，所述方法还包括
-提供包括设置在夹的位于导线上方的部分上的绝缘层的夹。
21.根据权利要求19所述的方法，其中，所述方法还包括
-将介电体连接到导线的一部分，其中，介电体还连接到第一半导体裸片的第二主面。
CN202011409358.1A 2019-12-05 2020-12-04 与夹和部分地设置在夹下方的导线连接的半导体裸片 Pending CN112928088A (zh)

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US6566749B1 (en) 2002-01-15 2003-05-20 Fairchild Semiconductor Corporation Semiconductor die package with improved thermal and electrical performance
US20040080028A1 (en) 2002-09-05 2004-04-29 Kabushiki Kaisha Toshiba Semiconductor device with semiconductor chip mounted in package
JP5232367B2 (ja) * 2006-07-12 2013-07-10 ルネサスエレクトロニクス株式会社 半導体装置
KR100891516B1 (ko) * 2006-08-31 2009-04-06 주식회사 하이닉스반도체 적층 가능한 에프비지에이 타입 반도체 패키지와 이를이용한 적층 패키지
US7800208B2 (en) 2007-10-26 2010-09-21 Infineon Technologies Ag Device with a plurality of semiconductor chips
JP4865829B2 (ja) 2009-03-31 2012-02-01 シャープ株式会社 半導体装置およびその製造方法
US9230880B2 (en) * 2014-01-28 2016-01-05 Infineon Technolgies Ag Electronic device and method for fabricating an electronic device
US9972559B2 (en) 2016-05-19 2018-05-15 Hyundai Motor Company Signal block and double-faced cooling power module using the same
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