WO2022236665A1 - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
WO2022236665A1
WO2022236665A1 PCT/CN2021/093006 CN2021093006W WO2022236665A1 WO 2022236665 A1 WO2022236665 A1 WO 2022236665A1 CN 2021093006 W CN2021093006 W CN 2021093006W WO 2022236665 A1 WO2022236665 A1 WO 2022236665A1
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WO
WIPO (PCT)
Prior art keywords
transistor
electrically connected
electrode
pad
semiconductor chip
Prior art date
Application number
PCT/CN2021/093006
Other languages
English (en)
French (fr)
Inventor
王天宇
王晛
Original Assignee
罗姆股份有限公司
王天宇
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 罗姆股份有限公司, 王天宇 filed Critical 罗姆股份有限公司
Priority to DE112021007642.6T priority Critical patent/DE112021007642T5/de
Priority to PCT/CN2021/093006 priority patent/WO2022236665A1/zh
Priority to JP2023568241A priority patent/JP2024516717A/ja
Priority to CN202180097958.5A priority patent/CN117296248A/zh
Publication of WO2022236665A1 publication Critical patent/WO2022236665A1/zh
Priority to US18/500,653 priority patent/US20240071879A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire

Definitions

  • the present disclosure relates to a semiconductor device.
  • a clamping element (the clamping element may be, for example, a clamping transistor or a capacitor) is usually provided on the control electrode of the first transistor used for switching.
  • the clamping element is generally arranged on a PCB (Printed Circuit Board, printed circuit board) board.
  • the distance between the pins of the first transistor and the PCB card is relatively long, so that the distance between the wafer of the first transistor and the clamping element cannot be set to be short, The effect of the clamping element is greatly reduced.
  • the main purpose of the present disclosure is to provide a semiconductor device.
  • an embodiment of the present disclosure provides a semiconductor device, including a sealing body, a first transistor, and a second transistor, wherein the first transistor includes a control electrode, a first terminal, and a second terminal;
  • the first transistor is used to enable current to flow from the first terminal to the second terminal under the control of the potential of its control electrode; the first electrode of the second transistor is connected with the control of the first transistor The electrodes are electrically connected, and the second electrode of the second transistor is electrically connected to the second terminal of the first transistor;
  • the first transistor and the second transistor are sealed by the same sealing body, the control electrode of the first transistor is electrically connected to the first control electrode pin, and the control electrode of the second transistor is connected to the second control electrode pin. Pole pins are electrically connected.
  • the first transistor is an n-type transistor, the first terminal is a first electrode, the first electrode is a drain electrode, the second terminal is a second electrode, and the second electrode is a source electrodes; or,
  • the first transistor is a p-type transistor, the first terminal is a first electrode, the first terminal is a source electrode, the second terminal is a second electrode, and the second terminal is a drain electrode.
  • the semiconductor device described in at least one embodiment of the present disclosure further includes a first chip mounting portion, a second chip mounting portion, a first semiconductor chip, a second semiconductor chip, a first gate pin, and a second gate pin pins; the first chip mounting portion and the second chip mounting portion are insulated from each other; a first transistor is formed on the first semiconductor chip, and a second transistor is formed on the second semiconductor chip;
  • At least a part of the first chip mounting part, at least a part of the second chip mounting part, the first semiconductor chip, and the second semiconductor chip are sealed by the same sealing body;
  • the first semiconductor chip has a first surface and a first back surface opposite to the first surface
  • the second semiconductor chip has a second surface and a second back surface opposite to the second surface
  • a first control electrode pad and a first pad are formed on the first surface of the first semiconductor chip, and the first back surface is electrically connected to the first terminal of the first transistor; the first control electrode The pads are respectively electrically connected to the control electrode of the first transistor and the first control electrode pin, and the first pad is electrically connected to the second terminal of the first transistor;
  • a second control electrode pad and a second pad are formed on the first surface of the second semiconductor chip, and the second back surface is electrically connected to the first electrode of the second transistor; the second control electrode The pads are respectively electrically connected to the control electrode of the second transistor and the second control electrode pin, and the second electrode of the second transistor is electrically connected to the second pad;
  • the first chip mounting portion has a first upper surface, the first semiconductor chip is mounted on the first upper surface of the first chip mounting portion, the first back surface of the first semiconductor chip faces the first an upper surface; the first back surface of the first semiconductor chip is electrically connected to the first chip mounting portion;
  • the second chip mounting portion has a second upper surface, the second semiconductor chip is mounted on the second upper surface of the second chip mounting portion, the second back surface of the second semiconductor chip faces the second The upper surface; the second back surface of the second semiconductor chip is electrically connected to the second chip mounting portion.
  • the second chip mounting portion is electrically connected to the first control electrode pad through a wire; the second pad is electrically connected to the first pad.
  • the second chip mounting part is electrically connected to the first control electrode pin through a wire, and the second pad is electrically connected to the first pad.
  • the semiconductor device described in at least one embodiment of the present disclosure further includes a first electrode pin and a second electrode pin;
  • the first electrode pin is electrically connected to the first pad, and the second electrode pin is electrically connected to the first chip mounting portion.
  • the first chip mounting portion is disposed on a first side of the second chip mounting portion, the conduction current of the first transistor is greater than the conduction current of the second transistor, and the first The turn-on speed of the transistor is greater than the turn-on speed of the second transistor.
  • the semiconductor device described in at least one embodiment of the present disclosure further includes a first chip mounting portion, a second chip mounting portion, a first semiconductor chip, a second semiconductor chip, a first gate pin, and a second gate pin pins; at least a part of the first chip mounting part, at least a part of the second chip mounting part, the first semiconductor chip and the second semiconductor chip are all sealed by the same sealing body; A first transistor is formed on the first semiconductor chip, and a second transistor is formed on the second semiconductor chip;
  • the first semiconductor chip has a first surface and a first back surface opposite to the first surface
  • the second semiconductor chip has a second surface and a second back surface opposite to the second surface
  • a first control electrode pad and a first pad are formed on the first surface of the first semiconductor chip, and the first back surface is electrically connected to the first terminal of the first transistor; the first control electrode The pads are respectively electrically connected to the control electrode of the first transistor and the first control electrode pin, and the first pad is electrically connected to the second terminal of the first transistor;
  • a second control electrode pad and a second pad are formed on the first surface of the second semiconductor chip, and the second back surface is electrically connected to the first electrode of the second transistor; the second control electrode The pads are respectively electrically connected to the control electrode of the second transistor and the second control electrode pin, and the second electrode of the second transistor is electrically connected to the second pad;
  • the first chip mounting portion has a first upper surface, the first semiconductor chip is mounted on the first upper surface of the first chip mounting portion, the first back surface of the first semiconductor chip faces the first an upper surface; the first back surface of the first semiconductor chip is electrically connected to the first chip mounting portion;
  • the second chip mounting portion has a second upper surface and a second lower surface opposite to the second upper surface, and the second chip mounting portion is mounted on the first upper surface of the first chip mounting portion Above, the second chip mounting part is insulated from the first chip mounting part, and the second lower surface of the second chip mounting part faces the first upper surface;
  • the second semiconductor chip is mounted on the second upper surface of the second chip mounting portion, the second back surface of the second semiconductor chip faces the second upper surface; the second back surface of the second semiconductor chip is and electrically connected to the second chip mounting portion.
  • the second chip mounting portion is electrically connected to the first control electrode pad through a wire; the second pad is electrically connected to the first pad.
  • the second chip mounting part is electrically connected to the first control electrode pin through a wire, and the second pad is electrically connected to the first pad.
  • the semiconductor device described in at least one embodiment of the present disclosure further includes a first electrode pin and a second electrode pin;
  • the first electrode pin is electrically connected to the first pad, and the second electrode pin is electrically connected to the first chip mounting portion.
  • the first semiconductor chip is disposed on the first side of the second semiconductor chip, the conduction current of the first transistor is greater than the conduction current of the second transistor, and the conduction current of the first transistor is The turn-on speed is greater than the turn-on speed of the second transistor.
  • the first transistor is a MOSFET made of SiC
  • the second transistor is a MOSFET made of Si.
  • the semiconductor device described in at least one embodiment of the present disclosure further includes a first chip mounting portion, a second chip mounting portion, a first semiconductor chip, a second semiconductor chip, a first gate pin, and a second gate pin pins; the first chip mounting portion and the second chip mounting portion are insulated from each other; a first transistor is formed on the first semiconductor chip, and a second transistor is formed on the second semiconductor chip;
  • At least a part of the first chip mounting part, at least a part of the second chip mounting part, the first semiconductor chip, and the second semiconductor chip are sealed by the same sealing body;
  • the first semiconductor chip has a first surface and a first back surface opposite to the first surface
  • the second semiconductor chip has a second surface and a second back surface opposite to the second surface
  • a first gate pad, at least one first pad, and at least one second pad are formed on the first surface of the first semiconductor chip, and the first gate pad is connected to the first transistor respectively.
  • the control electrode and the first control electrode pin are electrically connected, the first pad is electrically connected to the second terminal of the first transistor, and the second pad is electrically connected to the first terminal of the first transistor ;
  • a second control electrode pad and a third pad are formed on the first surface of the second semiconductor chip, and the second back surface is electrically connected to the first electrode of the second transistor; the second control electrode The pads are respectively electrically connected to the control electrode of the second transistor and the second control electrode pin, and the second electrode of the second transistor is electrically connected to the third pad;
  • the first chip mounting portion has a first upper surface, the first semiconductor chip is mounted on the first upper surface of the first chip mounting portion, the first back surface of the first semiconductor chip faces the first upper surface;
  • the second chip mounting portion has a second upper surface, the second semiconductor chip is mounted on the second upper surface of the second chip mounting portion, the second back surface of the second semiconductor chip faces the second The upper surface; the second back surface of the second semiconductor chip is electrically connected to the second chip mounting portion.
  • the second chip mounting portion is electrically connected to the first control electrode pad through a wire; the third pad is electrically connected to the first pad.
  • the second chip mounting part is electrically connected to the first control electrode pin through a wire
  • the third pad is electrically connected to the first pad
  • the semiconductor device described in at least one embodiment of the present disclosure further includes a first electrode pin and a second electrode pin;
  • the first electrode pin is electrically connected to the first pad, and the second electrode pin is electrically connected to the second pad.
  • the first chip mounting portion is disposed on a first side of the second chip mounting portion, the conduction current of the first transistor is greater than the conduction current of the second transistor, and the first The turn-on speed of the transistor is greater than the turn-on speed of the second transistor.
  • the first transistor is a field effect transistor made of GaN
  • the second transistor is a MOSFET made of Si.
  • both the first chip mounting portion and the second chip mounting portion are disposed on the same substrate;
  • a second distance between the second chip mounting portion and the substrate is greater than a first distance between the first chip mounting portion and the substrate.
  • the second electrode of the second transistor is electrically connected to the second terminal of the first transistor through a wire;
  • the wire includes a first wire part, a second wire part and a third wire part;
  • the first end of the first wire part is electrically connected to the second electrode of the second transistor, the second end of the first wire part is electrically connected to the first end of the second wire part, and the first The second end of the second lead part is electrically connected to the first end of the third lead part, and the second end of the third lead part is electrically connected to the second terminal of the first transistor;
  • the second upper surface of the second chip mounting part is perpendicular to the first lead part
  • the first upper surface of the first chip mounting portion is not perpendicular to the third lead portion.
  • the semiconductor device described in at least one embodiment of the present disclosure further includes a chip mounting portion, a first semiconductor chip, a second semiconductor chip, a first gate pin, and a second gate pin; A first transistor is formed on the semiconductor chip, and a second transistor is formed on the second semiconductor chip;
  • the first semiconductor chip has a first surface opposite to the first surface.
  • a first backside on a side the second semiconductor chip has a second surface and a second backside opposite to the second surface;
  • a first control electrode pad and a first pad are formed on the first surface of the first semiconductor chip, and the first back surface is electrically connected to the first terminal of the first transistor; the first control electrode The pads are respectively electrically connected to the control electrode of the first transistor and the first control electrode pin, and the first pad is electrically connected to the second terminal of the first transistor;
  • a second gate pad, at least one second pad, and at least one third pad are formed on the second surface of the second semiconductor chip, and the second gate pad is connected to the second transistor respectively.
  • the control electrode of the second transistor is electrically connected to the second control electrode pin, the second electrode of the second transistor is electrically connected to the second pad, and the first electrode of the second transistor is electrically connected to the third pad ;
  • the chip mounting portion has an upper surface, the first semiconductor chip is mounted on the upper surface of the chip mounting portion, the first back surface of the first semiconductor chip faces the upper surface; The first back surface is electrically connected to the chip mounting part;
  • the second semiconductor chip is mounted on the upper surface of the chip mounting portion, and the second back surface of the second semiconductor chip faces the upper surface.
  • the third pad is electrically connected to the first control electrode pin through a wire, and the second pad is electrically connected to the first pad.
  • the third pad is electrically connected to the first control electrode pad through a wire, and the second pad is electrically connected to the first pad.
  • the semiconductor device described in at least one embodiment of the present disclosure further includes a first electrode pin and a second electrode pin;
  • the first electrode pin is electrically connected to the first pad, and the second electrode pin is electrically connected to the chip mounting portion.
  • the first semiconductor chip is disposed on the first side of the second semiconductor chip, and the conduction current of the first transistor is greater than the conduction current of the second transistor.
  • the first transistor is a MOSFET made of SiC
  • the second transistor is a field effect transistor made of GaN.
  • a fourth distance between the first semiconductor chip and the chip mounting portion is greater than a third distance between the first semiconductor chip and the chip mounting portion.
  • the second electrode of the second transistor is electrically connected to the second terminal of the first transistor through a wire;
  • the wire includes a first wire part, a second wire part and a third wire part;
  • the first end of the first wire part is electrically connected to the second electrode of the second transistor, the second end of the first wire part is electrically connected to the first end of the second wire part, and the first The second end of the second lead part is electrically connected to the first end of the third lead part, and the second end of the third lead part is electrically connected to the second terminal of the first transistor;
  • a second surface of the second semiconductor chip is perpendicular to the first lead portion
  • the first surface of the first semiconductor chip is not perpendicular to the third lead portion.
  • An embodiment of the present disclosure also provides a semiconductor device, including a sealing body, a first transistor, and a capacitor, wherein the first transistor includes a control electrode, a first terminal, and a second terminal; the capacitor includes a first capacitor electrode and a second capacitive electrode;
  • the first transistor is used to enable current to flow from the first terminal to the second terminal under the control of the potential of its control electrode;
  • the first capacitor electrode is electrically connected to the control electrode of the first transistor ,
  • the second capacitor electrode is electrically connected to the second terminal of the first transistor;
  • Both the first transistor and the capacitor are sealed by the same sealing body, and the control electrode of the first transistor is electrically connected to the first control electrode pin.
  • the first transistor is an n-type transistor, the first terminal is a first electrode, the first electrode is a drain electrode, the second terminal is a second electrode, and the second electrode is a source electrodes; or,
  • the first transistor is a p-type transistor, the first terminal is a first electrode, the first terminal is a source electrode, the second terminal is a second electrode, and the second terminal is a drain electrode.
  • the semiconductor device described in at least one embodiment of the present disclosure further includes a chip mounting portion, a first semiconductor chip, a second semiconductor chip, and a first gate pin; a first gate pin is formed on the first semiconductor chip. a transistor; the capacitor is formed on the second semiconductor chip;
  • At least a part of the chip mounting portion, the first semiconductor chip, and the second semiconductor chip are sealed by the same sealing body;
  • the first semiconductor chip has a first surface and a first back surface opposite to the first surface;
  • the second semiconductor chip has a second surface and a second back surface opposite the second surface;
  • a first control electrode pad and a first pad are formed on the first surface of the first semiconductor chip, and the first back surface is electrically connected to the first terminal of the first transistor; the first control electrode The pads are respectively electrically connected to the control electrode of the first transistor and the first control electrode pin, and the first pad is electrically connected to the second terminal of the first transistor;
  • a first electrode pad and a second electrode pad are formed on the second surface of the second semiconductor chip; the first electrode pad is electrically connected to the first capacitor electrode, and the second electrode pad electrically connected to the second capacitor electrode;
  • the chip mounting portion has an upper surface, the first semiconductor chip is mounted on the upper surface of the chip mounting portion, the first back surface of the first semiconductor chip faces the upper surface; The first back surface is electrically connected to the chip mounting part;
  • the second semiconductor chip is mounted on the upper surface of the chip mounting part, and the second back surface of the second semiconductor chip faces the upper surface;
  • the first electrode pad is electrically connected to the first control electrode pin or the first control electrode pad, and the second electrode pad is electrically connected to the first pad.
  • the semiconductor device described in at least one embodiment of the present disclosure further includes a first electrode pin and a second electrode pin;
  • the first electrode pin is electrically connected to the first pad, and the second electrode pin is electrically connected to the chip mounting portion.
  • the semiconductor device described in at least one embodiment of the present disclosure can ensure better clamping effect and simplify wiring.
  • FIG. 1 is a schematic diagram of a connection relationship between a first transistor and a second transistor included in a semiconductor device according to at least one embodiment of the present disclosure
  • FIG. 2 is a structural diagram of a semiconductor device according to at least one embodiment of the present disclosure
  • FIG. 3 is a structural diagram of a semiconductor device according to at least one embodiment of the present disclosure.
  • Fig. 4 is a sectional view of Fig. 3 along A-A ' direction;
  • FIG. 5 is a structural diagram of a semiconductor device according to at least one embodiment of the present disclosure.
  • FIG. 6 is a structural diagram of a semiconductor device according to at least one embodiment of the present disclosure.
  • FIG. 7 is a structural diagram of a semiconductor device according to at least one embodiment of the present disclosure.
  • FIG. 8 is a structural diagram of a semiconductor device according to at least one embodiment of the present disclosure.
  • FIG. 9 is a structural diagram of a semiconductor device according to at least one embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of the connection relationship between the first transistor and the capacitor included in the semiconductor device according to at least one embodiment of the present disclosure.
  • FIG. 11 is a structural diagram of a semiconductor device according to at least one embodiment of the present disclosure.
  • FIG. 12 is a structural diagram of a switching system including a semiconductor chip according to at least one embodiment of the present disclosure.
  • the transistors used in all the embodiments of the present disclosure may be triodes, thin film transistors or field effect transistors or other devices with the same characteristics.
  • one pole is called the first pole, and the other pole is called the second pole.
  • the control electrode when the transistor is a triode, can be a base, the first electrode can be a collector, and the second electrode can be an emitter; or, the control electrode can be a base pole, the first pole may be an emitter, and the second pole may be a collector.
  • the control electrode when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate, the first electrode may be a drain, and the second electrode may be a source; or, the The control electrode may be a gate, the first electrode may be a source, and the second electrode may be a drain.
  • the semiconductor device includes a sealing body, a first transistor, and a second transistor, wherein the first transistor includes a control electrode, a first terminal, and a second terminal;
  • the first transistor is used to enable current to flow from the first terminal to the second terminal under the control of the potential of its control electrode; the first electrode of the second transistor is connected with the control of the first transistor The electrodes are electrically connected, and the second electrode of the second transistor is electrically connected to the second terminal of the first transistor;
  • Both the first transistor and the second transistor are sealed by the same sealing body, the control electrode of the first transistor is electrically connected to the first control electrode pin, and the control electrode of the second transistor is electrically connected to the second The CONTROL pin is electrically connected.
  • control electrode of the first transistor may be electrically connected to the first control electrode pin through a bonding wire
  • control electrode of the second transistor may be connected to the second control electrode pin.
  • the pole pins can be electrically connected by bonding wires, since voltage signals are provided to the second control pole pins, the interference signal on the loop is also small; the bonding wires are wires.
  • both the first transistor and the second transistor are sealed by the same sealing body, so as to shorten the second transistor and the control electrode of the first transistor to ensure better clamping effect and simplify wiring.
  • the first control electrode pin is at least partially disposed outside the encapsulation body
  • the second control electrode pin is at least partially disposed outside the encapsulation body, but not limited thereto.
  • the sealing body may be made of resin, but not limited thereto.
  • the first transistor is an n-type transistor, the first terminal is a first electrode, the first electrode is a drain electrode, the second terminal is a second electrode, and the second electrode is a source electrodes; or,
  • the first transistor is a p-type transistor, the first terminal is a first electrode, the first terminal is a source electrode, the second terminal is a second electrode, and the second terminal is a drain electrode.
  • the semiconductor device described in at least one embodiment of the present disclosure includes a first transistor M1 and a second transistor M2;
  • the first transistor M1 is used to allow current to flow from the drain electrode D of the first transistor M1 to the source electrode S of the first transistor M1 under the control of the potential of the gate G1;
  • the drain electrode D2 of the second transistor M2 is electrically connected to the gate G1 of the first transistor M1, and the source electrode S2 of the second transistor M2 is electrically connected to the source electrode S of the first transistor M1.
  • M1 and M2 are n-type MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistor, Metal-Oxide-Semiconductor Field-Effect Transistor), but not as limit.
  • the semiconductor device described in at least one embodiment of the present disclosure may further include a first chip mounting portion, a second chip mounting portion, a first semiconductor chip, a second semiconductor chip, a first gate pin and The second gate pin; the first chip mounting part and the second chip mounting part are insulated from each other; a first transistor is formed on the first semiconductor chip, and a first transistor is formed on the second semiconductor chip two transistors;
  • At least a part of the first chip mounting part, at least a part of the second chip mounting part, the first semiconductor chip, and the second semiconductor chip are sealed by the same sealing body;
  • the first semiconductor chip has a first surface and a first back surface opposite to the first surface
  • the second semiconductor chip has a second surface and a second back surface opposite to the second surface
  • a first control electrode pad and a first pad are formed on the first surface of the first semiconductor chip, and the first back surface is electrically connected to the first terminal of the first transistor; the first control electrode The pads are respectively electrically connected to the control electrode of the first transistor and the first control electrode pin, and the first pad is electrically connected to the second terminal of the first transistor;
  • a second control electrode pad and a second pad are formed on the first surface of the second semiconductor chip, and the second back surface is electrically connected to the first electrode of the second transistor; the second control electrode The pads are respectively electrically connected to the control electrode of the second transistor and the second control electrode pin, and the second electrode of the second transistor is electrically connected to the second pad;
  • the first chip mounting portion has a first upper surface, the first semiconductor chip is mounted on the first upper surface of the first chip mounting portion, the first back surface of the first semiconductor chip faces the first an upper surface; the first back surface of the first semiconductor chip is electrically connected to the first chip mounting portion;
  • the second chip mounting portion has a second upper surface, the second semiconductor chip is mounted on the second upper surface of the second chip mounting portion, the second back surface of the second semiconductor chip faces the second The upper surface; the second back surface of the second semiconductor chip is electrically connected to the second chip mounting portion.
  • the semiconductor device described in at least one embodiment of the present disclosure may include two chip mounting parts and two semiconductor chips; a first transistor is formed on the first semiconductor chip, and a first transistor is formed on the second semiconductor chip A second transistor is formed on it; at least a part of the first chip mounting part, at least a part of the second chip mounting part, the first semiconductor chip and the second semiconductor chip are sealed by the same sealing body ;
  • the first transistor may be a MOSFET made of SiC
  • the second transistor may be a MOSFET made of Si, but not limited thereto.
  • the second chip mounting part is electrically connected to the first control electrode pad through a wire, so that the first electrode of the second transistor is electrically connected to the control electrode of the first transistor;
  • the second pad is electrically connected to the first pad, so that the second electrode of the second transistor is electrically connected to the second terminal of the first transistor.
  • the wire between the second chip mounting portion and the first gate pad is short.
  • the second chip-mounting part is electrically connected to the first control pin through a wire, so as to avoid occupying the inner space of the wafer, and make the first electrode of the second transistor and the first
  • the control electrode of the transistor is electrically connected;
  • the second pad is electrically connected to the first pad, so that the second electrode of the second transistor is electrically connected to the second terminal of the first transistor.
  • the wire between the second chip mounting part and the first gate pin is short.
  • the semiconductor device described in at least one embodiment of the present disclosure may further include a first electrode pin and a second electrode pin;
  • the first electrode pin is electrically connected to the first pad, so that the first electrode pin is electrically connected to the second terminal of the first transistor;
  • the second electrode pin is electrically connected to the first chip mounting portion, so that the second electrode pin is electrically connected to the first terminal of the first transistor.
  • the first electrode pins may be at least partially disposed outside the encapsulation body, and the second electrode pins may be at least partially disposed outside the encapsulation body, but not limited thereto.
  • the semiconductor device may include a first transistor, a second transistor, a sealing body F0, a first chip mounting part P1, a second chip mounting part P2, a first semiconductor chip C1 , the second semiconductor chip C2, the first gate pin J01, the second gate pin J02, the first electrode pin J1 and the second electrode pin J2; the first chip mounting part P1 and the second The chip mounting parts P2 are insulated from each other; the first transistor is formed on the first semiconductor chip C1, and the second transistor is formed on the second semiconductor chip C2;
  • the first chip mounting part P1, the second chip mounting part P2, the first semiconductor chip C1 and the second semiconductor chip C2 are sealed by the sealing body F0;
  • the first semiconductor chip C1 has a first surface and a first back surface opposite to the first surface
  • the second semiconductor chip C2 has a second surface and a second surface opposite to the second surface. back;
  • a first gate pad H01 and a first pad H1 are formed on the first surface of the first semiconductor chip C1, and the first back surface is electrically connected to the first terminal of the first transistor;
  • a control electrode pad H01 is electrically connected to the control electrode of the first transistor and the first control electrode pin J01 respectively, and the first pad H1 is electrically connected to the second terminal of the first transistor;
  • a second control electrode pad H02 and a second pad H2 are formed on the first surface of the second semiconductor chip C2, and the second back surface is electrically connected to the first electrode of the second transistor;
  • Two control electrode pads H02 are respectively electrically connected to the control electrode of the second transistor and the second control electrode pin J02, and the second electrode of the second transistor is electrically connected to the second pad H2;
  • the first chip mounting portion P1 has a first upper surface, the first semiconductor chip C1 is mounted on the first upper surface of the first chip mounting portion P1, and the first back surface of the first semiconductor chip C1 faces The first upper surface; the first back surface of the first semiconductor chip C1 is electrically connected to the first chip mounting portion P1, so that the first chip mounting portion P1 is connected to the first terminal of the first transistor electrical connection;
  • the second chip mounting portion P2 has a second upper surface, the second semiconductor chip C2 is mounted on the second upper surface of the second chip mounting portion P2, and the second back surface of the second semiconductor chip C2 faces The second upper surface; the second back surface of the second semiconductor chip C2 is electrically connected to the second chip mounting part P2, so that the second chip mounting part P2 is connected to the first electrode of the second transistor electrical connection;
  • the second chip mounting part P2 is electrically connected to the first control electrode pad H01 through the first wire L1, so that the first electrode of the second transistor is electrically connected to the control electrode of the first transistor, and the The first gate pad H01 is set closer to the second chip mounting part P2, so that the first wire L1 is shorter, so as to ensure the best clamping effect and simplify wiring;
  • the second pad H2 is electrically connected to the first pad H1, so that the second terminal of the first transistor is electrically connected to the second electrode of the second transistor;
  • the first electrode pin J1 is electrically connected to the first pad H1, so that the first electrode pin J1 is electrically connected to the second terminal of the first transistor;
  • the second electrode pin J2 is electrically connected to the first chip mounting part P1, so that the second electrode pin J2 is electrically connected to the first terminal of the first transistor.
  • the gate electrode of the first transistor is the gate, the first terminal of the first transistor is a drain electrode, and the second terminal of the first transistor is a source electrode, so
  • the control electrode of the second transistor is a gate, the first electrode of the second transistor is a drain electrode, and the second electrode of the second transistor is a source electrode, but not limited thereto.
  • the first transistor is a MOSFET made of SiC, and the second transistor may be a MOSFET made of Si; the first chip mounting part P1 is arranged on the second transistor. The right side of the second chip mounting part P2, but not limited thereto. In actual operation, P1 can also be set on the left side of P2.
  • the second transistor is a Miller clamp transistor
  • the second transistor is a Miller clamp transistor
  • the metal plate disposed on the right side forms the first chip mounting portion P1, and the metal plate disposed on the right side forms the second chip mounting portion P2; the first chip mounting portion P1 Formed integrally with the second electrode pin J2, the first chip mounting part P1 is electrically connected to the second electrode pin J2; to separate and separate the second electrode pin J2
  • the first control electrode pin J01 and the first electrode pin J1 are configured in a manner. Specifically, as shown in FIG. 2 , J1 is arranged on the right side of J2, J01 is arranged on the left side of J2, and J02 is arranged on the left side of J01. J02, J01, J2 and J1 are insulated from each other.
  • P1 is set on the right side of P2, and J02, J01, J2, and J1 are arranged in sequence from left to right, so that the distance between the second gate pad H02 on P2 and J02 is Closer, the distance between the first control electrode pad H01 and J01 on P1 is relatively close, and the distance between the first pad H1 and J1 on P1 is relatively close, which is convenient for the connection of H02 and J02, convenient for the connection of H01 and J01, and convenient for the connection of H1 and J1 .
  • the first semiconductor chip C1 is mounted on the first chip mounting portion P1, for example, via a conductive adhesive material composed of silver solder or solder;
  • a MOSFET made of SiC is formed on the first semiconductor chip C1;
  • the first back surface of the first semiconductor chip C1 becomes a drain electrode, and a first control electrode is formed on the first surface of the first semiconductor chip C1.
  • the pad H01 and the first pad H1; that is, the drain electrode of the first transistor is formed on the first back surface of the first semiconductor chip C1, and the first control electrode electrically connected to the gate of the first transistor
  • the pad H01, and the first pad H1 electrically connected to the source electrode of the first transistor are disposed on the first surface of the first semiconductor chip C1.
  • a second semiconductor chip C2 is mounted via a conductive adhesive material composed of silver solder or soldering;
  • a MOSFET made of Si is formed; the second back surface of the second semiconductor chip C2 becomes a drain electrode, and a second control electrode is formed on the first surface of the second semiconductor chip C2.
  • the pad H02, and the second pad H2 electrically connected to the source electrode of the second transistor are disposed on the second surface of the second semiconductor chip C2.
  • the first semiconductor chip C1 since the first semiconductor chip C1 is mounted on the first chip mounting portion P1 via a conductive adhesive material, the first semiconductor chip C1 formed on the back surface of the first semiconductor chip C1
  • the drain electrode of the transistor is electrically connected to the first chip mounting portion P1; since the second semiconductor chip C2 is mounted on the second chip mounting portion P2 via a conductive adhesive material, it is formed on the second conductor chip C2.
  • the drain electrode of the second transistor on the back is electrically connected to the second chip mounting portion P2.
  • the first chip mounting part P1, the second chip mounting part P2, the first semiconductor chip C1, the second semiconductor chip C2, a part of J02, A part of J01, a part of J2, and a part of J1 are sealed by the sealing body F0.
  • (G2) is drawn below J02, which means that J02 can be electrically connected to the gate G2 of the second transistor;
  • G1 is drawn below J01, which means that J01 can be connected to The gate G1 of the first transistor is electrically connected;
  • D) is drawn below J2, which means that J2 can be electrically connected to the drain electrode D of the first transistor;
  • S is drawn below J1, which means J1 It may be electrically connected to the source electrode S of the first transistor.
  • the first chip mounting portion may be disposed on the first side of the second chip mounting portion, and the conduction current of the first transistor is greater than the conduction current of the second transistor. current, the turn-on speed of the first transistor is greater than the turn-on speed of the second transistor.
  • the first side can be the right side or the left side
  • the conduction current of the MOSFET made of SiC is greater than the conduction current of the MOSFET made of Si
  • the MOSFET made of SiC The turn-on speed is greater than that of MOSFETs made of Si.
  • the pin J01 is electrically connected so that the first electrode of the second transistor is electrically connected to the control electrode of the first transistor, and the first control electrode pin J01 is set at a distance from the second chip mounting part P2 closer to make the second wire L2 shorter to ensure the best clamping effect and simplify wiring.
  • the composite part of the connection part required by the lead wire and the pin is changed from the chip to the pin, so that the connection part has a larger connection. area, which also has benefits in terms of manufacturing.
  • Fig. 4 is a sectional view along the direction A-A' of Fig. 3 .
  • the first chip mounting portion P1 is disposed on the first substrate F1
  • the second chip mounting portion P2 is disposed on the second substrate F2;
  • a first semiconductor chip is mounted on the first chip mounting portion P1, and a second semiconductor chip is mounted on the second chip mounting portion P2;
  • a second distance between the second chip mounting portion P2 and the substrate F1 is greater than a first distance L between the first chip mounting portion P1 and the substrate F1;
  • An isolation layer G0 is provided between the second chip mounting portion P2 and the substrate to raise the second chip mounting portion P2 so that the second chip mounting portion P2 is higher than the first chip
  • the mounting portion P1 ; the isolation layer G0 is respectively bonded to the substrate F1 and the second chip mounting portion P2 through an insulating adhesive material.
  • the isolation layer G0 is made of Al2O3, and the first chip mounting part P1 can be disposed on the first substrate F1 through solder paste, but not limited thereto.
  • the second chip mounting portion P2 is higher than the first chip mounting portion P1, so that the second electrode of the second transistor is formed between the second terminal of the first transistor and the second terminal of the first transistor through a wire.
  • the stress on the second transistor can be increased, the stress on the first transistor can be reduced, and the first transistor can be protected.
  • the second electrode of the second transistor (not shown in Figure 4, the second transistor is formed on the second semiconductor chip) is connected to the second terminal of the first transistor ( Not shown in FIG. 4, a first transistor) is electrically connected on the first semiconductor chip;
  • the wire includes a first wire part L11, a second wire part L12 and a third wire part L13;
  • the first end of the first lead part L11 is electrically connected to the second electrode of the second transistor, the second end of the first lead part L11 is electrically connected to the first end of the second lead part L12, The second end of the second lead part L12 is electrically connected to the first end of the third lead part L13, and the second end of the third lead part L13 is electrically connected to the second terminal of the first transistor;
  • the leads connecting the two semiconductor chips are electrically connected to the semiconductor chips once at both ends.
  • the first wire connection is performed on the high-level semiconductor chip, and then the second wire connection is performed on the low-level chip.
  • the surface is perpendicular to the first lead part L11, and the first upper surface of the first chip mounting part P2 is not perpendicular to the third lead part L13, so that the stress on the second transistor is large and the stress on the first transistor is reduced. transistor stress, protecting the first transistor.
  • the semiconductor device described in at least one embodiment of the present disclosure may further include a first chip mounting portion, a second chip mounting portion, a first semiconductor chip, a second semiconductor chip, a first gate pin and the second gate pin; at least a part of the first chip mounting part, at least a part of the second chip mounting part, the first semiconductor chip and the second semiconductor chip are all sealed by the same sealing body sealing; a first transistor is formed on the first semiconductor chip, and a second transistor is formed on the second semiconductor chip;
  • the first semiconductor chip has a first surface and a first back surface opposite to the first surface
  • the second semiconductor chip has a second surface and a second back surface opposite to the second surface
  • a first control electrode pad and a first pad are formed on the first surface of the first semiconductor chip, and the first back surface is electrically connected to the first terminal of the first transistor; the first control electrode The pads are respectively electrically connected to the control electrode of the first transistor and the first control electrode pin, and the first pad is electrically connected to the second terminal of the first transistor;
  • a second control electrode pad and a second pad are formed on the first surface of the second semiconductor chip, and the second back surface is electrically connected to the first electrode of the second transistor; the second control electrode The pads are respectively electrically connected to the control electrode of the second transistor and the second control electrode pin, and the second electrode of the second transistor is electrically connected to the second pad;
  • the first chip mounting portion has a first upper surface, the first semiconductor chip is mounted on the first upper surface of the first chip mounting portion, the first back surface of the first semiconductor chip faces the first an upper surface; the first back surface of the first semiconductor chip is electrically connected to the first chip mounting portion;
  • the second chip mounting portion has a second upper surface and a second lower surface opposite to the second upper surface, and the second chip mounting portion is mounted on the first upper surface of the first chip mounting portion Above, the second chip mounting part is insulated from the first chip mounting part, and the second lower surface of the second chip mounting part faces the first upper surface;
  • the second semiconductor chip is mounted on the second upper surface of the second chip mounting portion, the second back surface of the second semiconductor chip faces the second upper surface; the second back surface of the second semiconductor chip is and electrically connected to the second chip mounting portion.
  • the semiconductor device described in at least one embodiment of the present disclosure further includes a first chip mounting portion, a second chip mounting portion, a first semiconductor chip, a second semiconductor chip, a first gate pin, and a second control pin. a pole pin; a first transistor is formed on the first semiconductor chip, and a second transistor is formed on the second semiconductor chip;
  • At least a part of the first chip mounting part, at least a part of the second chip mounting part, the first semiconductor chip, and the second semiconductor chip are all sealed by the same sealing body;
  • the first semiconductor chip and the second chip mounting portion are mounted on the first chip mounting portion, the first chip mounting portion is insulated from the second chip mounting portion, and the second semiconductor chip is mounted on the on the second chip mounting part.
  • the second chip mounting part is electrically connected to the first control electrode pad through a wire, so that the first electrode of the second transistor is electrically connected to the control electrode of the first transistor;
  • the second pad is electrically connected to the first pad, so that the second electrode of the second transistor is electrically connected to the second terminal of the first transistor.
  • the wire between the second chip mounting portion and the first gate pad is short.
  • the second chip mounting part is electrically connected to the first control electrode pin through a wire, so that the first electrode of the second transistor is electrically connected to the control electrode of the first transistor, and the The second pad is electrically connected to the first pad, so that the second electrode of the second transistor is electrically connected to the second terminal of the first transistor.
  • the wire between the second chip mounting part and the first gate pin is short.
  • the semiconductor device may further include a first electrode pin and a second electrode pin;
  • the first electrode pin is electrically connected to the first pad, so that the first electrode pin is electrically connected to the second terminal of the first transistor;
  • the second electrode pin is electrically connected to the first chip mounting portion, so that the second electrode pin is electrically connected to the first terminal of the first transistor.
  • first electrode pins and the second electrode pins may be at least partially disposed outside the sealing body, but not limited thereto.
  • the semiconductor device described in at least one embodiment of the present disclosure may include a first transistor, a second transistor, a sealing body F0, a first chip mounting part P1, a second chip mounting part P2, a first semiconductor chip C1 , the second semiconductor chip C2, the first gate pin J01, the second gate pin J02, the first electrode pin J1 and the second electrode pin J2; the first chip mounting part P1, the second The chip mounting part P2, the first semiconductor chip C1, and the second semiconductor chip C2 are all sealed by the same sealing body F0; a first transistor is formed on the first semiconductor chip C1, and a first transistor is formed on the first semiconductor chip C1. A second transistor is formed on the second semiconductor chip C2;
  • the first semiconductor chip C1 has a first surface and a first back surface opposite to the first surface
  • the second semiconductor chip C2 has a second surface and a second surface opposite to the second surface. back;
  • a first gate pad H01 and a first pad H1 are formed on the first surface of the first semiconductor chip C1, and the first back surface is electrically connected to the first terminal of the first transistor;
  • a control electrode pad H01 is electrically connected to the control electrode of the first transistor and the first control electrode pin J01 respectively, and the first pad H1 is electrically connected to the second terminal of the first transistor;
  • a second control electrode pad H02 and a second pad H2 are formed on the first surface of the second semiconductor chip C2, and the second back surface is electrically connected to the first electrode of the second transistor;
  • the two control electrode pads H02 are respectively electrically connected to the control electrode of the second transistor and the second control electrode pin J02, and the second electrode of the second transistor is electrically connected to the second pad H2;
  • the first chip mounting portion P1 has a first upper surface, the first semiconductor chip C1 is mounted on the first upper surface of the first chip mounting portion P1, and the first back surface of the first semiconductor chip C1 faces The first upper surface; the first back surface of the first semiconductor chip C1 is electrically connected to the first chip mounting portion P1;
  • the second chip mounting part P2 has a second upper surface and a second lower surface opposite to the second upper surface, and the second chip mounting part P2 is mounted on the first chip mounting part P1.
  • the second chip mounting portion P2 is insulated from the first chip mounting portion P1, and the second lower surface of the second chip mounting portion P2 faces the first upper surface;
  • the second semiconductor chip C2 is mounted on the second upper surface of the second chip mounting part P2, and the second back surface of the second semiconductor chip C2 faces the second upper surface; the second semiconductor chip C2 The second back of the second chip is electrically connected to the second chip mounting part P2;
  • the first electrode pin J1 is electrically connected to the first pad H1, so that the first electrode pin J1 is electrically connected to the second terminal of the first transistor;
  • the second electrode pin J2 is electrically connected to the first chip mounting part P1, so that the second electrode pin J2 is electrically connected to the first terminal of the first transistor;
  • the second chip mounting part P2 is electrically connected to the first control electrode pad H01 through the third wire L3, so that the first electrode of the second transistor is electrically connected to the control electrode of the first transistor, and the The first gate pad H01 is set closer to the second chip mounting part P2, so that the third wire L3 is shorter, so as to ensure the best clamping effect and simplify wiring;
  • the second pad H2 is electrically connected to the first pad H1, so that the second electrode of the second transistor is electrically connected to the second terminal of the first transistor.
  • the gate electrode of the first transistor is the gate, the first terminal of the first transistor is a drain electrode, and the second terminal of the first transistor is a source electrode, so
  • the control electrode of the second transistor is a gate, the first electrode of the second transistor is a drain electrode, and the second electrode of the second transistor is a source electrode, but not limited thereto.
  • the first transistor is a MOSFET made of SiC
  • the second transistor may be a MOSFET made of Si
  • the first chip mounting part P1 is disposed on the second transistor.
  • the first chip mounting part P1 and the second chip mounting part P2 are metal plates; the first chip mounting part P1 is connected to the second electrode pin J2 Formed integrally, the first chip mounting part P1 is electrically connected to the second electrode pin J2; the first control electrode pin J01 and the first control electrode pin J01 are arranged in a manner of separating and interposing the second electrode pin J2 Electrode pin J1. Specifically, as shown in FIG. 5 , J1 is arranged on the right side of J2, J01 is arranged on the left side of J2, and J02 is arranged on the left side of J01. J02, J01, J2 and J1 are insulated from each other.
  • P1 is set on the right side of P2, and J02, J01, J2, and J1 are arranged in sequence from left to right, so that the distance between the second gate pad H02 on P2 and J02 is Closer, the distance between the first control electrode pad H01 and J01 on P1 is relatively close, and the distance between the first pad H1 and J1 on P1 is relatively close, which is convenient for the connection of H02 and J02, convenient for the connection of H01 and J01, and convenient for the connection of H1 and J1 .
  • a first semiconductor chip is mounted via a conductive adhesive material composed of silver solder or soldering.
  • the first gate pad H01 and the first pad H1; that is, the drain electrode of the first transistor is formed on the first back surface of the first semiconductor chip C1, and is electrically connected to the gate of the first transistor.
  • the first gate pad H01 and the first pad H1 electrically connected to the source electrode of the first transistor are disposed on the first surface of the first semiconductor chip C1.
  • the second chip mounting part P2 is disposed on the first upper surface of the first chip mounting part P1, and the second chip mounting part P2 and the first chip
  • the mounting parts P1 are insulated; the second lower surface of the second chip mounting part P2 faces the first upper surface;
  • a second semiconductor chip is mounted via a conductive adhesive material composed of silver solder or soldering. C2; on the second semiconductor chip C2, a MOSFET made of Si is formed; the second back surface of the second semiconductor chip C2 becomes a drain electrode, and a drain electrode is formed on the first surface of the second semiconductor chip C2
  • the second control electrode pad H02 and the second pad H2; that is, the drain electrode of the second transistor is formed on the second back surface of the second semiconductor chip C2, and is electrically connected to the gate of the second transistor
  • the second gate pad H02 of the second transistor, and the second pad H2 electrically connected to the source electrode of the second transistor are disposed on the second surface of the second semiconductor chip C2.
  • the first semiconductor chip C1 since the first semiconductor chip C1 is mounted on the first chip mounting portion P1 via a conductive adhesive material, the first semiconductor chip C1 formed on the back surface of the first semiconductor chip C1
  • the drain electrode of the transistor is electrically connected to the first chip mounting portion P1; since the second semiconductor chip C2 is mounted on the second chip mounting portion P2 via a conductive adhesive material, it is formed on the second conductor chip C2.
  • the drain electrode of the second transistor on the back is electrically connected to the second chip mounting portion P2.
  • the first chip mounting part P1, the second chip mounting part P2, the first semiconductor chip C1, the second semiconductor chip C2, a part of J02, A part of J01, a part of J2, and a part of J1 are sealed by the sealing body F0.
  • the first chip mounting portion may be disposed on the first side of the second chip mounting portion, and the conduction current of the first transistor is greater than the conduction current of the second transistor. current, the turn-on speed of the first transistor is greater than the turn-on speed of the second transistor.
  • the first side can be the right side or the left side
  • the conduction current of the MOSFET made of SiC is greater than the conduction current of the MOSFET made of Si
  • the MOSFET made of SiC The turn-on speed is greater than that of MOSFETs made of Si.
  • (G2) is drawn below J02, which means that J02 can be electrically connected to the gate G2 of the second transistor;
  • G1 is drawn below J01, which means that J01 can be connected to The gate G1 of the first transistor is electrically connected;
  • D) is drawn below J2, which means that J2 can be electrically connected to the drain electrode D of the first transistor;
  • S is drawn below J1, which means J1 It may be electrically connected to the source electrode S of the first transistor.
  • the pin J01 is electrically connected so that the first electrode of the second transistor is electrically connected to the control electrode of the first transistor, and the first control electrode pin J01 is set at a distance from the second chip mounting part P2 closer to make the fourth wire L4 shorter to ensure the best clamping effect and simplify wiring.
  • the semiconductor device described in at least one embodiment of the present disclosure may further include a first chip mounting portion, a second chip mounting portion, a first semiconductor chip, a second semiconductor chip, a first gate pin and the second gate pin; the first chip mounting part and the second chip mounting part are insulated from each other; a first transistor is formed on the first semiconductor chip, and a transistor is formed on the second semiconductor chip second transistor;
  • At least a part of the first chip mounting part, at least a part of the second chip mounting part, the first semiconductor chip, and the second semiconductor chip are sealed by the same sealing body;
  • the first semiconductor chip has a first surface and a first back surface opposite to the first surface
  • the second semiconductor chip has a second surface and a second back surface opposite to the second surface
  • a first gate pad, at least one first pad, and at least one second pad are formed on the first surface of the first semiconductor chip, and the first gate pad is connected to the first transistor respectively.
  • the control electrode of the control electrode is electrically connected to the first control electrode pin, the first pad is electrically connected to the second terminal of the first transistor, and the second pad is electrically connected to the first terminal of the first transistor. electrical connection;
  • a second control electrode pad and a third pad are formed on the first surface of the second semiconductor chip, and the second back surface is electrically connected to the first electrode of the second transistor; the second control electrode The pads are respectively electrically connected to the control electrode of the second transistor and the second control electrode pin, and the second electrode of the second transistor is electrically connected to the third pad;
  • the first chip mounting portion has a first upper surface, the first semiconductor chip is mounted on the first upper surface of the first chip mounting portion, the first back surface of the first semiconductor chip faces the first upper surface;
  • the second chip mounting portion has a second upper surface, the second semiconductor chip is mounted on the second upper surface of the second chip mounting portion, the second back surface of the second semiconductor chip faces the second The upper surface; the second back surface of the second semiconductor chip is electrically connected to the second chip mounting portion.
  • the at least one first pad is electrically connected, and the at least one second pad is electrically connected, but not limited thereto.
  • the first pad is insulated from the second pad, the first pad is insulated from the first control electrode pad, and the second pad is insulated from the The first gate pads are insulated.
  • the first transistor may be a field effect transistor made of GaN
  • the second transistor may be a MOSFET made of Si, but not limited thereto.
  • the semiconductor device described in at least one embodiment of the present disclosure may further include a first chip mounting portion, a second chip mounting portion, a first semiconductor chip, and a second semiconductor chip; There is a first transistor, and a second transistor is formed on the second semiconductor chip; the first chip mounting portion and the second chip mounting portion are insulated from each other; at least a part of the first chip mounting portion, the At least a part of the second chip mounting portion, the first semiconductor chip, and the second semiconductor chip are sealed by the same sealing body;
  • a first gate pad, at least one first pad, and at least one second pad are formed on the first surface of the first semiconductor chip, and a first gate pad is formed on the first surface of the second semiconductor chip.
  • two control electrode pads and a third pad the second back is electrically connected to the first electrode of the second transistor, the second back of the second semiconductor chip is electrically connected to the second chip mounting portion, so that the second chip mounting portion is electrically connected to the first electrode of the second transistor.
  • the second chip mounting part is electrically connected to the first control electrode pad through a wire, so that the first electrode of the second transistor is electrically connected to the control electrode of the first transistor;
  • the third pad is electrically connected to the first pad, so that the second electrode of the second transistor is electrically connected to the second terminal of the first transistor.
  • the wire between the second chip mounting portion and the first gate pad is short.
  • the second chip mounting part is electrically connected to the first control electrode pin through a wire, so that the first electrode of the second transistor is electrically connected to the control electrode of the first transistor, and the The third pad is electrically connected to the first pad, so that the second electrode of the second transistor is electrically connected to the second terminal of the first transistor.
  • the wire between the second chip mounting part and the first gate pin is short.
  • the semiconductor device described in at least one embodiment of the present disclosure further includes a first electrode pin and a second electrode pin;
  • the first electrode pin is electrically connected to the first pad, so that the first electrode pin is electrically connected to the second terminal of the first transistor;
  • the second electrode pin is electrically connected to the second pad, so that the second electrode pin is electrically connected to the first terminal of the first transistor.
  • first electrode pins and the second electrode pins may be at least partially disposed outside the sealing body, but not limited thereto.
  • the first chip mounting portion is disposed on a first side of the second chip mounting portion, and the conduction current of the first transistor is greater than the conduction current of the second transistor. , the turn-on speed of the first transistor is greater than the turn-on speed of the second transistor.
  • the first side can be the left side, or the first side can be the right side; when the first transistor is a field effect transistor made of GaN, the second transistor is made of Si In the case of a MOSFET made of materials, the turn-on current of the first transistor is greater than the turn-on current of the second transistor, and the turn-on speed of the first transistor is greater than the turn-on speed of the second transistor.
  • the semiconductor device may include a first transistor, a second transistor, a sealing body F0, a first chip mounting part P1, a second chip mounting part P2, a first semiconductor chip C1 , the second semiconductor chip C2, the first gate pin J01, the second gate pin J02, the first electrode pin J1 and the second electrode pin J2; the first chip mounting part P1 and the second The chip mounting parts P2 are insulated from each other; a first transistor is formed on the first semiconductor chip C1, and a second transistor is formed on the second semiconductor chip C2;
  • the first chip mounting part P1, the second chip mounting part P2, the first semiconductor chip C1 and the second semiconductor chip C2 are sealed by the same sealing body F0;
  • the first semiconductor chip C1 has a first surface and a first back surface opposite to the first surface
  • the second semiconductor chip C2 has a second surface and a second surface opposite to the second surface. back;
  • a first gate pad H01 Formed on the first surface of the first semiconductor chip C1 are a first gate pad H01, a first first pad H11, a second first pad H21, a third first pad H31, The first second pad H12, the second second pad H22 and the third second pad H32, the first control electrode pad H01 is connected to the control electrode of the first transistor and the first transistor respectively.
  • a control electrode pin J01 is electrically connected;
  • H11, H21, and H31 are electrically connected to each other, and H11, H21, and H31 are respectively electrically connected to the second terminal of the first transistor;
  • H12, H22, and H32 are electrically connected to each other, and H12, H22, and H32 are respectively electrically connected to the first terminal of the first transistor;
  • a second control electrode pad H02 and a third pad H3 are formed on the first surface of the second semiconductor chip C2, and the second back surface is electrically connected to the first electrode of the second transistor;
  • Two control electrode pads H02 are respectively electrically connected to the control electrode of the second transistor and the second control electrode pin J02, and the second electrode of the second transistor is electrically connected to the third pad H3;
  • the first chip mounting portion P1 has a first upper surface, the first semiconductor chip C1 is mounted on the first upper surface of the first chip mounting portion P1, and the first back surface of the first semiconductor chip C1 faces said first upper surface;
  • the second chip mounting portion P2 has a second upper surface, the second semiconductor chip C2 is mounted on the second upper surface of the second chip mounting portion P2, and the second back surface of the second semiconductor chip C2 faces The second upper surface; the second back surface of the second semiconductor chip C2 is electrically connected to the second chip mounting part P2, so that the first electrode of the second transistor is connected to the second chip mounting part P2 electrical connection;
  • the first transistor is a field effect transistor made of GaN
  • the second transistor is a MOSFET made of Si.
  • the second chip mounting part P2 is electrically connected to the first control electrode pin J01 through the fifth wire L5, so that the first electrode of the second transistor is connected to the first electrode of the second transistor.
  • the control electrode of the first transistor is electrically connected; wherein, the fifth wire L5 between the second chip mounting part P2 and the first control electrode pin J01 is short;
  • the third pad H3 is electrically connected to H11, H21 and H31 respectively, so that the second electrode of the second transistor is electrically connected to the second terminal of the first transistor.
  • the first chip mounting portion P1 is integrally formed in a manner of being connected to the first electrode pin J1, so that the first chip mounting portion P1 is connected to the The first electrode pin J1 is electrically connected, and H11 is electrically connected to the first chip mounting part P1, so that H11 is electrically connected to J1, and since H11, H21 and H31 are electrically connected, H21 is electrically connected to J1, H31 is electrically connected to J1;
  • H12, H22 and H32 are respectively electrically connected to J2.
  • control pole of the first transistor is a gate
  • the first terminal of the first transistor is a drain electrode
  • the second terminal of the first transistor is a source electrode
  • the control electrode of the second transistor is a gate
  • the first electrode of the second transistor is a drain electrode
  • the second electrode of the second transistor is a source electrode, but not limited thereto.
  • the first chip mounting part P1 and the first semiconductor chip C1 may be arranged in a vertical direction, but not limited thereto.
  • J02, J01, J2 and J1 are arranged sequentially from left to right, and J02, J01, J2 and J1 are insulated from each other; H11, H21 and H31 are arranged sequentially from top to bottom, and H12 , H22 and H32 are arranged sequentially from top to bottom, and H11, H21 and H31 are close to the second semiconductor chip C2, so as to facilitate the electrical connection between H11, H21 and H31 and H3; H01 is arranged at the lower left corner of the first semiconductor chip C1 , to facilitate the electrical connection between H01 and J01.
  • the first transistor is a field effect transistor made of GaN
  • the second transistor is a MOSFET made of Si
  • the first chip mounting part P1 is arranged on The right side of the second chip mounting part P2, but not limited thereto. In actual operation, P1 can also be set on the left side of P2.
  • a first semiconductor chip is mounted via a conductive adhesive material composed of silver solder or soldering.
  • a second semiconductor chip is mounted via a conductive adhesive material composed of silver solder or soldering.
  • C2 on the second semiconductor chip C2, a MOSFET made of Si is formed; the second back surface of the second semiconductor chip C2 becomes a drain electrode, and a drain electrode is formed on the second surface of the second semiconductor chip C2
  • the second control electrode pad H02 and the third pad H3; that is, the drain electrode of the second transistor is formed on the second back surface of the second semiconductor chip C2, and is electrically connected to the gate of the second transistor
  • the second gate pad H02 of the second transistor, and the third pad H3 electrically connected to the source electrode of the second transistor are disposed on the second surface of the second semiconductor chip C2.
  • the second semiconductor chip C2 since the second semiconductor chip C2 is mounted on the second chip mounting portion P2 via a conductive adhesive material, the second semiconductor chip C2 formed on the back surface of the second semiconductor chip C2 A drain electrode of the transistor is electrically connected to the second chip mounting portion P2.
  • the first chip mounting part P1, the second chip mounting part P2, the first semiconductor chip C1, the second semiconductor chip C2, a part of J02, A part of J01, a part of J2, and a part of J1 are sealed by the sealing body F0.
  • (G2) is drawn below J02, which means that J02 can be electrically connected to the gate G2 of the second transistor;
  • G1 is drawn below J01, which means that J01 can be connected to The gate G1 of the first transistor is electrically connected;
  • D) is drawn below J2, which means that J2 can be electrically connected to the drain electrode D of the first transistor;
  • S is drawn below J1, which means J1 It may be electrically connected to the source electrode S of the first transistor.
  • the second chip mounting portion P2 may also be electrically connected to the first control electrode pad H01 through a wire, so that the first electrode of the second transistor is connected to the control electrode of the first transistor. Electrical connection; wherein, the wire between the second chip mounting part P2 and the first gate pad H01 is short.
  • the difference between at least one embodiment shown in FIG. 8 and at least one embodiment shown in FIG. 7 is that the first chip mounting parts P1 are arranged in the horizontal direction, and the first semiconductor chips C1 are arranged in the horizontal direction, so that H11, H21 and H31 is arranged in sequence from right to left, and H12, H22 and H32 are arranged in sequence from right to left, and H31 is electrically connected to H3, and H11 is electrically connected to J1.
  • the second chip mounting portion P2 is electrically connected to the first control electrode pin J01 through a sixth wire L6, so that the first electrode of the second transistor is connected to the first electrode of the second transistor.
  • the control electrode of the first transistor is electrically connected; wherein, the sixth wire L6 between the second chip mounting part P2 and the first control electrode pin J01 is short.
  • the first chip mounting portion P1 is integrally formed in a manner of being connected to the first electrode pin J1, so that the first chip mounting portion P1 is connected to the The first electrode pin J1 is electrically connected, and H11 is electrically connected to the first chip mounting part P1, so that H11 is electrically connected to J1, and since H11, H21 and H31 are electrically connected, H21 is electrically connected to J1, H31 is electrically connected with J1.
  • both the first chip-mounting part and the second chip-mounting part may be disposed on the same substrate;
  • a second distance between the second chip mounting portion and the substrate is greater than a first distance between the first chip mounting portion and the substrate.
  • an isolation layer may be provided between the second chip-mounting portion and the substrate to raise the second chip-mounting portion so that the second chip-mounting portion is higher than the first chip-mounting portion.
  • a chip mounting part; the isolation layer is respectively bonded to the substrate and the second chip mounting part through an insulating bonding material.
  • the isolation layer may be made of Al2O3, but not limited thereto.
  • the second chip-mounting portion is higher than the first chip-mounting portion, so that the second electrode of the second transistor is formed through the wire between the second terminal of the first transistor and the second terminal of the first transistor.
  • the stress on the second transistor can be increased, the stress on the first transistor can be reduced, and the first transistor can be protected.
  • the second electrode of the second transistor is electrically connected to the second terminal of the first transistor through a wire;
  • the wire includes a first wire part, a second wire part and a third wire part;
  • the first end of the first wire part is electrically connected to the second electrode of the second transistor, the second end of the first wire part is electrically connected to the first end of the second wire part, and the first The second end of the second lead part is electrically connected to the first end of the third lead part, and the second end of the third lead part is electrically connected to the second terminal of the first transistor;
  • the second upper surface of the second chip mounting part is perpendicular to the first lead part, and the first upper surface of the first chip mounting part is not perpendicular to the third lead part, so that the second transistor The stress is large, reducing the stress on the first transistor and protecting the first transistor.
  • the semiconductor device described in at least one embodiment of the present disclosure may further include a chip mounting portion, a first semiconductor chip, and a second semiconductor chip; a first transistor is formed on the first semiconductor chip, and A second transistor is formed on the second semiconductor chip;
  • the first semiconductor chip has a first surface opposite to the first surface.
  • a first backside on a side the second semiconductor chip has a second surface and a second backside opposite to the second surface;
  • a first control electrode pad and a first pad are formed on the first surface of the first semiconductor chip, and the first back surface is electrically connected to the first terminal of the first transistor; the first control electrode The pads are respectively electrically connected to the control electrode of the first transistor and the first control electrode pin, and the first pad is electrically connected to the second terminal of the first transistor;
  • a second gate pad, at least one second pad, and at least one third pad are formed on the second surface of the second semiconductor chip, and the second gate pad is connected to the second transistor respectively.
  • the control electrode of the second transistor is electrically connected to the second control electrode pin, the second electrode of the second transistor is electrically connected to the second pad, and the first electrode of the second transistor is electrically connected to the third pad electrical connection;
  • the chip mounting portion has an upper surface, the first semiconductor chip is mounted on the upper surface of the chip mounting portion, the first back surface of the first semiconductor chip faces the upper surface; The first back surface is electrically connected to the chip mounting part;
  • the second semiconductor chip is mounted on the upper surface of the chip mounting portion, and the second back surface of the second semiconductor chip faces the upper surface.
  • the semiconductor device described in at least one embodiment of the present disclosure may further include a chip mounting portion, a first semiconductor chip, and a second semiconductor chip; a first transistor is formed on the first semiconductor chip, and a first transistor is formed on the first semiconductor chip. A second transistor is formed on the second semiconductor chip; at least a part of the chip mounting portion, the first semiconductor chip, and the second semiconductor chip are sealed by the same sealing body;
  • a first gate pad and a first pad are formed on the first surface of the first semiconductor chip, the first back surface is electrically connected to the first terminal of the first transistor, and the first semiconductor chip
  • the first back surface of the first semiconductor chip is electrically connected to the chip mounting portion, so that the first terminal of the first transistor is electrically connected to the chip mounting portion;
  • a second control circuit is formed on the second surface of the second semiconductor chip. pole pad, at least one second pad and at least one third pad.
  • the third pad is electrically connected to the first control electrode pin through a wire, so that the first electrode of the second transistor is electrically connected to the control electrode of the first transistor;
  • the second pad is electrically connected to the first pad, so that the second electrode of the second transistor is electrically connected to the second terminal of the first transistor.
  • the wire between the third pad and the first gate pin is short.
  • the third pad is electrically connected to the first control electrode pad through a wire, so that the first electrode of the second transistor is electrically connected to the control electrode of the first transistor;
  • the second pad is electrically connected to the first pad, so that the second electrode of the second transistor is electrically connected to the second terminal of the first transistor.
  • the wire between the third pad and the first gate pad is short.
  • the semiconductor device may further include a first electrode pin and a second electrode pin;
  • the first electrode pin is electrically connected to the first pad, so that the first electrode pin is electrically connected to the second terminal of the first transistor;
  • the second electrode pin is electrically connected to the chip mounting portion, so that the second electrode pin is electrically connected to the first terminal of the first transistor.
  • the first semiconductor chip is disposed on the first side of the second semiconductor chip, and the conduction current of the first transistor is greater than the conduction current of the second transistor.
  • the first transistor is a MOSFET made of SiC
  • the second transistor is a field effect transistor made of GaN.
  • the first side may be the left side, or the first side may be the right side; when the first transistor is a MOSFET made of SiC, the first side When the second transistor is a field effect transistor made of GaN, the conduction current of the first transistor is greater than that of the second transistor.
  • a fourth distance between the first semiconductor chip and the chip mounting portion is greater than a third distance between the first semiconductor chip and the chip mounting portion.
  • an isolation layer may be provided between the second semiconductor chip and the chip mounting part to raise the second semiconductor chip so that the second semiconductor chip is higher than the first semiconductor chip.
  • a semiconductor chip; the isolation layer is respectively bonded to the chip mounting part and the second semiconductor chip through an insulating bonding material.
  • the isolation layer may be made of Al2O3, but not limited thereto.
  • the second semiconductor chip is higher than the first semiconductor chip, so that when the second electrode of the second transistor passes through the wire and the wire between the second terminal of the first transistor, The stress on the second transistor can be increased, the stress on the first transistor can be reduced, and the first transistor can be protected.
  • the second electrode of the second transistor is electrically connected to the second terminal of the first transistor through a wire;
  • the wire includes a first wire part, a second wire part and a third wire part;
  • the first end of the first wire part is electrically connected to the second electrode of the second transistor, the second end of the first wire part is electrically connected to the first end of the second wire part, and the first The second end of the second lead part is electrically connected to the first end of the third lead part, and the second end of the third lead part is electrically connected to the second terminal of the first transistor;
  • the second surface of the second semiconductor chip is perpendicular to the first lead part, and the first surface of the first semiconductor chip is not perpendicular to the third lead part so that the stress on the second transistor is large and the stress on the second transistor is reduced.
  • the first transistor is protected against stress on the first transistor.
  • the semiconductor device may include a first transistor, a second transistor, a sealing body F0, a chip mounting part P0, a first semiconductor chip C1, a second semiconductor chip C2, a first A gate pin J01, a second gate pin J02, a first electrode pin J1, and a second electrode pin J2; a first transistor is formed on the first semiconductor chip C1, and a first transistor is formed on the second semiconductor chip C1 A second transistor is formed on C2;
  • the chip mounting part P0, the first semiconductor chip C1, and the second semiconductor chip C2 are sealed by the same sealing body;
  • the first semiconductor chip C1 has a first surface and is separated from the first surface.
  • a first back surface on the opposite side the second semiconductor chip C2 has a second surface and a second back surface on the opposite side to the second surface;
  • a first gate pad H01 and a first pad H1 are formed on the first surface of the first semiconductor chip C1, and the first back surface is electrically connected to the first terminal of the first transistor;
  • a control electrode pad H01 is electrically connected to the control electrode of the first transistor and the first control electrode pin J01 respectively, and the first pad H1 is electrically connected to the second terminal of the first transistor;
  • a second gate pad H02 Formed on the second surface of the second semiconductor chip are a second gate pad H02, a first second pad H12, a second second pad H22, a first third pad H13 and a first Two third pads H23, the second control electrode pad H02 are respectively electrically connected to the control electrode of the second transistor and the second control electrode pin J02, and the second electrodes of the second transistor are respectively It is electrically connected to H12 and H22, and the first electrode of the second transistor is electrically connected to H13 and H23 respectively;
  • H12 is electrically connected to H22, and H13 is electrically connected to H23;
  • the chip mounting part P0 has an upper surface, the first semiconductor chip C1 is mounted on the upper surface of the chip mounting part P0, and the first back surface of the first semiconductor chip C1 faces the upper surface; A first back surface of a semiconductor chip C1 is electrically connected to the chip mounting portion P0, so that the first terminal of the first transistor is electrically connected to the chip mounting portion P0;
  • the second semiconductor chip C2 is mounted on the upper surface of the chip mounting part P0, and the second back surface of the second semiconductor chip C2 faces the upper surface;
  • the first electrode pin J1 is electrically connected to the first pad H1, so that the first electrode pin J1 is electrically connected to the second terminal of the first transistor;
  • the second electrode pin J2 is electrically connected to the chip mounting part P0, so that the second electrode pin J2 is electrically connected to the first terminal of the first transistor;
  • H13 is electrically connected to the first control electrode pin J01 through the seventh wire L7, so that the first electrode of the second transistor is electrically connected to the control electrode of the first transistor; H12 is connected to the first pad H1 is electrically connected such that the second electrode of the second transistor is electrically connected with the second terminal of the first transistor.
  • the seventh wire L7 between H13 and the first gate pin J01 is short.
  • the gate electrode of the first transistor is the gate, the first terminal of the first transistor is a drain electrode, and the second terminal of the first transistor is a source electrode, so
  • the control electrode of the second transistor is a gate, the first electrode of the second transistor is a drain electrode, and the second electrode of the second transistor is a source electrode, but not limited thereto.
  • the chip mounting part P0 is integrally formed in a manner of being connected to the second electrode lead J2, so that the chip mounting part P0 is connected to the second electrode lead J2.
  • Pin J2 is electrically connected.
  • J02, J01, J2 and J1 are arranged sequentially from left to right, and J02, J01, J2 and J1 are insulated from each other; H12 and H22 are arranged sequentially from right to left, and H13 and H23 Arranged from right to left, H13 is close to J01 to facilitate the electrical connection between H13 and J01.
  • the first transistor is a MOSFET made of SiC
  • the second transistor is a field effect transistor made of GaN
  • the first semiconductor chip C1 is disposed on the The right side of the second semiconductor chip C2 is mentioned above, but not limited thereto. In actual operation, C1 can also be set on the left side of C2.
  • a first semiconductor chip C1 is mounted via a conductive adhesive material composed of silver solder or soldering; On the first semiconductor chip C1, a MOSFET made of SiC is formed; the first back surface of the first semiconductor chip C1 becomes a drain electrode, and a first control electrode is formed on the first surface of the first semiconductor chip C1
  • the pad H01 and the first pad H1; that is, the drain electrode of the first transistor is formed on the first back surface of the first semiconductor chip C1, and the first control electrode electrically connected to the gate of the first transistor
  • the electrode pad H01, and the first pad H1 electrically connected to the source electrode of the first transistor are disposed on the first surface of the first semiconductor chip C2.
  • the second semiconductor chip C2 is provided with the second back surface of the second semiconductor chip C2 facing the upper surface;
  • the second back surface of the second semiconductor chip C2 is insulated from the chip mounting portion P0.
  • the chip mounting part P0, the first semiconductor chip C1, the second semiconductor chip C2, a part of J02, a part of J01, a part of J2 and a part of J1 It is sealed by the sealing body F0.
  • (G2) is drawn below J02, which means that J02 can be electrically connected to the gate G2 of the second transistor;
  • G1 is drawn below J01, which means that J01 can be connected to the first transistor is electrically connected to the gate G1 of J2;
  • D is drawn below J2, which means that J2 can be electrically connected to the drain electrode D of the first transistor;
  • S is drawn below J1, which means that J1 can be connected to the first transistor.
  • the source electrode S of a transistor is electrically connected.
  • the first third pad H13 may also be electrically connected to the first control electrode pad H01 through a wire, so that the first electrode of the second transistor is connected to the first electrode of the first transistor.
  • the control electrode is electrically connected; wherein, the wire between the first third pad H13 and the first control electrode pad H01 is short.
  • At least one embodiment of the present disclosure includes a semiconductor device including a sealing body, a first transistor, and a capacitor, wherein the first transistor includes a control electrode, a first terminal, and a second terminal; the capacitor includes a first capacitor electrode and a second capacitor electrode ;
  • the first transistor is used to enable current to flow from the first terminal to the second terminal under the control of the potential of its control electrode;
  • the first capacitor electrode is electrically connected to the control electrode of the first transistor ,
  • the second capacitor electrode is electrically connected to the second terminal of the first transistor;
  • Both the first transistor and the capacitor are sealed by the same sealing body, and the control electrode of the first transistor is electrically connected to the first control electrode pin.
  • control electrode of the first transistor may be electrically connected to the first control electrode pin through a bonding wire; the bonding wire is a wire.
  • both the first transistor and the capacitor are sealed by the same sealing body, so as to shorten the capacitor and the control electrode of the first transistor to ensure better clamping effect and simplify wiring.
  • the first gate pin is at least partially disposed outside the encapsulation body, but not limited thereto.
  • the sealing body may be made of resin, but not limited thereto.
  • the first transistor is an n-type transistor, the first terminal is a first electrode, the first electrode is a drain electrode, the second terminal is a second electrode, and the second electrode is a source electrodes; or,
  • the first transistor is a p-type transistor, the first terminal is a first electrode, the first terminal is a source electrode, the second terminal is a second electrode, and the second terminal is a drain electrode.
  • the semiconductor device described in at least one embodiment of the present disclosure further includes a chip mounting portion, a first semiconductor chip, a second semiconductor chip, and a first gate pin; a first gate pin is formed on the first semiconductor chip. a transistor; the capacitor is formed on the second semiconductor chip;
  • At least a part of the chip mounting portion, the first semiconductor chip, and the second semiconductor chip are sealed by the same sealing body;
  • the first semiconductor chip has a first surface and a first back surface opposite to the first surface;
  • the second semiconductor chip has a second surface and a second back surface opposite the second surface;
  • a first control electrode pad and a first pad are formed on the first surface of the first semiconductor chip, and the first back surface is electrically connected to the first terminal of the first transistor; the first control electrode The pads are respectively electrically connected to the control electrode of the first transistor and the first control electrode pin, and the first pad is electrically connected to the second terminal of the first transistor;
  • a first electrode pad and a second electrode pad are formed on the second surface of the second semiconductor chip; the first electrode pad is electrically connected to the first capacitor electrode, and the second electrode pad electrically connected to the second capacitor electrode;
  • the chip mounting portion has an upper surface, the first semiconductor chip is mounted on the upper surface of the chip mounting portion, the first back surface of the first semiconductor chip faces the upper surface; The first back surface is electrically connected to the chip mounting part;
  • the second semiconductor chip is mounted on the upper surface of the chip mounting part, and the second back surface of the second semiconductor chip faces the upper surface;
  • the first electrode pad is electrically connected to the first control pin or the first control pad, and the second electrode pad is electrically connected to the first pad, so that the first The two capacitor electrodes are electrically connected to the second terminal of the first transistor.
  • the semiconductor device further includes a chip mounting portion, a first semiconductor chip, a second semiconductor chip, and a first control pin; a first transistor is formed on the first semiconductor chip; The capacitance is formed on the second semiconductor chip; at least a part of the chip mounting portion, the first semiconductor chip, and the second semiconductor chip are sealed by the same sealing body; the first transistor It may be a MOSFET made of SiC, and the first electrode pad is electrically connected to the first control pin or the first control pad, wherein the first electrode pad is connected to the The wires between the first control electrode pins or the first control electrode pads are short.
  • the semiconductor device may also include a first electrode pin and a second electrode pin;
  • the first electrode pin is electrically connected to the first pad, and the second electrode pin is electrically connected to the chip mounting portion.
  • the first control electrode pin is at least partially disposed outside the sealing body, the first electrode pin is at least partially disposed outside the sealing body, and the second electrode pin is at least partially disposed outside the sealing body. on the outside of the enclosure.
  • the semiconductor device described in at least one embodiment of the present disclosure includes a first transistor M1 and a capacitor C0; the capacitor C0 includes a first capacitor electrode and a second capacitor electrode;
  • the first transistor M1 is used to allow current to flow from the drain electrode D of the first transistor M1 to the source electrode S of the first transistor M1 under the control of the potential of the gate G1;
  • the first capacitor electrode is electrically connected to the gate G1 of the first transistor M1, and the second capacitor electrode is electrically connected to the source electrode S of the first transistor M1.
  • M1 is an n-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, Metal-Oxide-Semiconductor Field Effect Transistor), but not limited thereto.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor, Metal-Oxide-Semiconductor Field Effect Transistor
  • the semiconductor device described in at least one embodiment of the present disclosure may include a first transistor, a second transistor, a sealing body F0, a chip mounting part P0, a first semiconductor chip C1, a second semiconductor chip C2, a first A control electrode pin J01, a first electrode pin J1, and a second electrode pin J2; a first transistor is formed on the first semiconductor chip C1; and the capacitor is formed on the second semiconductor chip C2;
  • the chip mounting part P0, the first semiconductor chip C1 and the second semiconductor chip C2 are sealed by the same sealing body F0;
  • the first semiconductor chip C1 has a first surface and a first back surface opposite to the first surface;
  • the second semiconductor chip C2 has a second surface and a second surface opposite to the second surface. back;
  • a first gate pad H01 and a first pad H1 are formed on the first surface of the first semiconductor chip C1, and the first back surface is electrically connected to the first terminal of the first transistor;
  • a control electrode pad H01 is electrically connected to the control electrode of the first transistor and the first control electrode pin J01 respectively, and the first pad H1 is electrically connected to the second terminal of the first transistor;
  • a first electrode pad H41 and a second electrode pad H42 are formed on the second surface of the second semiconductor chip C2; the first electrode pad H41 is electrically connected to the first capacitor electrode, and the first electrode pad H41 is electrically connected to the first capacitor electrode.
  • the second electrode pad H42 is electrically connected to the second capacitor electrode;
  • the chip mounting part P0 has an upper surface, the first semiconductor chip C1 is mounted on the upper surface of the chip mounting part P0, and the first back surface of the first semiconductor chip C1 faces the upper surface; A first back surface of the semiconductor chip C1 is electrically connected to the chip mounting portion P0;
  • the second semiconductor chip C2 is mounted on the upper surface of the chip mounting part, and the second back surface of the second semiconductor chip C2 faces the upper surface;
  • the second electrode pad H41 is electrically connected to the first pad H1;
  • the first electrode pad H41 is electrically connected to the first control electrode pin J01 through the eighth wire L8, so that the first capacitor electrode is electrically connected to the control electrode of the first transistor; the second The electrode pad 42 is electrically connected to the first pad H1, so that the second capacitance electrode is electrically connected to the second terminal of the first transistor; wherein, the first electrode pad H41 is connected to the second terminal of the first transistor.
  • the eighth wire L8 between the control pole pins J01 is short;
  • the first electrode pin J1 is electrically connected to the first pad H1, so that the first electrode pin J1 is electrically connected to the second terminal of the first transistor; the second electrode pin J2 It is electrically connected with the chip mounting part P0, so that the second electrode pin J2 is electrically connected with the first terminal of the first transistor.
  • the first transistor is an n-type transistor
  • the first terminal is a first electrode
  • the first electrode is a drain electrode
  • the second terminal is a second electrode
  • the second electrode is a source electrode
  • (G1) is drawn below J01, which means that J01 can be electrically connected to the gate G1 of the first transistor;
  • D is drawn below J2, which means that J2 can be connected to the first transistor The drain electrode D of the first transistor is electrically connected;
  • S is drawn below J1, which means that J1 can be electrically connected with the source electrode S of the first transistor.
  • the first transistor is a MOSFET made of SiC; the first semiconductor chip C1 is disposed on the right side of the second semiconductor chip C2 , but not limited thereto. In actual operation, C1 can also be set on the left side of C2.
  • a small area is used to set a capacitor to integrate the capacitor inside the SiC MOSFET.
  • the chip mounting part P0 is integrally formed in a manner of being connected to the second electrode pin J2, and the chip mounting part P0 and the second electrode pin J2 Electrical connection; disposing the first control electrode pin J01 and the first electrode pin J1 in a manner of separating and interposing the second electrode pin J2.
  • J1 is arranged on the right side of J2
  • J01 is arranged on the left side of J2
  • J01 , J2 and J1 are insulated from each other.
  • a first semiconductor chip C1 is mounted via a conductive adhesive material composed of silver solder or solder;
  • a MOSFET made of SiC is formed on the semiconductor chip C1;
  • the first back surface of the first semiconductor chip C1 becomes a drain electrode, and a first gate pad H01 is formed on the first surface of the first semiconductor chip C1 and the first pad H1; that is, the drain electrode of the first transistor is formed on the first back surface of the first semiconductor chip C1, and the first gate pad electrically connected to the gate of the first transistor H01, and a first pad H1 electrically connected to the source electrode of the first transistor is disposed on the first surface of the first semiconductor chip C1.
  • the second back surface of the second semiconductor chip C2 faces the upper surface of the chip mounting portion P0, and the second back surface of the second semiconductor chip C2 is insulated from the chip mounting portion P0, but is not This is the limit.
  • a second semiconductor chip C2 is arranged on the chip mounting portion P0, and the capacitor is formed on the second semiconductor chip C2;
  • a first electrode pad H41 and a second electrode pad H42 are formed on the second surface of C2.
  • the chip mounting part P0, the first semiconductor chip C1, the second semiconductor chip C2, a part of J01, a part of J2 and a part of J1 are covered by the package Solid F0 mount.
  • the switch system may include a gate driver and the above-mentioned semiconductor device.
  • the gate driver provides a gate drive signal for the control electrode of the first transistor in the semiconductor device to control the conduction of the first transistor. on or off.
  • a first pole of the first transistor may be electrically connected to a power supply terminal, and a second pole of the first transistor may be electrically connected to a load. When the first transistor is turned on, the power terminal provides a power supply voltage for the load.
  • At least one embodiment of the switching system may include a gate driver 120 and at least one embodiment of the semiconductor device shown in FIG. 1 of the present disclosure;
  • the gate driver 120 is electrically connected to the gate G1 of M1 through a resistor R, the drain electrode D of M1 is electrically connected to the power supply voltage terminal E1 , and the source electrode S of M1 is electrically connected to the load 121 .
  • At least one embodiment of the switch system shown in FIG. 12 is in operation, and when the connection between E1 and the load 121 needs to be turned on, the gate driver 120 provides a gate drive signal to the gate G1 of M1 to Control M1 to be turned on, so as to control the communication between the power supply voltage terminal E1 and the load 121 .

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Abstract

本公开提供一种半导体器件。所述半导体器件包括封固体、第一晶体管和第二晶体管，其中，所述第一晶体管包括控制极、第一端子和第二端子；所述第一晶体管用于在其控制极的电位的控制下，使得电流能够从所述第一端子流向所述第二端子；所述第二晶体管的第一电极与所述第一晶体管的控制极电连接，所述第二晶体管的第二电极与所述第一晶体管的第二端子电连接；所述第一晶体管和所述第二晶体管被同一所述封固体封固，所述第一晶体管的控制极与第一控制极引脚电连接，所述第二晶体管的控制极与第二控制极引脚电连接。本公开能够保证较好的钳位效果，并简化布线。

Description

半导体器件 技术领域
本公开涉及一种半导体器件。
背景技术
在相关技术中，在用于开关的第一晶体管的控制极通常设有钳位元件(所述钳位元件例如可以为钳位晶体管或电容)。然而，在实际使用时，所述钳位元件一般设置于PCB(Printed Circuit Board，印刷电路板)板卡。
由于需要设置散热器，所述第一晶体管的管脚与PCB板卡之间距离较长，导致，所述第一晶体管的晶圆与所述钳位元件之间的距离无法设置为较短，使得钳位元件的作用大打折扣。
发明内容
本公开的主要目的在于提供一种半导体器件。
为了达到上述目的，本公开实施例提供了一种半导体器件，包括封固体、第一晶体管和第二晶体管，其中，所述第一晶体管包括控制极、第一端子和第二端子；
所述第一晶体管用于在其控制极的电位的控制下，使得电流能够从所述第一端子流向所述第二端子；所述第二晶体管的第一电极与所述第一晶体管的控制极电连接，所述第二晶体管的第二电极与所述第一晶体管的第二端子电连接；
所述第一晶体管和所述第二晶体管被同一所述封固体封固，所述第一晶体管的控制极与第一控制极引脚电连接，所述第二晶体管的控制极与第二控制极引脚电连接。
可选的，所述第一晶体管为n型晶体管，所述第一端子为第一电极，所述第一电极为漏电极，所述第二端子为第二电极，所述第二电极为源电极；或者，
所述第一晶体管为p型晶体管，所述第一端子为第一电极，所述第一端 子为源电极，所述第二端子为第二电极，所述第二端子为漏电极。
可选的，本公开至少一实施例所述的半导体器件还包括第一芯片搭载部、第二芯片搭载部、第一半导体芯片、第二半导体芯片、第一控制极引脚和第二控制极引脚；所述第一芯片搭载部与所述第二芯片搭载部相互绝缘；在所述第一半导体芯片上形成有第一晶体管，在所述第二半导体芯片上形成有第二晶体管；
所述第一芯片搭载部的至少一部分、所述第二芯片搭载部的至少一部分、所述第一半导体芯片和所述第二半导体芯片被同一所述封固体封固；
所述第一半导体芯片具有第一表面和与所述第一表面为相反侧的第一背面，所述第二半导体芯片具有第二表面和与所述第二表面为相反侧的第二背面；
在所述第一半导体芯片的第一表面上形成有第一控制极焊盘和第一焊盘，所述第一背面与所述第一晶体管的第一端子电连接；所述第一控制极焊盘分别与所述第一晶体管的控制极和第一控制极引脚电连接，所述第一焊盘与所述第一晶体管的第二端子电连接；
在所述第二半导体芯片的第一表面上形成有第二控制极焊盘和第二焊盘，所述第二背面与所述第二晶体管的第一电极电连接；所述第二控制极焊盘分别与所述第二晶体管的控制极和第二控制极引脚电连接，所述第二晶体管的第二电极与所述第二焊盘电连接；
所述第一芯片搭载部具有第一上表面，所述第一半导体芯片搭载于所述第一芯片搭载部的第一上表面上，所述第一半导体芯片的第一背面朝向所述第一上表面；所述第一半导体芯片的第一背面与所述第一芯片搭载部电连接；
所述第二芯片搭载部具有第二上表面，所述第二半导体芯片搭载于所述第二芯片搭载部的第二上表面上，所述第二半导体芯片的第二背面朝向所述第二上表面；所述第二半导体芯片的第二背面与所述第二芯片搭载部电连接。
可选的，所述第二芯片搭载部通过导线与所述第一控制极焊盘电连接；所述第二焊盘与所述第一焊盘电连接。
可选的，所述第二芯片搭载部通过导线与所述第一控制极引脚电连接，所述第二焊盘与所述第一焊盘电连接。
可选的，本公开至少一实施例所述的半导体器件还包括第一电极引脚和第二电极引脚；
所述第一电极引脚与所述第一焊盘电连接，所述第二电极引脚与所述第一芯片搭载部电连接。
可选的，所述第一芯片搭载部设置于所述第二芯片搭载部的第一侧边，所述第一晶体管的导通电流大于所述第二晶体管的导通电流，所述第一晶体管的导通速度大于所述第二晶体管的导通速度。
可选的，本公开至少一实施例所述的半导体器件还包括第一芯片搭载部、第二芯片搭载部、第一半导体芯片、第二半导体芯片、第一控制极引脚和第二控制极引脚；所述第一芯片搭载部的至少一部分、所述第二芯片搭载部的至少一部分、所述第一半导体芯片和所述第二半导体芯片都被同一所述封固体封固；在所述第一半导体芯片上形成有第一晶体管，在所述第二半导体芯片上形成有第二晶体管；
所述第一半导体芯片具有第一表面和与所述第一表面为相反侧的第一背面，所述第二半导体芯片具有第二表面和与所述第二表面为相反侧的第二背面；
在所述第一半导体芯片的第一表面上形成有第一控制极焊盘和第一焊盘，所述第一背面与所述第一晶体管的第一端子电连接；所述第一控制极焊盘分别与所述第一晶体管的控制极和第一控制极引脚电连接，所述第一焊盘与所述第一晶体管的第二端子电连接；
在所述第二半导体芯片的第一表面上形成有第二控制极焊盘和第二焊盘，所述第二背面与所述第二晶体管的第一电极电连接；所述第二控制极焊盘分别与所述第二晶体管的控制极和第二控制极引脚电连接，所述第二晶体管的第二电极与所述第二焊盘电连接；
所述第一芯片搭载部具有第一上表面，所述第一半导体芯片搭载于所述第一芯片搭载部的第一上表面上，所述第一半导体芯片的第一背面朝向所述第一上表面；所述第一半导体芯片的第一背面与所述第一芯片搭载部电连接；
所述第二芯片搭载部具有第二上表面和与所述第二上表面为相反侧的第二下表面，所述第二芯片搭载部搭载于所述第一芯片搭载部的第一上表面 上，所述第二芯片搭载部与所述第一芯片搭载部之间绝缘，所述第二芯片搭载部的第二下表面朝向所述第一上表面；
所述第二半导体芯片搭载于所述第二芯片搭载部的第二上表面上，所述第二半导体芯片的第二背面朝向所述第二上表面；所述第二半导体芯片的第二背面与所述第二芯片搭载部电连接。
可选的，所述第二芯片搭载部通过导线与所述第一控制极焊盘电连接；所述第二焊盘与所述第一焊盘电连接。
可选的，所述第二芯片搭载部通过导线与所述第一控制极引脚电连接，所述第二焊盘与所述第一焊盘电连接。
可选的，本公开至少一实施例所述的半导体器件还包括第一电极引脚和第二电极引脚；
所述第一电极引脚与所述第一焊盘电连接，所述第二电极引脚与所述第一芯片搭载部电连接。
可选的，所述第一半导体芯片设置于所述第二半导体芯片的第一侧边，所述第一晶体管的导通电流大于所述第二晶体管的导通电流，所述第一晶体管的导通速度大于所述第二晶体管的导通速度。
可选的，所述第一晶体管为以SiC为材料的MOSFET，所述第二晶体管为以Si为材料的MOSFET。
可选的，本公开至少一实施例所述的半导体器件还包括第一芯片搭载部、第二芯片搭载部、第一半导体芯片、第二半导体芯片、第一控制极引脚和第二控制极引脚；所述第一芯片搭载部与所述第二芯片搭载部相互绝缘；在所述第一半导体芯片上形成有第一晶体管，在所述第二半导体芯片上形成有第二晶体管；
所述第一芯片搭载部的至少一部分、所述第二芯片搭载部的至少一部分、所述第一半导体芯片和所述第二半导体芯片被同一所述封固体封固；
所述第一半导体芯片具有第一表面和与所述第一表面为相反侧的第一背面，所述第二半导体芯片具有第二表面和与所述第二表面为相反侧的第二背面；
在所述第一半导体芯片的第一表面上形成有第一控制极焊盘、至少一个 第一焊盘和至少一个第二焊盘，所述第一控制极焊盘分别与所述第一晶体管的控制极和第一控制极引脚电连接，所述第一焊盘与所述第一晶体管的第二端子电连接，所述第二焊盘与所述第一晶体管的第一端子电连接；
在所述第二半导体芯片的第一表面上形成有第二控制极焊盘和第三焊盘，所述第二背面与所述第二晶体管的第一电极电连接；所述第二控制极焊盘分别与所述第二晶体管的控制极和第二控制极引脚电连接，所述第二晶体管的第二电极与所述第三焊盘电连接；
所述第一芯片搭载部具有第一上表面，所述第一半导体芯片搭载于所述第一芯片搭载部的第一上表面上，所述第一半导体芯片的第一背面朝向所述第一上表面；
所述第二芯片搭载部具有第二上表面，所述第二半导体芯片搭载于所述第二芯片搭载部的第二上表面上，所述第二半导体芯片的第二背面朝向所述第二上表面；所述第二半导体芯片的第二背面与所述第二芯片搭载部电连接。
可选的，所述第二芯片搭载部通过导线与所述第一控制极焊盘电连接；所述第三焊盘与所述第一焊盘电连接。
可选的，所述第二芯片搭载部通过导线与所述第一控制极引脚电连接，所述第三焊盘与所述第一焊盘电连接。
可选的，本公开至少一实施例所述的半导体器件还包括第一电极引脚和第二电极引脚；
所述第一电极引脚与所述第一焊盘电连接，所述第二电极引脚与所述第二焊盘电连接。
可选的，所述第一芯片搭载部设置于所述第二芯片搭载部的第一侧边，所述第一晶体管的导通电流大于所述第二晶体管的导通电流，所述第一晶体管的导通速度大于所述第二晶体管的导通速度。
可选的，所述第一晶体管为以GaN为材料的场效应晶体管，所述第二晶体管为以Si为材料的MOSFET。
可选的，所述第一芯片搭载部和所述第二芯片搭载部都设置于同一基板上；
所述第二芯片搭载部与所述基板之间的第二距离，大于所述第一芯片搭 载部与所述基板之间的第一距离。
可选的，所述第二晶体管的第二电极通过导线与所述第一晶体管的第二端子电连接；
所述导线包括第一导线部、第二导线部和第三导线部；
所述第一导线部的第一端与所述第二晶体管的第二电极电连接，所述第一导线部的第二端与所述第二导线部的第一端电连接，所述第二导线部的第二端与所述第三导线部的第一端电连接，所述第三导线部的第二端与所述第一晶体管的第二端子电连接；
所述第二芯片搭载部的第二上表面与所述第一导线部垂直；
所述第一芯片搭载部的第一上表面与所述第三导线部不垂直。
可选的，本公开至少一实施例所述的半导体器件还包括芯片搭载部、第一半导体芯片、第二半导体芯片、第一控制极引脚和第二控制极引脚；在所述第一半导体芯片上形成有第一晶体管，在所述第二半导体芯片上形成有第二晶体管；
所述芯片搭载部的至少一部分、所述第一半导体芯片和所述第二半导体芯片被同一所述封固体封固；所述第一半导体芯片具有第一表面和与所述第一表面为相反侧的第一背面，所述第二半导体芯片具有第二表面和与所述第二表面为相反侧的第二背面；
在所述第一半导体芯片的第一表面上形成有第一控制极焊盘和第一焊盘，所述第一背面与所述第一晶体管的第一端子电连接；所述第一控制极焊盘分别与所述第一晶体管的控制极和第一控制极引脚电连接，所述第一焊盘与所述第一晶体管的第二端子电连接；
在所述第二半导体芯片的第二表面上形成有第二控制极焊盘、至少一个第二焊盘和至少一个第三焊盘，所述第二控制极焊盘分别与所述第二晶体管的控制极和第二控制极引脚电连接，所述第二晶体管的第二电极与所述第二焊盘电连接，所述第二晶体管的第一电极与所述第三焊盘电连接；
所述芯片搭载部具有上表面，所述第一半导体芯片搭载于所述芯片搭载部的上表面上，所述第一半导体芯片的第一背面朝向所述上表面；所述第一半导体芯片的第一背面与所述芯片搭载部电连接；
所述第二半导体芯片搭载于所述芯片搭载部的上表面上，所述第二半导体芯片的第二背面朝向所述上表面。
可选的，所述第三焊盘通过导线与所述第一控制极引脚电连接，所述第二焊盘与所述第一焊盘电连接。
可选的，所述第三焊盘通过导线与所述第一控制极焊盘电连接，所述第二焊盘与所述第一焊盘电连接。
可选的，本公开至少一实施例所述的半导体器件还包括第一电极引脚和第二电极引脚；
所述第一电极引脚与所述第一焊盘电连接，所述第二电极引脚与所述芯片搭载部电连接。
可选的，所述第一半导体芯片设置于所述第二半导体芯片的第一侧边，所述第一晶体管的导通电流大于所述第二晶体管的导通电流。
可选的，所述第一晶体管为以SiC为材料的MOSFET，所述第二晶体管为以GaN为材料的场效应晶体管。
可选的，所述第一半导体芯片与所述芯片搭载部之间的第四距离，大于所述第一半导体芯片与所述芯片搭载部之间的第三距离。
可选的，所述第二晶体管的第二电极通过导线与所述第一晶体管的第二端子电连接；
所述导线包括第一导线部、第二导线部和第三导线部；
所述第一导线部的第一端与所述第二晶体管的第二电极电连接，所述第一导线部的第二端与所述第二导线部的第一端电连接，所述第二导线部的第二端与所述第三导线部的第一端电连接，所述第三导线部的第二端与所述第一晶体管的第二端子电连接；
所述第二半导体芯片的第二表面与所述第一导线部垂直；
所述第一半导体芯片的第一表面与所述第三导线部不垂直。
本公开实施例还提供了一种半导体器件，包括封固体、第一晶体管和电容，其中，所述第一晶体管包括控制极、第一端子和第二端子；所述电容包括第一电容电极和第二电容电极；
所述第一晶体管用于在其控制极的电位的控制下，使得电流能够从所述 第一端子流向所述第二端子；所述第一电容电极与所述第一晶体管的控制极电连接，所述第二电容电极与所述第一晶体管的第二端子电连接；
所述第一晶体管和所述电容都被同一所述封固体封固，所述第一晶体管的控制极与第一控制极引脚电连接。
可选的，所述第一晶体管为n型晶体管，所述第一端子为第一电极，所述第一电极为漏电极，所述第二端子为第二电极，所述第二电极为源电极；或者，
所述第一晶体管为p型晶体管，所述第一端子为第一电极，所述第一端子为源电极，所述第二端子为第二电极，所述第二端子为漏电极。
可选的，本公开至少一实施例所述的半导体器件还包括芯片搭载部、第一半导体芯片、第二半导体芯片和第一控制极引脚；在所述第一半导体芯片上形成有第一晶体管；在所述第二半导体芯片上形成有所述电容；
所述芯片搭载部的至少一部分、所述第一半导体芯片和所述第二半导体芯片被同一所述封固体封固；
所述第一半导体芯片具有第一表面和与所述第一表面为相反侧的第一背面；所述第二半导体芯片具有第二表面和与所述第二表面为相反侧的第二背面；
在所述第一半导体芯片的第一表面上形成有第一控制极焊盘和第一焊盘，所述第一背面与所述第一晶体管的第一端子电连接；所述第一控制极焊盘分别与所述第一晶体管的控制极和第一控制极引脚电连接，所述第一焊盘与所述第一晶体管的第二端子电连接；
在所述第二半导体芯片的第二表面上形成有第一电极焊盘和第二电极焊盘；所述第一电极焊盘与所述第一电容电极电连接，所述第二电极焊盘与所述第二电容电极电连接；
所述芯片搭载部具有上表面，所述第一半导体芯片搭载于所述芯片搭载部的上表面上，所述第一半导体芯片的第一背面朝向所述上表面；所述第一半导体芯片的第一背面与所述芯片搭载部电连接；
所述第二半导体芯片搭载于所述芯片搭载部的上表面上，所述第二半导体芯片的第二背面朝向所述上表面；
所述第一电极焊盘与所述第一控制极引脚或所述第一控制极焊盘电连接，所述第二电极焊盘与所述第一焊盘电连接。
可选的，本公开至少一实施例所述的半导体器件还包括第一电极引脚和第二电极引脚；
所述第一电极引脚与所述第一焊盘电连接，所述第二电极引脚与所述芯片搭载部电连接。
本公开至少一实施例所述的半导体器件能够保证较好的钳位效果，并简化布线。
附图说明
图1是本公开至少一实施例所述的半导体器件包括的第一晶体管和第二晶体管之间的连接关系示意图；
图2是本公开至少一实施例所述的半导体器件的结构图；
图3是本公开至少一实施例所述的半导体器件的结构图；
图4是图3沿A-A’方向的截面图；
图5是本公开至少一实施例所述的半导体器件的结构图；
图6是本公开至少一实施例所述的半导体器件的结构图；
图7是本公开至少一实施例所述的半导体器件的结构图；
图8是本公开至少一实施例所述的半导体器件的结构图；
图9是本公开至少一实施例所述的半导体器件的结构图；
图10是本公开至少一实施例所述的半导体器件包括的第一晶体管和电容之间的连接关系示意图
图11是本公开至少一实施例所述的半导体器件的结构图；
图12是包括本公开至少一实施例所述的半导体芯片的开关系统的结构图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而 不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为三极管时，所述控制极可以为基极，所述第一极可以为集电极，所述第二极可以发射极；或者，所述控制极可以为基极，所述第一极可以为发射极，所述第二极可以集电极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述控制极可以为栅极，所述第一极可以为漏极，所述第二极可以为源极；或者，所述控制极可以为栅极，所述第一极可以为源极，所述第二极可以为漏极。
本公开至少一实施例所述的半导体器件包括封固体、第一晶体管和第二晶体管，其中，所述第一晶体管包括控制极、第一端子和第二端子；
所述第一晶体管用于在其控制极的电位的控制下，使得电流能够从所述第一端子流向所述第二端子；所述第二晶体管的第一电极与所述第一晶体管的控制极电连接，所述第二晶体管的第二电极与所述第一晶体管的第二端子电连接；
所述第一晶体管和所述第二晶体管都被同一所述封固体封固，所述第一晶体管的控制极与第一控制极引脚电连接，所述第二晶体管的控制极与第二控制极引脚电连接。
在本公开至少一实施例中，所述第一晶体管的控制极与所述第一控制极引脚之间可以通过绑定线电连接，所述第二晶体管的控制极与所述第二控制极引脚之间可以通过绑定线电连接，由于提供至所述第二控制极引脚的是电压信号，回路上的干扰信号也较小；所述绑定线为导线。
本公开至少一实施例所述的半导体器件将第一晶体管和第二晶体管(所述第二晶体管可以为米勒钳位晶体管)都被同一所述封固体封固，以缩短所述第二晶体管和所述第一晶体管的控制极之间的距离，以保证较好的钳位效果，并简化布线。
在具体实施时，所述第一控制极引脚至少部分设置于所述封固体外部， 所述第二控制极引脚至少部分设置于所述封固体外部，但不以此为限。
在具体实施时，所述封固体可以由树脂制成，但不以此为限。
可选的，所述第一晶体管为n型晶体管，所述第一端子为第一电极，所述第一电极为漏电极，所述第二端子为第二电极，所述第二电极为源电极；或者，
所述第一晶体管为p型晶体管，所述第一端子为第一电极，所述第一端子为源电极，所述第二端子为第二电极，所述第二端子为漏电极。
如图1所示，本公开至少一实施例所述的半导体器件包括第一晶体管M1和第二晶体管M2；
所述第一晶体管M1用于在其栅极G1的电位的控制下，使得电流可以从第一晶体管M1的漏电极D流向第一晶体管M1的源电极S；
所述第二晶体管M2的漏电极D2与所述第一晶体管M1的栅极G1电连接，所述第二晶体管M2的源电极S2与所述第一晶体管M1的源电极S电连接。
在图1所示的半导体器件的至少一实施例中，M1和M2都为n型MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor,金属-氧化物-半导体场效应晶体管)，但不以此为限。
根据一种具体实施方式，本公开至少一实施例所述的半导体器件还可以包括第一芯片搭载部、第二芯片搭载部、第一半导体芯片、第二半导体芯片、第一控制极引脚和第二控制极引脚；所述第一芯片搭载部与所述第二芯片搭载部相互绝缘；在所述第一半导体芯片上形成有第一晶体管，在所述第二半导体芯片上形成有第二晶体管；
所述第一芯片搭载部的至少一部分、所述第二芯片搭载部的至少一部分、所述第一半导体芯片和所述第二半导体芯片被同一所述封固体封固；
所述第一半导体芯片具有第一表面和与所述第一表面为相反侧的第一背面，所述第二半导体芯片具有第二表面和与所述第二表面为相反侧的第二背面；
在所述第一半导体芯片的第一表面上形成有第一控制极焊盘和第一焊盘，所述第一背面与所述第一晶体管的第一端子电连接；所述第一控制极焊盘分 别与所述第一晶体管的控制极和所述第一控制极引脚电连接，所述第一焊盘与所述第一晶体管的第二端子电连接；
在所述第二半导体芯片的第一表面上形成有第二控制极焊盘和第二焊盘，所述第二背面与所述第二晶体管的第一电极电连接；所述第二控制极焊盘分别与所述第二晶体管的控制极和所述第二控制极引脚电连接，所述第二晶体管的第二电极与所述第二焊盘电连接；
所述第一芯片搭载部具有第一上表面，所述第一半导体芯片搭载于所述第一芯片搭载部的第一上表面上，所述第一半导体芯片的第一背面朝向所述第一上表面；所述第一半导体芯片的第一背面与所述第一芯片搭载部电连接；
所述第二芯片搭载部具有第二上表面，所述第二半导体芯片搭载于所述第二芯片搭载部的第二上表面上，所述第二半导体芯片的第二背面朝向所述第二上表面；所述第二半导体芯片的第二背面与所述第二芯片搭载部电连接。
在实际操作时，本公开至少一实施例所述的半导体器件可以包括两个芯片搭载部和两个半导体芯片；在所述第一半导体芯片上形成有第一晶体管，在所述第二半导体芯片上形成有第二晶体管；所述第一芯片搭载部的至少一部分、所述第二芯片搭载部的至少一部分、所述第一半导体芯片和所述第二半导体芯片被同一所述封固体封固；其中，所述第一晶体管可以为以SiC为材料的MOSFET，所述第二晶体管可以为以Si为材料的MOSFET，但不以此为限。
可选的，所述第二芯片搭载部通过导线与所述第一控制极焊盘电连接，以使得所述第二晶体管的第一电极与所述第一晶体管的控制极电连接；所述第二焊盘与所述第一焊盘电连接，以使得所述第二晶体管的第二电极与所述第一晶体管的第二端子电连接。其中，所述第二芯片搭载部与所述第一控制极焊盘之间的导线短。
可选的，所述第二芯片搭载部通过导线与所述第一控制极引脚电连接，以避免占用晶圆的内部空间，并使得所述第二晶体管的第一电极与所述第一晶体管的控制极电连接；所述第二焊盘与所述第一焊盘电连接，以使得所述第二晶体管的第二电极与所述第一晶体管的第二端子电连接。其中，所述第二芯片搭载部与所述第一控制极引脚之间的导线短。
在具体实施时，本公开至少一实施例所述的半导体器件还可以包括第一电极引脚和第二电极引脚；
所述第一电极引脚与所述第一焊盘电连接，以使得所述第一电极引脚与所述第一晶体管的第二端子电连接；
所述第二电极引脚与所述第一芯片搭载部电连接，以使得所述第二电极引脚与所述第一晶体管的第一端子电连接。
在实际操作时，所述第一电极引脚可以至少部分设置于所述封固体外部，所述第二电极引脚可以至少部分设置于所述封固体外部，但不以此为限。
如图2所示，本公开至少一实施例所述的半导体器件可以包括第一晶体管、第二晶体管、封固体F0、第一芯片搭载部P1、第二芯片搭载部P2、第一半导体芯片C1、第二半导体芯片C2、第一控制极引脚J01、第二控制极引脚J02、第一电极引脚J1和第二电极引脚J2；所述第一芯片搭载部P1与所述第二芯片搭载部P2相互绝缘；在所述第一半导体芯片C1上形成有所述第一晶体管，在所述第二半导体芯片C2上形成有所述第二晶体管；
所述第一芯片搭载部P1、所述第二芯片搭载部P2、所述第一半导体芯片C1和所述第二半导体芯片C2被所述封固体F0封固；
所述第一半导体芯片C1具有第一表面和与所述第一表面为相反侧的第一背面，所述第二半导体芯片C2具有第二表面和与所述第二表面为相反侧的第二背面；
在所述第一半导体芯片C1的第一表面上形成有第一控制极焊盘H01和第一焊盘H1，所述第一背面与所述第一晶体管的第一端子电连接；所述第一控制极焊盘H01分别与所述第一晶体管的控制极和第一控制极引脚J01电连接，所述第一焊盘H1与所述第一晶体管的第二端子电连接；
在所述第二半导体芯片C2的第一表面上形成有第二控制极焊盘H02和第二焊盘H2，所述第二背面与所述第二晶体管的第一电极电连接；所述第二控制极焊盘H02分别与所述第二晶体管的控制极和所述第二控制极引脚J02电连接，所述第二晶体管的第二电极与所述第二焊盘H2电连接；
所述第一芯片搭载部P1具有第一上表面，所述第一半导体芯片C1搭载于所述第一芯片搭载部P1的第一上表面上，所述第一半导体芯片C1的第一 背面朝向所述第一上表面；所述第一半导体芯片C1的第一背面与所述第一芯片搭载部P1电连接，以使得所述第一芯片搭载部P1与所述第一晶体管的第一端子电连接；
所述第二芯片搭载部P2具有第二上表面，所述第二半导体芯片C2搭载于所述第二芯片搭载部P2的第二上表面上，所述第二半导体芯片C2的第二背面朝向所述第二上表面；所述第二半导体芯片C2的第二背面与所述第二芯片搭载部P2电连接，以使得所述第二芯片搭载部P2与所述第二晶体管的第一电极电连接；
所述第二芯片搭载部P2通过第一导线L1与所述第一控制极焊盘H01电连接，以使得所述第二晶体管的第一电极与所述第一晶体管的控制极电连接，将所述第一控制极焊盘H01设置为与所述第二芯片搭载部P2距离较近，以使得所述第一导线L1较短，以保证最好的钳位效果，并简化布线；
所述第二焊盘H2与所述第一焊盘H1电连接，以使得所述第一晶体管的第二端子与所述第二晶体管的第二电极电连接；
所述第一电极引脚J1与所述第一焊盘H1电连接，以使得所述第一电极引脚J1与所述第一晶体管的第二端子电连接；
所述第二电极引脚J2与所述第一芯片搭载部P1电连接，以使得所述第二电极引脚J2与所述第一晶体管的第一端子电连接。
在图2所示的至少一实施例中，所述第一晶体管的控制极为栅极，所述第一晶体管的第一端子为漏电极，所述第一晶体管的第二端子为源电极，所述第二晶体管的控制极为栅极，所述第二晶体管的第一电极为漏电极，所述第二晶体管的第二电极为源电极，但不以此为限。在图2所示的至少一实施例中，第一晶体管为以SiC为材料的MOSFET，所述第二晶体管可以为以Si为材料的MOSFET；所述第一芯片搭载部P1设置于所述第二芯片搭载部P2右侧，但不以此为限。在实际操作时，P1也可以设置于P2左侧。
也可以在SiC MOSFET晶圆制作时，利用很小的面积，设置第二晶体管(所述第二晶体管为米勒钳位晶体管)，以将米勒钳位晶体管集成于SiC MOSFET内部。
在图2所示的至少一实施例中，配置在右侧的金属板形成第一芯片搭载 部P1，配置在右侧的金属板形成第二芯片搭载部P2；所述第一芯片搭载部P1以与所述第二电极引脚J2连结的方式一体的形成，所述第一芯片搭载部P1与所述第二电极引脚J2电连接；以分离并隔着所述第二电极引脚J2的方式配置第一控制电极引脚J01和第一电极引脚J1。具体的，如图2所示，在J2的右侧配置有J1，在J2的左侧配置有J01，在J01的左侧配置有J02，J02、J01、J2和J1相互绝缘。
在图2所示的至少一实施例中，P1设置于P2的右侧，并J02、J01、J2和J1从左至右依次排列，以使得P2上的第二控制极焊盘H02与J02距离较近，P1上的第一控制极焊盘H01与J01距离较近，P1上的第一焊盘H1与J1距离较近，方便H02与J02连接，方便H01与J01连接，方便H1与J1连接。
在图2所示的至少一实施例中，在所述第一芯片搭载部P1上，例如，经由银焊剂或锡焊构成的导电性粘结材料而搭载有第一半导体芯片C1；在所述第一半导体芯片C1上，形成有以SiC为材料的MOSFET；所述第一半导体芯片C1的第一背面成为漏电极，在所述第一半导体芯片C1的第一表面形成有第一控制极焊盘H01和第一焊盘H1；也即，所述第一晶体管的漏电极形成于所述第一半导体芯片C1的第一背面，与所述第一晶体管的栅极电连接的第一控制极焊盘H01，以及，与所述第一晶体管的源电极电连接的第一焊盘H1设置于所述第一半导体芯片C1的第一表面。
在图2所示的至少一实施例中，在所述第二芯片搭载部P2上，例如，经由银焊剂或锡焊构成的导电性粘结材料而搭载有第二半导体芯片C2；在所述第二半导体芯片C2上，形成有以Si为材料的MOSFET；所述第二半导体芯片C2的第二背面成为漏电极，在所述第二半导体芯片C2的第一表面形成有第二控制极焊盘H02和第二焊盘H2；也即，所述第二晶体管的漏电极形成于所述第二半导体芯片C2的第二背面，与所述第二晶体管的栅极电连接的第二控制极焊盘H02，以及，与所述第二晶体管的源电极电连接的第二焊盘H2设置于所述第二半导体芯片C2的第二表面。
在图2所示的至少一实施例中，由于第一半导体芯片C1经由导电性粘结材料而搭载在所述第一芯片搭载部P1上，形成于所述第一半导体芯片C1背 面的第一晶体管的漏电极与所述第一芯片搭载部P1电连接；由于第二半导体芯片C2经由导电性粘结材料而搭载在所述第二芯片搭载部P2上，形成于所述第二导体芯片C2背面的第二晶体管的漏电极与所述第二芯片搭载部P2电连接。
在图2所示的至少一实施例中，所述第一芯片搭载部P1、所述第二芯片搭载部P2、所述第一半导体芯片C1、所述第二半导体芯片C2、J02的一部分、J01的一部分、J2的一部分和J1的一部分被所述封固体F0封固。
在图2和图3中，在J02的下方绘制有(G2)，指的是J02可以与第二晶体管的栅极G2电连接；在J01的下方绘制有(G1)，指的是J01可以与第一晶体管的栅极G1电连接；在J2的下方绘制有(D)，指的是J2可以与第一晶体管的漏电极D电连接；在J1的下方绘制有(S)，指的是J1可以与第一晶体管的源电极S电连接。
在本公开至少一实施例中，所述第一芯片搭载部可以设置于所述第二芯片搭载部的第一侧边，所述第一晶体管的导通电流大于所述第二晶体管的导通电流，所述第一晶体管的导通速度大于所述第二晶体管的导通速度。
在具体实施时，所述第一侧边可以为右侧边或左侧边，以SiC为材料的MOSFET的导通电流大于以Si为材料的MOSFET的导通电流，以SiC为材料的MOSFET的导通速度大于以Si为材料的MOSFET的导通速度。
图3所示的半导体器件的至少一实施例与图2所示的半导体器件的至少一实施例的区别如下：所述第二芯片搭载部P2通过第二导线L2与所述第一控制极引脚J01电连接，以使得所述第二晶体管的第一电极与所述第一晶体管的控制极电连接，将所述第一控制极引脚J01设置为与所述第二芯片搭载部P2距离较近，以使得所述第二导线L2较短，以保证最好的钳位效果，并简化布线。并且，图3所示的半导体器件的至少一实施例的连接方法中，使得引线与引脚所需要的连接部的复合部位，由芯片上改到了引脚上，使得连接部有更大的连接面积，在制造方面也有好处。
图4是图3沿A-A’方向的截面图。
如图4所示，所述第一芯片搭载部P1设置于第一基板F1上，所述第二芯片搭载部P2设置于第二基板F2上；
所述第一芯片搭载部P1上搭载有第一半导体芯片，所述第二芯片搭载部P2上搭载有第二半导体芯片；
所述第二芯片搭载部P2与所述基板F1之间的第二距离，大于所述第一芯片搭载部P1与所述基板F1之间的第一距离L；
在所述第二芯片搭载部P2与所述基板之间设置有隔离层G0，以将所述第二芯片搭载部P2垫高，使得所述第二芯片搭载部P2高于所述第一芯片搭载部P1；所述隔离层G0通过绝缘粘结材料分别与所述基板F1和所述第二芯片搭载部P2粘结。
可选的，所述隔离层G0由AL2O3制成，所述第一芯片搭载部P1可以通过焊锡膏设置于所述第一基板F1上，但不以此为限。
如图4所示，所述第二芯片搭载部P2比所述第一芯片搭载部P1高，这样在制作所述第二晶体管的第二电极通过导线与所述第一晶体管的第二端子之间的导线时，可以使得对第二晶体管的应力大，减小对第一晶体管的应力，保护第一晶体管。
如图4所示，所述第二晶体管的第二电极(图4中未示出，在所述第二半导体芯片上形成有第二晶体管)通过导线与所述第一晶体管的第二端子(图4中未示出，在所述第一半导体芯片上形成有第一晶体管)电连接；
所述导线包括第一导线部L11、第二导线部L12和第三导线部L13；
所述第一导线部L11的第一端与所述第二晶体管的第二电极电连接，所述第一导线部L11的第二端与所述第二导线部L12的第一端电连接，所述第二导线部L12的第二端与所述第三导线部L13的第一端电连接，所述第三导线部L13的第二端与所述第一晶体管的第二端子电连接；
连接两个半导体芯片的的引线会在两端各进行一次引线与半导体片的电连接。本公开至少一实施例先从高位的半导体芯片进行第一次引线连接，再在低位的芯片上进行第二次引线连接，这样连接的特征是：所述第二芯片搭载部P2的第二上表面与所述第一导线部L11垂直，所述第一芯片搭载部P2的第一上表面与所述第三导线部L13不垂直，以使得对第二晶体管的应力大，减小对第一晶体管的应力，保护第一晶体管。根据另一种具体实施方式，本公开至少一实施例所述的半导体器件还可以包括第一芯片搭载部、第二芯片 搭载部、第一半导体芯片、第二半导体芯片、第一控制极引脚和第二控制极引脚；所述第一芯片搭载部的至少一部分、所述第二芯片搭载部的至少一部分、所述第一半导体芯片和所述第二半导体芯片都被同一所述封固体封固；在所述第一半导体芯片上形成有第一晶体管，在所述第二半导体芯片上形成有第二晶体管；
所述第一半导体芯片具有第一表面和与所述第一表面为相反侧的第一背面，所述第二半导体芯片具有第二表面和与所述第二表面为相反侧的第二背面；
在所述第一半导体芯片的第一表面上形成有第一控制极焊盘和第一焊盘，所述第一背面与所述第一晶体管的第一端子电连接；所述第一控制极焊盘分别与所述第一晶体管的控制极和第一控制极引脚电连接，所述第一焊盘与所述第一晶体管的第二端子电连接；
在所述第二半导体芯片的第一表面上形成有第二控制极焊盘和第二焊盘，所述第二背面与所述第二晶体管的第一电极电连接；所述第二控制极焊盘分别与所述第二晶体管的控制极和第二控制极引脚电连接，所述第二晶体管的第二电极与所述第二焊盘电连接；
所述第一芯片搭载部具有第一上表面，所述第一半导体芯片搭载于所述第一芯片搭载部的第一上表面上，所述第一半导体芯片的第一背面朝向所述第一上表面；所述第一半导体芯片的第一背面与所述第一芯片搭载部电连接；
所述第二芯片搭载部具有第二上表面和与所述第二上表面为相反侧的第二下表面，所述第二芯片搭载部搭载于所述第一芯片搭载部的第一上表面上，所述第二芯片搭载部与所述第一芯片搭载部之间绝缘，所述第二芯片搭载部的第二下表面朝向所述第一上表面；
所述第二半导体芯片搭载于所述第二芯片搭载部的第二上表面上，所述第二半导体芯片的第二背面朝向所述第二上表面；所述第二半导体芯片的第二背面与所述第二芯片搭载部电连接。
在具体实施时，本公开至少一实施例所述的半导体器件还包括第一芯片搭载部、第二芯片搭载部、第一半导体芯片、第二半导体芯片、第一控制极引脚和第二控制极引脚；在所述第一半导体芯片上形成有第一晶体管，在所 述第二半导体芯片上形成有第二晶体管；
所述第一芯片搭载部的至少一部分、所述第二芯片搭载部的至少一部分、所述第一半导体芯片和所述第二半导体芯片都被同一所述封固体封固；
所述第一半导体芯片和所述第二芯片搭载部搭载于所述第一芯片搭载部上，所述第一芯片搭载部与所述第二芯片搭载部绝缘，所述第二半导体芯片搭载于所述第二芯片搭载部上。
可选的，所述第二芯片搭载部通过导线与所述第一控制极焊盘电连接，以使得所述第二晶体管的第一电极与所述第一晶体管的控制极电连接；所述第二焊盘与所述第一焊盘电连接，以使得所述第二晶体管的第二电极与所述第一晶体管的第二端子电连接。其中，所述第二芯片搭载部与所述第一控制极焊盘之间的导线短。
可选的，所述第二芯片搭载部通过导线与所述第一控制极引脚电连接，以使得所述第二晶体管的第一电极与所述第一晶体管的控制极电连接，所述第二焊盘与所述第一焊盘电连接，以使得所述第二晶体管的第二电极与所述第一晶体管的第二端子电连接。其中，所述第二芯片搭载部与所述第一控制极引脚之间的导线短。
在本公开至少一实施例中，所述的半导体器件还可以包括第一电极引脚和第二电极引脚；
所述第一电极引脚与所述第一焊盘电连接，以使得所述第一电极引脚与所述第一晶体管的第二端子电连接；
所述第二电极引脚与所述第一芯片搭载部电连接，以使得所述第二电极引脚与所述第一晶体管的第一端子电连接。
在实际操作时，所述第一电极引脚和所述第二电极引脚可以至少部分设置于所述封固体外部，但不以此为限。
如图5所示，本公开至少一实施例所述的半导体器件可以包括第一晶体管、第二晶体管、封固体F0、第一芯片搭载部P1、第二芯片搭载部P2、第一半导体芯片C1、第二半导体芯片C2、第一控制极引脚J01、第二控制极引脚J02、第一电极引脚J1和第二电极引脚J2；所述第一芯片搭载部P1、所述第二芯片搭载部P2、所述第一半导体芯片C1和所述第二半导体芯片C2都被 同一所述封固体F0封固；在所述第一半导体芯片C1上形成有第一晶体管，在所述第二半导体芯片C2上形成有第二晶体管；
所述第一半导体芯片C1具有第一表面和与所述第一表面为相反侧的第一背面，所述第二半导体芯片C2具有第二表面和与所述第二表面为相反侧的第二背面；
在所述第一半导体芯片C1的第一表面上形成有第一控制极焊盘H01和第一焊盘H1，所述第一背面与所述第一晶体管的第一端子电连接；所述第一控制极焊盘H01分别与所述第一晶体管的控制极和第一控制极引脚J01电连接，所述第一焊盘H1与所述第一晶体管的第二端子电连接；
在所述第二半导体芯片C2的第一表面上形成有第二控制极焊盘H02和第二焊盘H2，所述第二背面与所述第二晶体管的第一电极电连接；所述第二控制极焊盘H02分别与所述第二晶体管的控制极和第二控制极引脚J02电连接，所述第二晶体管的第二电极与所述第二焊盘H2电连接；
所述第一芯片搭载部P1具有第一上表面，所述第一半导体芯片C1搭载于所述第一芯片搭载部P1的第一上表面上，所述第一半导体芯片C1的第一背面朝向所述第一上表面；所述第一半导体芯片C1的第一背面与所述第一芯片搭载部P1电连接；
所述第二芯片搭载部P2具有第二上表面和与所述第二上表面为相反侧的第二下表面，所述第二芯片搭载部P2搭载于所述第一芯片搭载部P1的第一上表面上，所述第二芯片搭载部P2与所述第一芯片搭载部P1之间绝缘，所述第二芯片搭载部P2的第二下表面朝向所述第一上表面；
所述第二半导体芯片C2搭载于所述第二芯片搭载部P2的第二上表面上，所述第二半导体芯片C2的第二背面朝向所述第二上表面；所述第二半导体芯片C2的第二背面与所述第二芯片搭载部P2电连接；
所述第一电极引脚J1与所述第一焊盘H1电连接，以使得所述第一电极引脚J1与所述第一晶体管的第二端子电连接；
所述第二电极引脚J2与所述第一芯片搭载部P1电连接，以使得所述第二电极引脚J2与所述第一晶体管的第一端子电连接；
所述第二芯片搭载部P2通过第三导线L3与所述第一控制极焊盘H01电 连接，以使得所述第二晶体管的第一电极与所述第一晶体管的控制极电连接，将所述第一控制极焊盘H01设置为与所述第二芯片搭载部P2距离较近，以使得所述第三导线L3较短，以保证最好的钳位效果，并简化布线；
所述第二焊盘H2与所述第一焊盘H1电连接，以使得所述第二晶体管的第二电极与所述第一晶体管的第二端子电连接。
在图5所示的至少一实施例中，所述第一晶体管的控制极为栅极，所述第一晶体管的第一端子为漏电极，所述第一晶体管的第二端子为源电极，所述第二晶体管的控制极为栅极，所述第二晶体管的第一电极为漏电极，所述第二晶体管的第二电极为源电极，但不以此为限。
在图5所示的至少一实施例中，第一晶体管为以SiC为材料的MOSFET，所述第二晶体管可以为以Si为材料的MOSFET；所述第一芯片搭载部P1设置于所述第二芯片搭载部P2右侧，但不以此为限。在实际操作时，P1也可以设置于P2左侧。
在图5所示的至少一实施例中，第一芯片搭载部P1和第二芯片搭载部P2为金属板；所述第一芯片搭载部P1以与所述第二电极引脚J2连结的方式一体的形成，所述第一芯片搭载部P1与所述第二电极引脚J2电连接；以分离并隔着所述第二电极引脚J2的方式配置第一控制电极引脚J01和第一电极引脚J1。具体的，如图5所示，在J2的右侧配置有J1，在J2的左侧配置有J01，在J01的左侧配置有J02，J02、J01、J2和J1相互绝缘。
在图5所示的至少一实施例中，P1设置于P2的右侧，并J02、J01、J2和J1从左至右依次排列，以使得P2上的第二控制极焊盘H02与J02距离较近，P1上的第一控制极焊盘H01与J01距离较近，P1上的第一焊盘H1与J1距离较近，方便H02与J02连接，方便H01与J01连接，方便H1与J1连接。
在图5所示的至少一实施例中，在所述第一芯片搭载部P1的第一上表面上，例如，经由银焊剂或锡焊构成的导电性粘结材料而搭载有第一半导体芯片C1；在所述第一半导体芯片C1上，形成有以SiC为材料的MOSFET；所述第一半导体芯片C1的第一背面成为漏电极，在所述第一半导体芯片C1的第一表面形成有第一控制极焊盘H01和第一焊盘H1；也即，所述第一晶体管 的漏电极形成于所述第一半导体芯片C1的第一背面，与所述第一晶体管的栅极电连接的第一控制极焊盘H01，以及，与所述第一晶体管的源电极电连接的第一焊盘H1设置于所述第一半导体芯片C1的第一表面。
在图5所示的至少一实施例中，第二芯片搭载部P2设置于所述第一芯片搭载部P1的第一上表面上，并所述第二芯片搭载部P2与所述第一芯片搭载部P1之间绝缘；所述第二芯片搭载部P2的第二下表面朝向所述第一上表面；
在图5所示的至少一实施例中，在所述第二芯片搭载部P2的第二上表面上，例如，经由银焊剂或锡焊构成的导电性粘结材料而搭载有第二半导体芯片C2；在所述第二半导体芯片C2上，形成有以Si为材料的MOSFET；所述第二半导体芯片C2的第二背面成为漏电极，在所述第二半导体芯片C2的第一表面形成有第二控制极焊盘H02和第二焊盘H2；也即，所述第二晶体管的漏电极形成于所述第二半导体芯片C2的第二背面，与所述第二晶体管的栅极电连接的第二控制极焊盘H02，以及，与所述第二晶体管的源电极电连接的第二焊盘H2设置于所述第二半导体芯片C2的第二表面。
在图5所示的至少一实施例中，由于第一半导体芯片C1经由导电性粘结材料而搭载在所述第一芯片搭载部P1上，形成于所述第一半导体芯片C1背面的第一晶体管的漏电极与所述第一芯片搭载部P1电连接；由于第二半导体芯片C2经由导电性粘结材料而搭载在所述第二芯片搭载部P2上，形成于所述第二导体芯片C2背面的第二晶体管的漏电极与所述第二芯片搭载部P2电连接。
在图5所示的至少一实施例中，所述第一芯片搭载部P1、所述第二芯片搭载部P2、所述第一半导体芯片C1、所述第二半导体芯片C2、J02的一部分、J01的一部分、J2的一部分和J1的一部分被所述封固体F0封固。
在本公开至少一实施例中，所述第一芯片搭载部可以设置于所述第二芯片搭载部的第一侧边，所述第一晶体管的导通电流大于所述第二晶体管的导通电流，所述第一晶体管的导通速度大于所述第二晶体管的导通速度。
在具体实施时，所述第一侧边可以为右侧边或左侧边，以SiC为材料的MOSFET的导通电流大于以Si为材料的MOSFET的导通电流，以SiC为材料的MOSFET的导通速度大于以Si为材料的MOSFET的导通速度。
在图5和图6中，在J02的下方绘制有(G2)，指的是J02可以与第二晶体管的栅极G2电连接；在J01的下方绘制有(G1)，指的是J01可以与第一晶体管的栅极G1电连接；在J2的下方绘制有(D)，指的是J2可以与第一晶体管的漏电极D电连接；在J1的下方绘制有(S)，指的是J1可以与第一晶体管的源电极S电连接。
图6所示的半导体器件的至少一实施例与图5所示的半导体器件的至少一实施例的区别如下：所述第二芯片搭载部P2通过第四导线L4与所述第一控制极引脚J01电连接，以使得所述第二晶体管的第一电极与所述第一晶体管的控制极电连接，将所述第一控制极引脚J01设置为与所述第二芯片搭载部P2距离较近，以使得所述第四导线L4较短，以保证最好的钳位效果，并简化布线。
根据又一种具体实施方式，本公开至少一实施例所述的半导体器件还可以包括第一芯片搭载部、第二芯片搭载部、第一半导体芯片、第二半导体芯片、第一控制极引脚和第二控制极引脚；所述第一芯片搭载部与所述第二芯片搭载部相互绝缘；在所述第一半导体芯片上形成有第一晶体管，在所述第二半导体芯片上形成有第二晶体管；
所述第一芯片搭载部的至少一部分、所述第二芯片搭载部的至少一部分、所述第一半导体芯片和所述第二半导体芯片被同一所述封固体封固；
所述第一半导体芯片具有第一表面和与所述第一表面为相反侧的第一背面，所述第二半导体芯片具有第二表面和与所述第二表面为相反侧的第二背面；
在所述第一半导体芯片的第一表面上形成有第一控制极焊盘、至少一个第一焊盘和至少一个第二焊盘，所述第一控制极焊盘分别与所述第一晶体管的控制极和所述第一控制极引脚电连接，所述第一焊盘与所述第一晶体管的第二端子电连接，所述第二焊盘与所述第一晶体管的第一端子电连接；
在所述第二半导体芯片的第一表面上形成有第二控制极焊盘和第三焊盘，所述第二背面与所述第二晶体管的第一电极电连接；所述第二控制极焊盘分别与所述第二晶体管的控制极和所述第二控制极引脚电连接，所述第二晶体管的第二电极与所述第三焊盘电连接；
所述第一芯片搭载部具有第一上表面，所述第一半导体芯片搭载于所述第一芯片搭载部的第一上表面上，所述第一半导体芯片的第一背面朝向所述第一上表面；
所述第二芯片搭载部具有第二上表面，所述第二半导体芯片搭载于所述第二芯片搭载部的第二上表面上，所述第二半导体芯片的第二背面朝向所述第二上表面；所述第二半导体芯片的第二背面与所述第二芯片搭载部电连接。
在具体实施时，所述至少一个所述第一焊盘之间电连接，所述至少一个所述第二焊盘之间电连接，但不以此为限。
在具体实施时，所述第一焊盘与所述第二焊盘之间绝缘，所述第一焊盘与所述第一控制极焊盘之间绝缘，所述第二焊盘与所述第一控制极焊盘之间绝缘。
在本公开至少一实施例中，所述第一晶体管可以为以GaN为材料的场效应晶体管，所述第二晶体管可以为以Si为材料的MOSFET，但不以此为限。
在具体实施时，本公开至少一实施例所述的半导体器件还可以包括第一芯片搭载部、第二芯片搭载部、第一半导体芯片和第二半导体芯片；在所述第一半导体芯片上形成有第一晶体管，在所述第二半导体芯片上形成有第二晶体管；所述第一芯片搭载部与所述第二芯片搭载部相互绝缘；所述第一芯片搭载部的至少一部分、所述第二芯片搭载部的至少一部分、所述第一半导体芯片和所述第二半导体芯片被同一所述封固体封固；
在所述第一半导体芯片的第一表面上形成有第一控制极焊盘、至少一个第一焊盘和至少一个第二焊盘，在所述第二半导体芯片的第一表面上形成有第二控制极焊盘和第三焊盘，所述第二背面与所述第二晶体管的第一电极电连接，所述第二半导体芯片的第二背面与所述第二芯片搭载部电连接，以使得所述第二芯片搭载部与所述第二晶体管的第一电极电连接。
可选的，所述第二芯片搭载部通过导线与所述第一控制极焊盘电连接，以使得所述第二晶体管的第一电极与所述第一晶体管的控制极电连接；所述第三焊盘与所述第一焊盘电连接，以使得所述第二晶体管的第二电极与所述第一晶体管的第二端子电连接。其中，所述第二芯片搭载部与所述第一控制极焊盘之间的导线短。
可选的，所述第二芯片搭载部通过导线与所述第一控制极引脚电连接，以使得所述第二晶体管的第一电极与所述第一晶体管的控制极电连接，所述第三焊盘与所述第一焊盘电连接，以使得所述第二晶体管的第二电极与所述第一晶体管的第二端子电连接。其中，所述第二芯片搭载部与所述第一控制极引脚之间的导线短。
在具体实施时，本公开至少一实施例所述的半导体器件还包括第一电极引脚和第二电极引脚；
所述第一电极引脚与所述第一焊盘电连接，以使得所述第一电极引脚与所述第一晶体管的第二端子电连接；
所述第二电极引脚与所述第二焊盘电连接，以使得所述第二电极引脚与所述第一晶体管的第一端子电连接。
在实际操作时，所述第一电极引脚和所述第二电极引脚可以至少部分设置于所述封固体外部，但不以此为限。
在本公开至少一实施例中，所述第一芯片搭载部设置于所述第二芯片搭载部的第一侧边，所述第一晶体管的导通电流大于所述第二晶体管的导通电流，所述第一晶体管的导通速度大于所述第二晶体管的导通速度。
可选的，第一侧边可以为左侧边，或者，所述第一侧边可以为右侧边；当第一晶体管为GaN为材料的场效应晶体管，所述第二晶体管为以Si为材料的MOSFET时，第一晶体管的导通电流大于所述第二晶体管的导通电流，所述第一晶体管的导通速度大于所述第二晶体管的导通速度。
如图7所示，本公开至少一实施例所述的半导体器件可以包括第一晶体管、第二晶体管、封固体F0、第一芯片搭载部P1、第二芯片搭载部P2、第一半导体芯片C1、第二半导体芯片C2、第一控制极引脚J01、第二控制极引脚J02、第一电极引脚J1和第二电极引脚J2；所述第一芯片搭载部P1与所述第二芯片搭载部P2相互绝缘；在所述第一半导体芯片C1上形成有第一晶体管，在所述第二半导体芯片C2上形成有第二晶体管；
所述第一芯片搭载部P1、所述第二芯片搭载部P2、所述第一半导体芯片C1和所述第二半导体芯片C2被同一所述封固体F0封固；
所述第一半导体芯片C1具有第一表面和与所述第一表面为相反侧的第 一背面，所述第二半导体芯片C2具有第二表面和与所述第二表面为相反侧的第二背面；
在所述第一半导体芯片C1的第一表面上形成有第一控制极焊盘H01、第一个第一焊盘H11、第二个第一焊盘H21、第三个第一焊盘H31、第一个第二焊盘H12、第二个第二焊盘H22和第三个第二焊盘H32，所述第一控制极焊盘H01分别与所述第一晶体管的控制极和所述第一控制极引脚J01电连接；
H11、H21和H31相互电连接，H11、H21和H31分别与所述第一晶体管的第二端子电连接；
H12、H22和H32相互电连接，H12、H22和H32分别与所述第一晶体管的第一端子电连接；
在所述第二半导体芯片C2的第一表面上形成有第二控制极焊盘H02和第三焊盘H3，所述第二背面与所述第二晶体管的第一电极电连接；所述第二控制极焊盘H02分别与所述第二晶体管的控制极和所述第二控制极引脚J02电连接，所述第二晶体管的第二电极与所述第三焊盘H3电连接；
所述第一芯片搭载部P1具有第一上表面，所述第一半导体芯片C1搭载于所述第一芯片搭载部P1的第一上表面上，所述第一半导体芯片C1的第一背面朝向所述第一上表面；
所述第二芯片搭载部P2具有第二上表面，所述第二半导体芯片C2搭载于所述第二芯片搭载部P2的第二上表面上，所述第二半导体芯片C2的第二背面朝向所述第二上表面；所述第二半导体芯片C2的第二背面与所述第二芯片搭载部P2电连接，以使得所述第二晶体管的第一电极与所述第二芯片搭载部P2电连接；
所述第一晶体管为以GaN为材料的场效应晶体管，所述第二晶体管为以Si为材料的MOSFET。
在图7所示的至少一实施例中，所述第二芯片搭载部P2通过第五导线L5与所述第一控制极引脚J01电连接，以使得所述第二晶体管的第一电极与所述第一晶体管的控制极电连接；其中，所述第二芯片搭载部P2与所述第一控制极引脚J01之间的第五导线L5短；
所述第三焊盘H3分别与H11、H21和H31电连接，以使得所述第二晶 体管的第二电极与所述第一晶体管的第二端子电连接。
在图7所示的至少一实施例中，所述第一芯片搭载部P1以与所述第一电极引脚J1连结的方式一体的形成，以使得所述第一芯片搭载部P1与所述第一电极引脚J1电连接，并H11与所述第一芯片搭载部P1电连接，以使得H11与J1电连接，并由于H11、H21与H31之间电连接，则H21与J1电连接，H31与J1电连接；
H12、H22和H32分别与J2电连接。
在图7所示的至少一实施例中，所述第一晶体管的控制极为栅极，所述第一晶体管的第一端子为漏电极，所述第一晶体管的第二端子为源电极，所述第二晶体管的控制极为栅极，所述第二晶体管的第一电极为漏电极，所述第二晶体管的第二电极为源电极，但不以此为限。
在图7所示的至少一实施例中，第一芯片搭载部P1和所述第一半导体芯片C1可以沿竖直方向排列，但不以此为限。
在图7所示的至少一实施例中，J02、J01、J2和J1从左至右依次排布，J02、J01、J2和J1相互绝缘；H11、H21和H31从上至下依次排列，H12、H22和H32从上至下依次排列，H11、H21和H31靠近所述第二半导体芯片C2，以方便H11、H21和H31与H3电连接；H01设置于所述第一半导体芯片C1的左下角，以方便H01与J01电连接。
在图7所示的至少一实施例中，所述第一晶体管为以GaN为材料的场效应晶体管，所述第二晶体管为以Si为材料的MOSFET；所述第一芯片搭载部P1设置于所述第二芯片搭载部P2右侧，但不以此为限。在实际操作时，P1也可以设置于P2左侧。
在图7所示的至少一实施例中，在所述第一芯片搭载部P1的第一上表面上，例如，经由银焊剂或锡焊构成的导电性粘结材料而搭载有第一半导体芯片C1；在所述第一半导体芯片C1上，形成有以GaN为材料的场效应晶体管；在所述第一半导体芯片C1的第一表面形成有第一控制极焊盘H01、第一个第一焊盘H11、第二个第一焊盘H21、第三个第一焊盘H31、第一个第二焊盘H12、第二个第二焊盘H22和第三个第二焊盘H32。
在图7所示的至少一实施例中，在所述第二芯片搭载部P2的第二上表面 上，例如，经由银焊剂或锡焊构成的导电性粘结材料而搭载有第二半导体芯片C2；在所述第二半导体芯片C2上，形成有以Si为材料的MOSFET；所述第二半导体芯片C2的第二背面成为漏电极，在所述第二半导体芯片C2的第二表面形成有第二控制极焊盘H02和第三焊盘H3；也即，所述第二晶体管的漏电极形成于所述第二半导体芯片C2的第二背面，与所述第二晶体管的栅极电连接的第二控制极焊盘H02，以及，与所述第二晶体管的源电极电连接的第三焊盘H3设置于所述第二半导体芯片C2的第二表面。
在图7所示的至少一实施例中，由于第二半导体芯片C2经由导电性粘结材料而搭载在所述第二芯片搭载部P2上，形成于所述第二导体芯片C2背面的第二晶体管的漏电极与所述第二芯片搭载部P2电连接。
在图7所示的至少一实施例中，所述第一芯片搭载部P1、所述第二芯片搭载部P2、所述第一半导体芯片C1、所述第二半导体芯片C2、J02的一部分、J01的一部分、J2的一部分和J1的一部分被所述封固体F0封固。
在图7和图8中，在J02的下方绘制有(G2)，指的是J02可以与第二晶体管的栅极G2电连接；在J01的下方绘制有(G1)，指的是J01可以与第一晶体管的栅极G1电连接；在J2的下方绘制有(D)，指的是J2可以与第一晶体管的漏电极D电连接；在J1的下方绘制有(S)，指的是J1可以与第一晶体管的源电极S电连接。
在具体实施时，所述第二芯片搭载部P2也可以通过导线与所述第一控制极焊盘H01电连接，以使得所述第二晶体管的第一电极与所述第一晶体管的控制极电连接；其中，所述第二芯片搭载部P2与所述第一控制极焊盘H01之间的导线短。
图8所示的至少一实施例与图7所示的至少一实施例的区别在于：第一芯片搭载部P1沿水平方向排列，第一半导体芯片C1沿水平方向排列，以使得H11、H21和H31由右至左依次排列，并使得H12、H22和H32从右至左依次排列，并H31与H3电连接，H11与J1电连接。
在图8所示的至少一实施例中，所述第二芯片搭载部P2通过第六导线L6与所述第一控制极引脚J01电连接，以使得所述第二晶体管的第一电极与所述第一晶体管的控制极电连接；其中，所述第二芯片搭载部P2与所述第一 控制极引脚J01之间的第六导线L6短。
在图8所示的至少一实施例中，所述第一芯片搭载部P1以与所述第一电极引脚J1连结的方式一体的形成，以使得所述第一芯片搭载部P1与所述第一电极引脚J1电连接，并H11与所述第一芯片搭载部P1电连接，以使得H11与J1电连接，并由于H11、H21与H31之间电连接，则H21与J1电连接，H31与J1电连接。
可选的，所述第一芯片搭载部和所述第二芯片搭载部可以都设置于同一基板上；
所述第二芯片搭载部与所述基板之间的第二距离，大于所述第一芯片搭载部与所述基板之间的第一距离。
在实际操作时，在所述第二芯片搭载部与所述基板之间可以设置有隔离层，以将所述第二芯片搭载部垫高，使得所述第二芯片搭载部高于所述第一芯片搭载部；所述隔离层通过绝缘粘结材料分别与所述基板和所述第二芯片搭载部粘结。例如，所述隔离层可以由AL2O3制成，但不以此为限。
在具体实施时，所述第二芯片搭载部比所述第一芯片搭载部高，这样在制作所述第二晶体管的第二电极通过导线与所述第一晶体管的第二端子之间的导线时，可以使得对第二晶体管的应力大，减小对第一晶体管的应力，保护第一晶体管。
在具体实施时，所述第二晶体管的第二电极通过导线与所述第一晶体管的第二端子电连接；
所述导线包括第一导线部、第二导线部和第三导线部；
所述第一导线部的第一端与所述第二晶体管的第二电极电连接，所述第一导线部的第二端与所述第二导线部的第一端电连接，所述第二导线部的第二端与所述第三导线部的第一端电连接，所述第三导线部的第二端与所述第一晶体管的第二端子电连接；
所述第二芯片搭载部的第二上表面与所述第一导线部垂直，所述第一芯片搭载部的第一上表面与所述第三导线部不垂直，以使得对第二晶体管的应力大，减小对第一晶体管的应力，保护第一晶体管。
根据一种具体实施方式，本公开至少一实施例所述的半导体器件还可以 包括芯片搭载部、第一半导体芯片和第二半导体芯片；在所述第一半导体芯片上形成有第一晶体管，在所述第二半导体芯片上形成有第二晶体管；
所述芯片搭载部的至少一部分、所述第一半导体芯片和所述第二半导体芯片被同一所述封固体封固；所述第一半导体芯片具有第一表面和与所述第一表面为相反侧的第一背面，所述第二半导体芯片具有第二表面和与所述第二表面为相反侧的第二背面；
在所述第一半导体芯片的第一表面上形成有第一控制极焊盘和第一焊盘，所述第一背面与所述第一晶体管的第一端子电连接；所述第一控制极焊盘分别与所述第一晶体管的控制极和所述第一控制极引脚电连接，所述第一焊盘与所述第一晶体管的第二端子电连接；
在所述第二半导体芯片的第二表面上形成有第二控制极焊盘、至少一个第二焊盘和至少一个第三焊盘，所述第二控制极焊盘分别与所述第二晶体管的控制极和所述第二控制极引脚电连接，所述第二晶体管的第二电极与所述第二焊盘电连接，所述第二晶体管的第一电极与所述第三焊盘电连接；
所述芯片搭载部具有上表面，所述第一半导体芯片搭载于所述芯片搭载部的上表面上，所述第一半导体芯片的第一背面朝向所述上表面；所述第一半导体芯片的第一背面与所述芯片搭载部电连接；
所述第二半导体芯片搭载于所述芯片搭载部的上表面上，所述第二半导体芯片的第二背面朝向所述上表面。
在具体实施时，本公开至少一实施例所述的半导体器件还可以包括芯片搭载部、第一半导体芯片和第二半导体芯片；在所述第一半导体芯片上形成有第一晶体管，在所述第二半导体芯片上形成有第二晶体管；所述芯片搭载部的至少一部分、所述第一半导体芯片和所述第二半导体芯片被同一所述封固体封固；
在所述第一半导体芯片的第一表面上形成有第一控制极焊盘和第一焊盘，所述第一背面与所述第一晶体管的第一端子电连接，所述第一半导体芯片的第一背面与所述芯片搭载部电连接，以使得所述第一晶体管的第一端子与所述芯片搭载部电连接；在所述第二半导体芯片的第二表面上形成有第二控制极焊盘、至少一个第二焊盘和至少一个第三焊盘。
可选的，所述第三焊盘通过导线与所述第一控制极引脚电连接，以使得所述第二晶体管的第一电极与所述第一晶体管的控制极电连接；所述第二焊盘与所述第一焊盘电连接，以使得所述第二晶体管的第二电极与所述第一晶体管的第二端子电连接。其中，所述第三焊盘与所述第一控制极引脚之间的导线短。
可选的，所述第三焊盘通过导线与所述第一控制极焊盘电连接，，以使得所述第二晶体管的第一电极与所述第一晶体管的控制极电连接；所述第二焊盘与所述第一焊盘电连接，以使得所述第二晶体管的第二电极与所述第一晶体管的第二端子电连接。其中，所述第三焊盘与所述第一控制极焊盘之间的导线短。
在本公开至少一实施例中，所述的半导体器件还可以包括第一电极引脚和第二电极引脚；
所述第一电极引脚与所述第一焊盘电连接，以使得所述第一电极引脚与所述第一晶体管的第二端子电连接；
所述第二电极引脚与所述芯片搭载部电连接，以使得所述第二电极引脚与所述第一晶体管的第一端子电连接。
在具体实施时，所述第一半导体芯片设置于所述第二半导体芯片的第一侧边，所述第一晶体管的导通电流大于所述第二晶体管的导通电流。
可选的，所述第一晶体管为以SiC为材料的MOSFET，所述第二晶体管为以GaN为材料的场效应晶体管。
在本公开至少一实施例中，第一侧边可以为左侧边，或者，所述第一侧边可以为右侧边；当所述第一晶体管为以SiC为材料的MOSFET，所述第二晶体管为以GaN为材料的场效应晶体管时，第一晶体管的导通电流大于所述第二晶体管的导通电流。
可选的，所述第一半导体芯片与所述芯片搭载部之间的第四距离，大于所述第一半导体芯片与所述芯片搭载部之间的第三距离。
在实际操作时，在所述第二半导体芯片与所述芯片搭载部之间可以设置有隔离层，以将所述第二半导体芯片垫高，使得所述第二半导体芯片高于所述第一半导体芯片；所述隔离层通过绝缘粘结材料分别与所述芯片搭载部和 所述第二半导体芯片粘结。例如，所述隔离层可以由AL2O3制成，但不以此为限。
在具体实施时，所述第二半导体芯片比所述第一半导体芯片高，这样在制作所述第二晶体管的第二电极通过导线与所述第一晶体管的第二端子之间的导线时，可以使得对第二晶体管的应力大，减小对第一晶体管的应力，保护第一晶体管。
在具体实施时，所述第二晶体管的第二电极通过导线与所述第一晶体管的第二端子电连接；
所述导线包括第一导线部、第二导线部和第三导线部；
所述第一导线部的第一端与所述第二晶体管的第二电极电连接，所述第一导线部的第二端与所述第二导线部的第一端电连接，所述第二导线部的第二端与所述第三导线部的第一端电连接，所述第三导线部的第二端与所述第一晶体管的第二端子电连接；
所述第二半导体芯片的第二表面与所述第一导线部垂直，所述第一半导体芯片的第一表面与所述第三导线部不垂直以使得对第二晶体管的应力大，减小对第一晶体管的应力，保护第一晶体管。
如图9所示，本公开至少一实施例所述的半导体器件可以包括第一晶体管、第二晶体管、封固体F0、芯片搭载部P0、第一半导体芯片C1、第二半导体芯片C2、第一控制极引脚J01、第二控制极引脚J02、第一电极引脚J1和第二电极引脚J2；在所述第一半导体芯片C1上形成有第一晶体管，在所述第二半导体芯片C2上形成有第二晶体管；
所述芯片搭载部P0、所述第一半导体芯片C1和所述第二半导体芯片C2被同一所述封固体封固；所述第一半导体芯片C1具有第一表面和与所述第一表面为相反侧的第一背面，所述第二半导体芯片C2具有第二表面和与所述第二表面为相反侧的第二背面；
在所述第一半导体芯片C1的第一表面上形成有第一控制极焊盘H01和第一焊盘H1，所述第一背面与所述第一晶体管的第一端子电连接；所述第一控制极焊盘H01分别与所述第一晶体管的控制极和所述第一控制极引脚J01电连接，所述第一焊盘H1与所述第一晶体管的第二端子电连接；
在所述第二半导体芯片的第二表面上形成有第二控制极焊盘H02、第一个第二焊盘H12、第二个第二焊盘H22、第一个第三焊盘H13和第二个第三焊盘H23，所述第二控制极焊盘H02分别与所述第二晶体管的控制极和所述第二控制极引脚J02电连接，所述第二晶体管的第二电极分别与H12和H22电连接，所述第二晶体管的第一电极分别与H13和H23电连接；
H12与H22之间电连接，H13与H23电连接；
所述芯片搭载部P0具有上表面，所述第一半导体芯片C1搭载于所述芯片搭载部P0的上表面上，所述第一半导体芯片C1的第一背面朝向所述上表面；所述第一半导体芯片C1的第一背面与所述芯片搭载部P0电连接，以使得所述第一晶体管的第一端子与所述芯片搭载部P0电连接；
所述第二半导体芯片C2搭载于所述芯片搭载部P0的上表面上，所述第二半导体芯片C2的第二背面朝向所述上表面；
所述第一电极引脚J1与所述第一焊盘H1电连接，以使得所述第一电极引脚J1与所述第一晶体管的第二端子电连接；
所述第二电极引脚J2与所述芯片搭载部P0电连接，以使得所述第二电极引脚J2与所述第一晶体管的第一端子电连接；
H13通过第七导线L7与所述第一控制极引脚J01电连接，以使得所述第二晶体管的第一电极与所述第一晶体管的控制极电连接；H12与所述第一焊盘H1电连接，以使得所述第二晶体管的第二电极与所述第一晶体管的第二端子电连接。其中，H13与所述第一控制极引脚J01之间的第七导线L7短。
在图9所示的至少一实施例中，所述第一晶体管的控制极为栅极，所述第一晶体管的第一端子为漏电极，所述第一晶体管的第二端子为源电极，所述第二晶体管的控制极为栅极，所述第二晶体管的第一电极为漏电极，所述第二晶体管的第二电极为源电极，但不以此为限。
在图9所示的至少一实施例中，所述芯片搭载部P0以与所述第二电极引脚J2连结的方式一体的形成，以使得所述芯片搭载部P0与所述第二电极引脚J2电连接。
在图9所示的至少一实施例中，J02、J01、J2和J1从左至右依次排布，J02、J01、J2和J1相互绝缘；H12和H22从右至左依次排列，H13和H23 从右至左依次排列，H13靠近J01，以方便H13与J01电连接。
在图9所示的至少一实施例中，所述第一晶体管为以SiC为材料的MOSFET，所述第二晶体管为以GaN为材料的场效应晶体管；所述第一半导体芯片C1设置于所述第二半导体芯片C2右侧，但不以此为限。在实际操作时，C1也可以设置于C2左侧。
在图9所示的至少一实施例中，在所述芯片搭载部P0的上表面上，例如，经由银焊剂或锡焊构成的导电性粘结材料而搭载有第一半导体芯片C1；在所述第一半导体芯片C1上，形成有以SiC为材料的MOSFET；所述第一半导体芯片C1的第一背面成为漏电极，在所述第一半导体芯片C1的第一表面形成有第一控制极焊盘H01和第一焊盘H1；也即，所述第一晶体管的漏电极形成于所述第一半导体芯片C1的第一背面，与所述第一晶体管的栅极电连接的第一控制极焊盘H01，以及，与所述第一晶体管的源电极电连接的第一焊盘H1设置于所述第一半导体芯片C2的第一表面。
在图9所示的至少一实施例中，在所述芯片搭载部P0的上表面上，设置有所述第二半导体芯片C2所述第二半导体芯片C2的第二背面朝向所述上表面；所述第二半导体芯片C2的第二背面与所述芯片搭载部P0之间绝缘。
在图9所示的至少一实施例中，所述芯片搭载部P0、所述第一半导体芯片C1、所述第二半导体芯片C2、J02的一部分、J01的一部分、J2的一部分和J1的一部分被所述封固体F0封固。
在图9中，在J02的下方绘制有(G2)，指的是J02可以与第二晶体管的栅极G2电连接；在J01的下方绘制有(G1)，指的是J01可以与第一晶体管的栅极G1电连接；在J2的下方绘制有(D)，指的是J2可以与第一晶体管的漏电极D电连接；在J1的下方绘制有(S)，指的是J1可以与第一晶体管的源电极S电连接。
在具体实施时，所述第一个第三焊盘H13也可以通过导线与所述第一控制极焊盘H01电连接，以使得所述第二晶体管的第一电极与所述第一晶体管的控制极电连接；其中，所述第一个第三焊盘H13与所述第一控制极焊盘H01之间的导线短。
本公开至少一实施例半导体器件包括封固体、第一晶体管和电容，其中， 所述第一晶体管包括控制极、第一端子和第二端子；所述电容包括第一电容电极和第二电容电极；
所述第一晶体管用于在其控制极的电位的控制下，使得电流能够从所述第一端子流向所述第二端子；所述第一电容电极与所述第一晶体管的控制极电连接，所述第二电容电极与所述第一晶体管的第二端子电连接；
所述第一晶体管和所述电容都被同一所述封固体封固，所述第一晶体管的控制极与第一控制极引脚电连接。
在本公开至少一实施例中，所述第一晶体管的控制极与所述第一控制极引脚之间可以通过绑定线电连接；所述绑定线为导线。
本公开至少一实施例所述的半导体器件将第一晶体管和电容(所述电容用于控制所述第一晶体管的控制极的电位)都被同一所述封固体封固，以缩短所述电容和所述第一晶体管的控制极之间的距离，以保证较好的钳位效果，并简化布线。
在具体实施时，所述第一控制极引脚至少部分设置于所述封固体外部，但不以此为限。
在具体实施时，所述封固体可以由树脂制成，但不以此为限。
可选的，所述第一晶体管为n型晶体管，所述第一端子为第一电极，所述第一电极为漏电极，所述第二端子为第二电极，所述第二电极为源电极；或者，
所述第一晶体管为p型晶体管，所述第一端子为第一电极，所述第一端子为源电极，所述第二端子为第二电极，所述第二端子为漏电极。
在具体实施时，本公开至少一实施例所述的半导体器件还包括芯片搭载部、第一半导体芯片、第二半导体芯片和第一控制极引脚；在所述第一半导体芯片上形成有第一晶体管；在所述第二半导体芯片上形成有所述电容；
所述芯片搭载部的至少一部分、所述第一半导体芯片和所述第二半导体芯片被同一所述封固体封固；
所述第一半导体芯片具有第一表面和与所述第一表面为相反侧的第一背面；所述第二半导体芯片具有第二表面和与所述第二表面为相反侧的第二背面；
在所述第一半导体芯片的第一表面上形成有第一控制极焊盘和第一焊盘，所述第一背面与所述第一晶体管的第一端子电连接；所述第一控制极焊盘分别与所述第一晶体管的控制极和第一控制极引脚电连接，所述第一焊盘与所述第一晶体管的第二端子电连接；
在所述第二半导体芯片的第二表面上形成有第一电极焊盘和第二电极焊盘；所述第一电极焊盘与所述第一电容电极电连接，所述第二电极焊盘与所述第二电容电极电连接；
所述芯片搭载部具有上表面，所述第一半导体芯片搭载于所述芯片搭载部的上表面上，所述第一半导体芯片的第一背面朝向所述上表面；所述第一半导体芯片的第一背面与所述芯片搭载部电连接；
所述第二半导体芯片搭载于所述芯片搭载部的上表面上，所述第二半导体芯片的第二背面朝向所述上表面；
所述第一电极焊盘与所述第一控制极引脚或所述第一控制极焊盘电连接，所述第二电极焊盘与所述第一焊盘电连接，以使得所述第二电容电极与所述第一晶体管的第二端子电连接。
在本公开至少一实施例中，所述半导体器件还包括芯片搭载部、第一半导体芯片、第二半导体芯片和第一控制极引脚；在所述第一半导体芯片上形成有第一晶体管；在所述第二半导体芯片上形成有所述电容；所述芯片搭载部的至少一部分、所述第一半导体芯片和所述第二半导体芯片被同一所述封固体封固；所述第一晶体管可以为以SiC为材料的MOSFET，并所述第一电极焊盘与所述第一控制极引脚或所述第一控制极焊盘电连接，其中，所述第一电极焊盘与所述第一控制极引脚或所述第一控制极焊盘之间的导线短。
可选的，所述的半导体器件还可以包括第一电极引脚和第二电极引脚；
所述第一电极引脚与所述第一焊盘电连接，所述第二电极引脚与所述芯片搭载部电连接。
在具体实施时，所述第一控制极引脚至少部分设置于所述封固体外部，所述第一电极引脚至少部分设置于所述封固体外部，所述第二电极引脚至少部分设置于所述封固体外部。
如图10所示，本公开至少一实施例所述的半导体器件包括第一晶体管 M1和电容C0；所述电容C0包括第一电容电极和第二电容电极；
所述第一晶体管M1用于在其栅极G1的电位的控制下，使得电流可以由所述第一晶体管M1的漏电极D流向所述第一晶体管M1的源电极S；
所述第一电容电极与所述第一晶体管M1的栅极G1电连接，所述第二电容电极与所述第一晶体管M1的源电极S电连接。
在图10所示的半导体器件的至少一实施例中，M1为n型MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor,金属-氧化物-半导体场效应晶体管)，但不以此为限。
如图11所示，本公开至少一实施例所述的半导体器件可以包括第一晶体管、第二晶体管、封固体F0、芯片搭载部P0、第一半导体芯片C1、第二半导体芯片C2、第一控制极引脚J01、第一电极引脚J1和第二电极引脚J2；在所述第一半导体芯片C1上形成有第一晶体管；在所述第二半导体芯片C2上形成有所述电容；
所述芯片搭载部P0、所述第一半导体芯片C1和所述第二半导体芯片C2被同一所述封固体F0封固；
所述第一半导体芯片C1具有第一表面和与所述第一表面为相反侧的第一背面；所述第二半导体芯片C2具有第二表面和与所述第二表面为相反侧的第二背面；
在所述第一半导体芯片C1的第一表面上形成有第一控制极焊盘H01和第一焊盘H1，所述第一背面与所述第一晶体管的第一端子电连接；所述第一控制极焊盘H01分别与所述第一晶体管的控制极和第一控制极引脚J01电连接，所述第一焊盘H1与所述第一晶体管的第二端子电连接；
在所述第二半导体芯片C2的第二表面上形成有第一电极焊盘H41和第二电极焊盘H42；所述第一电极焊盘H41与所述第一电容电极电连接，所述第二电极焊盘H42与所述第二电容电极电连接；
所述芯片搭载部P0具有上表面，所述第一半导体芯片C1搭载于所述芯片搭载部P0的上表面上，所述第一半导体芯片C1的第一背面朝向所述上表面；所述第一半导体芯片C1的第一背面与所述芯片搭载部P0电连接；
所述第二半导体芯片C2搭载于所述芯片搭载部的上表面上，所述第二半 导体芯片C2的第二背面朝向所述上表面；
所述第二电极焊盘H41与第一焊盘H1电连接；
所述第一电极焊盘H41通过第八导线L8与所述第一控制极引脚J01电连接，以使得所述第一电容电极与所述第一晶体管的控制极电连接；所述第二电极焊盘42与所述第一焊盘H1电连接，以使得所述第二电容电极与所述第一晶体管的第二端子电连接；其中，所述第一电极焊盘H41与所述第一控制极引脚J01之间的第八导线L8短；
所述第一电极引脚J1与所述第一焊盘H1电连接，以使得所述第一电极引脚J1与所述第一晶体管的第二端子电连接；所述第二电极引脚J2与所述芯片搭载部P0电连接，以使得所述第二电极引脚J2与所述第一晶体管的第一端子电连接。
在图11所示的至少一实施例中，所述第一晶体管为n型晶体管，所述第一端子为第一电极，所述第一电极为漏电极，所述第二端子为第二电极，所述第二电极为源电极。
在图11中，在J01的下方绘制有(G1)，指的是J01可以与第一晶体管的栅极G1电连接；在J2的下方绘制有(D)，指的是J2可以与第一晶体管的漏电极D电连接；在J1的下方绘制有(S)，指的是J1可以与第一晶体管的源电极S电连接。
在图11所示的至少一实施例中，第一晶体管为以SiC为材料的MOSFET；所述第一半导体芯片C1设置于所述第二半导体芯片C2右侧，但不以此为限。在实际操作时，C1也可以设置于C2左侧。
在图11所示的至少一实施例中，在SiC MOSFET晶圆制作时，利用很小的面积，设置电容，以将电容集成于SiC MOSFET内部。
在图11所示的至少一实施例中，所述芯片搭载部P0以与所述第二电极引脚J2连结的方式一体的形成，所述芯片搭载部P0与所述第二电极引脚J2电连接；以分离并隔着所述第二电极引脚J2的方式配置第一控制电极引脚J01和第一电极引脚J1。具体的，如图10所示，在J2的右侧配置有J1，在J2的左侧配置有J01，J01、J2和J1相互绝缘。
在图11所示的至少一实施例中，在所述芯片搭载部P0上，例如，经由 银焊剂或锡焊构成的导电性粘结材料而搭载有第一半导体芯片C1；在所述第一半导体芯片C1上，形成有以SiC为材料的MOSFET；所述第一半导体芯片C1的第一背面成为漏电极，在所述第一半导体芯片C1的第一表面形成有第一控制极焊盘H01和第一焊盘H1；也即，所述第一晶体管的漏电极形成于所述第一半导体芯片C1的第一背面，与所述第一晶体管的栅极电连接的第一控制极焊盘H01，以及，与所述第一晶体管的源电极电连接的第一焊盘H1设置于所述第一半导体芯片C1的第一表面。
在具体实施时，所述第二半导体芯片C2的第二背面朝向所述芯片搭载部P0的上表面，所述第二半导体芯片C2的第二背面与所述芯片搭载部P0绝缘，但不以此为限。
在图11所示的至少一实施例中，在所述芯片搭载部P0上设置有第二半导体芯片C2，在所述第二半导体芯片C2上形成有所述电容；在所述第二半导体芯片C2的第二表面上形成有第一电极焊盘H41和第二电极焊盘H42。
在图11所示的至少一实施例中，所述芯片搭载部P0、所述第一半导体芯片C1、所述第二半导体芯片C2、J01的一部分、J2的一部分和J1的一部分被所述封固体F0封固。
在本公开至少一实施例中，开关系统可以包括栅极驱动器和上述的半导体器件，栅极驱动器为所述半导体器件中的第一晶体管的控制极提供栅极驱动信号，以控制第一晶体管导通或关断。所述第一晶体管的第一极可以与电源端电连接，所述第一晶体管的第二极可以与负荷电连接。当所述第一晶体管导通时，所述电源端为所述负荷提供电源电压。
如图12所示，所述开关系统的至少一实施例可以包括栅极驱动器120和本公开如图1所示的半导体器件的至少一实施例；
所述栅极驱动器120通过电阻R与M1的栅极G1电连接，M1的漏电极D与电源电压端E1电连接，M1的源电极S与负荷121电连接。
如图12所示的开关系统的至少一实施例在工作时，在需要导通E1与负荷121之间的连接时，所述栅极驱动器120向M1的栅极G1提供栅极驱动信号，以控制M1导通，从而控制电源电压端E1与负荷121之间连通。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通 技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (33)

  1. 一种半导体器件，包括封固体、第一晶体管和第二晶体管，其中，所述第一晶体管包括控制极、第一端子和第二端子；
    所述第一晶体管用于在其控制极的电位的控制下，使得电流能够从所述第一端子流向所述第二端子；所述第二晶体管的第一电极与所述第一晶体管的控制极电连接，所述第二晶体管的第二电极与所述第一晶体管的第二端子电连接；
    所述第一晶体管和所述第二晶体管被同一所述封固体封固，所述第一晶体管的控制极与第一控制极引脚电连接，所述第二晶体管的控制极与第二控制极引脚电连接。
  2. 如权利要求1所述的半导体器件，其中，所述第一晶体管为n型晶体管，所述第一端子为第一电极，所述第一电极为漏电极，所述第二端子为第二电极，所述第二电极为源电极；或者，
    所述第一晶体管为p型晶体管，所述第一端子为第一电极，所述第一端子为源电极，所述第二端子为第二电极，所述第二端子为漏电极。
  3. 如权利要求2所述的半导体器件，其中，还包括第一芯片搭载部、第二芯片搭载部、第一半导体芯片、第二半导体芯片、第一控制极引脚和第二控制极引脚；所述第一芯片搭载部与所述第二芯片搭载部相互绝缘；在所述第一半导体芯片上形成有第一晶体管，在所述第二半导体芯片上形成有第二晶体管；
    所述第一芯片搭载部的至少一部分、所述第二芯片搭载部的至少一部分、所述第一半导体芯片和所述第二半导体芯片被同一所述封固体封固；
    所述第一半导体芯片具有第一表面和与所述第一表面为相反侧的第一背面，所述第二半导体芯片具有第二表面和与所述第二表面为相反侧的第二背面；
    在所述第一半导体芯片的第一表面上形成有第一控制极焊盘和第一焊盘，所述第一背面与所述第一晶体管的第一端子电连接；所述第一控制极焊盘分别与所述第一晶体管的控制极和第一控制极引脚电连接，所述第一焊盘与所 述第一晶体管的第二端子电连接；
    在所述第二半导体芯片的第一表面上形成有第二控制极焊盘和第二焊盘，所述第二背面与所述第二晶体管的第一电极电连接；所述第二控制极焊盘分别与所述第二晶体管的控制极和第二控制极引脚电连接，所述第二晶体管的第二电极与所述第二焊盘电连接；
    所述第一芯片搭载部具有第一上表面，所述第一半导体芯片搭载于所述第一芯片搭载部的第一上表面上，所述第一半导体芯片的第一背面朝向所述第一上表面；所述第一半导体芯片的第一背面与所述第一芯片搭载部电连接；
    所述第二芯片搭载部具有第二上表面，所述第二半导体芯片搭载于所述第二芯片搭载部的第二上表面上，所述第二半导体芯片的第二背面朝向所述第二上表面；所述第二半导体芯片的第二背面与所述第二芯片搭载部电连接。
  4. 如权利要求3所述的半导体器件，其中，所述第二芯片搭载部通过导线与所述第一控制极焊盘电连接；所述第二焊盘与所述第一焊盘电连接。
  5. 如权利要求3所述的半导体器件，其中，所述第二芯片搭载部通过导线与所述第一控制极引脚电连接，所述第二焊盘与所述第一焊盘电连接。
  6. 如权利要求3至5中任一权利要求所述的半导体器件，其中，还包括第一电极引脚和第二电极引脚；
    所述第一电极引脚与所述第一焊盘电连接，所述第二电极引脚与所述第一芯片搭载部电连接。
  7. 如权利要求3至5中任一权利要求所述的半导体器件，其中，所述第一芯片搭载部设置于所述第二芯片搭载部的第一侧边，所述第一晶体管的导通电流大于所述第二晶体管的导通电流，所述第一晶体管的导通速度大于所述第二晶体管的导通速度。
  8. 如权利要求2所述的半导体器件，其中，还包括第一芯片搭载部、第二芯片搭载部、第一半导体芯片、第二半导体芯片、第一控制极引脚和第二控制极引脚；所述第一芯片搭载部的至少一部分、所述第二芯片搭载部的至少一部分、所述第一半导体芯片和所述第二半导体芯片都被同一所述封固体封固；在所述第一半导体芯片上形成有第一晶体管，在所述第二半导体芯片上形成有第二晶体管；
    所述第一半导体芯片具有第一表面和与所述第一表面为相反侧的第一背面，所述第二半导体芯片具有第二表面和与所述第二表面为相反侧的第二背面；
    在所述第一半导体芯片的第一表面上形成有第一控制极焊盘和第一焊盘，所述第一背面与所述第一晶体管的第一端子电连接；所述第一控制极焊盘分别与所述第一晶体管的控制极和第一控制极引脚电连接，所述第一焊盘与所述第一晶体管的第二端子电连接；
    在所述第二半导体芯片的第一表面上形成有第二控制极焊盘和第二焊盘，所述第二背面与所述第二晶体管的第一电极电连接；所述第二控制极焊盘分别与所述第二晶体管的控制极和第二控制极引脚电连接，所述第二晶体管的第二电极与所述第二焊盘电连接；
    所述第一芯片搭载部具有第一上表面，所述第一半导体芯片搭载于所述第一芯片搭载部的第一上表面上，所述第一半导体芯片的第一背面朝向所述第一上表面；所述第一半导体芯片的第一背面与所述第一芯片搭载部电连接；
    所述第二芯片搭载部具有第二上表面和与所述第二上表面为相反侧的第二下表面，所述第二芯片搭载部搭载于所述第一芯片搭载部的第一上表面上，所述第二芯片搭载部与所述第一芯片搭载部之间绝缘，所述第二芯片搭载部的第二下表面朝向所述第一上表面；
    所述第二半导体芯片搭载于所述第二芯片搭载部的第二上表面上，所述第二半导体芯片的第二背面朝向所述第二上表面；所述第二半导体芯片的第二背面与所述第二芯片搭载部电连接。
  9. 如权利要求8所述的半导体器件，其中，所述第二芯片搭载部通过导线与所述第一控制极焊盘电连接；所述第二焊盘与所述第一焊盘电连接。
  10. 如权利要求8所述的半导体器件，其中，所述第二芯片搭载部通过导线与所述第一控制极引脚电连接，所述第二焊盘与所述第一焊盘电连接。
  11. 如权利要求8至10中任一权利要求所述的半导体器件，其中，还包括第一电极引脚和第二电极引脚；
    所述第一电极引脚与所述第一焊盘电连接，所述第二电极引脚与所述第一芯片搭载部电连接。
  12. 如权利要求8至10中任一权利要求所述的半导体器件，其中，所述第一半导体芯片设置于所述第二半导体芯片的第一侧边，所述第一晶体管的导通电流大于所述第二晶体管的导通电流，所述第一晶体管的导通速度大于所述第二晶体管的导通速度。
  13. 如权利要求3、4、5、8、9或10所述的半导体器件，其中，所述第一晶体管为以SiC为材料的MOSFET，所述第二晶体管为以Si为材料的MOSFET。
  14. 如权利要求2所述的半导体器件，其中，还包括第一芯片搭载部、第二芯片搭载部、第一半导体芯片、第二半导体芯片、第一控制极引脚和第二控制极引脚；所述第一芯片搭载部与所述第二芯片搭载部相互绝缘；在所述第一半导体芯片上形成有第一晶体管，在所述第二半导体芯片上形成有第二晶体管；
    所述第一芯片搭载部的至少一部分、所述第二芯片搭载部的至少一部分、所述第一半导体芯片和所述第二半导体芯片被同一所述封固体封固；
    所述第一半导体芯片具有第一表面和与所述第一表面为相反侧的第一背面，所述第二半导体芯片具有第二表面和与所述第二表面为相反侧的第二背面；
    在所述第一半导体芯片的第一表面上形成有第一控制极焊盘、至少一个第一焊盘和至少一个第二焊盘，所述第一控制极焊盘分别与所述第一晶体管的控制极和第一控制极引脚电连接，所述第一焊盘与所述第一晶体管的第二端子电连接，所述第二焊盘与所述第一晶体管的第一端子电连接；
    在所述第二半导体芯片的第一表面上形成有第二控制极焊盘和第三焊盘，所述第二背面与所述第二晶体管的第一电极电连接；所述第二控制极焊盘分别与所述第二晶体管的控制极和第二控制极引脚电连接，所述第二晶体管的第二电极与所述第三焊盘电连接；
    所述第一芯片搭载部具有第一上表面，所述第一半导体芯片搭载于所述第一芯片搭载部的第一上表面上，所述第一半导体芯片的第一背面朝向所述第一上表面；
    所述第二芯片搭载部具有第二上表面，所述第二半导体芯片搭载于所述 第二芯片搭载部的第二上表面上，所述第二半导体芯片的第二背面朝向所述第二上表面；所述第二半导体芯片的第二背面与所述第二芯片搭载部电连接。
  15. 如权利要求14所述的半导体器件，其中，所述第二芯片搭载部通过导线与所述第一控制极焊盘电连接；所述第三焊盘与所述第一焊盘电连接。
  16. 如权利要求14所述的半导体器件，其中，所述第二芯片搭载部通过导线与所述第一控制极引脚电连接，所述第三焊盘与所述第一焊盘电连接。
  17. 如权利要求14至16中任一权利要求所述的半导体器件，其中，还包括第一电极引脚和第二电极引脚；
    所述第一电极引脚与所述第一焊盘电连接，所述第二电极引脚与所述第二焊盘电连接。
  18. 如权利要求14至16中任一权利要求所述的半导体器件，其中，所述第一芯片搭载部设置于所述第二芯片搭载部的第一侧边，所述第一晶体管的导通电流大于所述第二晶体管的导通电流，所述第一晶体管的导通速度大于所述第二晶体管的导通速度。
  19. 如权利要求14至16中任一权利要求所述的半导体器件，其中，所述第一晶体管为以GaN为材料的场效应晶体管，所述第二晶体管为以Si为材料的MOSFET。
  20. 如权利要求3至19中任一权利要求所述的半导体器件，其中，所述第一芯片搭载部和所述第二芯片搭载部都设置于同一基板上；
    所述第二芯片搭载部与所述基板之间的第二距离，大于所述第一芯片搭载部与所述基板之间的第一距离。
  21. 如权利要求20所述的半导体器件，其中，所述第二晶体管的第二电极通过导线与所述第一晶体管的第二端子电连接；
    所述导线包括第一导线部、第二导线部和第三导线部；
    所述第一导线部的第一端与所述第二晶体管的第二电极电连接，所述第一导线部的第二端与所述第二导线部的第一端电连接，所述第二导线部的第二端与所述第三导线部的第一端电连接，所述第三导线部的第二端与所述第一晶体管的第二端子电连接；
    所述第二芯片搭载部的第二上表面与所述第一导线部垂直；
    所述第一芯片搭载部的第一上表面与所述第三导线部不垂直。
  22. 如权利要求2所述的半导体器件，其中，还包括芯片搭载部、第一半导体芯片、第二半导体芯片、第一控制极引脚和第二控制极引脚；在所述第一半导体芯片上形成有第一晶体管，在所述第二半导体芯片上形成有第二晶体管；
    所述芯片搭载部的至少一部分、所述第一半导体芯片和所述第二半导体芯片被同一所述封固体封固；所述第一半导体芯片具有第一表面和与所述第一表面为相反侧的第一背面，所述第二半导体芯片具有第二表面和与所述第二表面为相反侧的第二背面；
    在所述第一半导体芯片的第一表面上形成有第一控制极焊盘和第一焊盘，所述第一背面与所述第一晶体管的第一端子电连接；所述第一控制极焊盘分别与所述第一晶体管的控制极和第一控制极引脚电连接，所述第一焊盘与所述第一晶体管的第二端子电连接；
    在所述第二半导体芯片的第二表面上形成有第二控制极焊盘、至少一个第二焊盘和至少一个第三焊盘，所述第二控制极焊盘分别与所述第二晶体管的控制极和第二控制极引脚电连接，所述第二晶体管的第二电极与所述第二焊盘电连接，所述第二晶体管的第一电极与所述第三焊盘电连接；
    所述芯片搭载部具有上表面，所述第一半导体芯片搭载于所述芯片搭载部的上表面上，所述第一半导体芯片的第一背面朝向所述上表面；所述第一半导体芯片的第一背面与所述芯片搭载部电连接；
    所述第二半导体芯片搭载于所述芯片搭载部的上表面上，所述第二半导体芯片的第二背面朝向所述上表面。
  23. 如权利要求22所述的半导体器件，其中，所述第三焊盘通过导线与所述第一控制极引脚电连接，所述第二焊盘与所述第一焊盘电连接。
  24. 如权利要求22所述的半导体器件，其中，所述第三焊盘通过导线与所述第一控制极焊盘电连接，所述第二焊盘与所述第一焊盘电连接。
  25. 如权利要求22至24中任一权利要求所述的半导体器件，其中，还包括第一电极引脚和第二电极引脚；
    所述第一电极引脚与所述第一焊盘电连接，所述第二电极引脚与所述芯 片搭载部电连接。
  26. 如权利要求22至24中任一权利要求所述的半导体器件，其中，所述第一半导体芯片设置于所述第二半导体芯片的第一侧边，所述第一晶体管的导通电流大于所述第二晶体管的导通电流。
  27. 如权利要求22至24中任一权利要求所述的半导体器件，其中，所述第一晶体管为以SiC为材料的MOSFET，所述第二晶体管为以GaN为材料的场效应晶体管。
  28. 如权利要求22至27中任一权利要求所述的半导体器件，其中，
    所述第一半导体芯片与所述芯片搭载部之间的第四距离，大于所述第一半导体芯片与所述芯片搭载部之间的第三距离。
  29. 如权利要求28所述的半导体器件，其中，所述第二晶体管的第二电极通过导线与所述第一晶体管的第二端子电连接；
    所述导线包括第一导线部、第二导线部和第三导线部；
    所述第一导线部的第一端与所述第二晶体管的第二电极电连接，所述第一导线部的第二端与所述第二导线部的第一端电连接，所述第二导线部的第二端与所述第三导线部的第一端电连接，所述第三导线部的第二端与所述第一晶体管的第二端子电连接；
    所述第二半导体芯片的第二表面与所述第一导线部垂直；
    所述第一半导体芯片的第一表面与所述第三导线部不垂直。
  30. 一种半导体器件，其中，包括封固体、第一晶体管和电容，其中，所述第一晶体管包括控制极、第一端子和第二端子；所述电容包括第一电容电极和第二电容电极；
    所述第一晶体管用于在其控制极的电位的控制下，使得电流能够从所述第一端子流向所述第二端子；所述第一电容电极与所述第一晶体管的控制极电连接，所述第二电容电极与所述第一晶体管的第二端子电连接；
    所述第一晶体管和所述电容都被同一所述封固体封固，所述第一晶体管的控制极与第一控制极引脚电连接。
  31. 如权利要求30所述的半导体器件，其中，所述第一晶体管为n型晶体管，所述第一端子为第一电极，所述第一电极为漏电极，所述第二端子为第二电极，所述第二电极为源电极；或者，
    所述第一晶体管为p型晶体管，所述第一端子为第一电极，所述第一端子为源电极，所述第二端子为第二电极，所述第二端子为漏电极。
  32. 如权利要求31所述的半导体器件，其中，还包括芯片搭载部、第一半导体芯片、第二半导体芯片和第一控制极引脚；在所述第一半导体芯片上形成有第一晶体管；在所述第二半导体芯片上形成有所述电容；
    所述芯片搭载部的至少一部分、所述第一半导体芯片和所述第二半导体芯片被同一所述封固体封固；
    所述第一半导体芯片具有第一表面和与所述第一表面为相反侧的第一背面；所述第二半导体芯片具有第二表面和与所述第二表面为相反侧的第二背面；
    在所述第一半导体芯片的第一表面上形成有第一控制极焊盘和第一焊盘，所述第一背面与所述第一晶体管的第一端子电连接；所述第一控制极焊盘分别与所述第一晶体管的控制极和第一控制极引脚电连接，所述第一焊盘与所述第一晶体管的第二端子电连接；
    在所述第二半导体芯片的第二表面上形成有第一电极焊盘和第二电极焊盘；所述第一电极焊盘与所述第一电容电极电连接，所述第二电极焊盘与所述第二电容电极电连接；
    所述芯片搭载部具有上表面，所述第一半导体芯片搭载于所述芯片搭载部的上表面上，所述第一半导体芯片的第一背面朝向所述上表面；所述第一半导体芯片的第一背面与所述芯片搭载部电连接；
    所述第二半导体芯片搭载于所述芯片搭载部的上表面上，所述第二半导体芯片的第二背面朝向所述上表面；
    所述第一电极焊盘与所述第一控制极引脚或所述第一控制极焊盘电连接，所述第二电极焊盘与所述第一焊盘电连接。
  33. 如权利要求32所述的半导体器件，其中，还包括第一电极引脚和第二电极引脚；
    所述第一电极引脚与所述第一焊盘电连接，所述第二电极引脚与所述芯片搭载部电连接。
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US20150115313A1 (en) * 2013-10-31 2015-04-30 Infineon Technologies Austria Ag Semiconductor Device Package
CN104600062A (zh) * 2013-10-31 2015-05-06 英飞凌科技奥地利有限公司 半导体器件封装

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