CN103545283A - 具有多个引线框架的半导体封装及其形成方法 - Google Patents

具有多个引线框架的半导体封装及其形成方法 Download PDF

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Publication number
CN103545283A
CN103545283A CN201310286049.3A CN201310286049A CN103545283A CN 103545283 A CN103545283 A CN 103545283A CN 201310286049 A CN201310286049 A CN 201310286049A CN 103545283 A CN103545283 A CN 103545283A
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lead
lead frame
semiconductor chip
tube core
coupled
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CN201310286049.3A
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CN103545283B (zh
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J.霍伊格劳尔
R.奥特雷巴
K.施伊斯
X.施洛伊格
J.施雷德
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明涉及具有多个引线框架的半导体封装及其形成方法。根据本发明的实施例，半导体封装包括具有第一管芯踏板的第一引线框架、和具有第二管芯踏板和多个引线的第二引线框架。第二管芯踏板被部署在第一管芯踏板之上。半导体芯片被部署在第二管芯踏板之上。半导体芯片在面向第二引线框架的第一侧上具有多个接触区域。多个接触区域被电耦合到多个引线。

Description

具有多个引线框架的半导体封装及其形成方法
技术领域
本发明一般地涉及半导体封装，并且更特别地涉及具有多个引线框架的半导体封装及其形成方法。
背景技术
半导体器件在各种电子的和其它的应用中被使用。半导体器件包括，除了别的之外，集成电路或者分立器件，其通过在半导体晶片之上沉积一个或多个类型的材料薄膜来被形成在半导体晶片上的，并且对材料薄膜形成图案来形成集成电路。
半导体器件一般地被封装在陶瓷或者塑料主体内来保护半导体器件使其不受物理损坏或者腐蚀。封装同样地支撑连接半导体器件（也被称作管芯或者芯片）到在封装之外的其它器件需要的电接触点。依赖于半导体器件的类型和被封装的半导体器件的意图的用途，许多不同类型的封装是可用的。诸如封装的尺寸、引脚数等之类的典型的封装特征可以除了别的之外遵从来自电子器件工程联合会（Joint Electron Devices Engineering Council，JEDEC）的开放标准。封装也可以被称作半导体器件装配，或者简单地被称为装配。
封装的一个关注涉及寄生效应的最小化。这是因为由于寄生电阻、寄生电感等等，封装能够显著地更改其中的半导体芯片的性能。
发明内容
根据本发明的实施例，半导体封装包括第一引线框架、和被部署在第一引线框架之上的第二引线框架。第二引线框架具有管芯踏板和多个引线。半导体芯片被部署在第二引线框架之上，半导体芯片耦合到多个引线。
根据本发明的可替换的实施例，半导体封装包括具有第一管芯踏板的第一引线框架、和具有第二管芯踏板和多个引线的第二引线框架。第二管芯踏板被部署在第一管芯踏板之上。半导体芯片被部署在第二管芯踏板之上。半导体芯片在面向第二引线框架的第一侧上具有多个接触区域。多个接触区域被耦合到多个引线。
根据本发明的还有另一个实施例，形成半导体封装的方法包括：提供具有第一管芯踏板的第一引线框架和提供具有第二管芯踏板和多个引线的第二引线框架。第二管芯踏板被附着到第一管芯踏板。半导体芯片被附着到第二管芯踏板。半导体芯片在面向第二引线框架的第一侧具有多个接触区域。多个接触区域被耦合到多个引线。
附图说明
为了本发明及其优点的更全面的理解，现参照连同附图一起采取的下面的描述，在其中：
包括图1A-1D的图1，图示了根据本发明的实施例的包括多个引线框架的半导体封装，其中图1A图示了顶视图，图1B图示了在半导体封装之内但没有灌封的组件的顶视图，其中图1C图示了部分顶视图，而其中图1D图示了横截面视图；
包括图2A-2B的图2，图示了根据可替换的实施例的半导体封装；
包括图3A-3B的图3，图示了根据本发明的实施例的具有增加的漏电距离的半导体封装；
图4图示了根据本发明的实施例的具有洞的第二引线框架；
包括图5A-5B的图5，图示了根据本发明的实施例的具有多个引线和管芯踏板的第一引线框架；
图6图示了根据本发明的实施例的在半导体封装的制造期间的第一引线框架和第二引线框架的顶视图；
包括图7A-7B的图7，图示了根据本发明的实施例的在放置半导体芯片在引线框架之上后正在被制造的半导体封装，其中图7A图示了顶视图，并且其中图7B图示了横截面视图；
包括图8A-8D的图8，图示了根据本发明的实施例的在半导体芯片之上形成互连之后正在制造的半导体封装，其中图8A和8B图示了在可替换的实施例中的顶视图，并且其中图8C和图8D图示了在可替换的实施例中的横截面视图；
包括图9A-9B的图9，图示了根据本发明的实施例的在灌封之后正在制造的半导体封装，其中图9A图示了顶视图，并且其中图9B图示了横截面视图；并且
图10图示了根据本发明的实施例在切单片期间的半导体封装的顶视图。
在不同图中的相应的数字和符号一般指的是部件，除非另外指示。图被绘制以清晰地图示实施例的相关方面，而不必按比例绘制。
具体实施方式
各种实施例的制作和使用在下面被详细讨论。应该领会的是，然而，本发明提供了许多可应用的发明概念，其能够在各种各样的上下文中被具体化。被讨论的实施例只不过是说明制作和使用本发明的一些方式的，而不限制本发明的范围。
功率半导体器件引大量的电流，并且因此对由封装设计引起的寄生损耗非常敏感。寄生组件可以在输入侧（源极侧）或者在输出侧（漏极侧）被引入。这些寄生组价可以由把半导体芯片耦合到封装引线的电连接引起，所述封装引线被用于将封装与外部电路接触。发明人已经发现通过封装被引入的寄生组件对于器件性能的影响是非对称的。特别地，在输入侧的寄生元件比在输出侧的寄生元件对于半导体封装的性能要有害得多。因此本发明的实施例提供不同的封装设计，其有利减少在半导体封装的输入端的寄生效应。
半导体封装的结构的实施例将通过使用图1来被描述。本发明可替换的结构的实施例将通过使用图2-5来被描述。制造半导体封装的方法将通过使用图6-10来被描述。
包括图1A-1D的图1，图示了根据本发明的实施例的包括多个引线框架的半导体封装，其中图1A图示了顶视图，图1B图示了没有灌封的在半导体封装之内的组件的顶视图，其中图1C图示了部分顶视图，而其中图1D图示了横截面视图。
参见图1A和1B，半导体封装包括半导体芯片20被部署在其之上的第一引线框架10。第一引线框架10具有多个引线90，其包括第一引线110、第二引线120、和第三引线130。半导体芯片20被耦合到第一引线框架10。第一引线框架10同样包括半导体芯片20被部署在其之上的管芯踏板105（在图1D中被更好地图示）。管芯踏板105和第二引线120（例如，栅基引线）机械地支撑着半导体芯片20。在图示的实施例中，管芯踏板105是对称的，使得第二引线120（例如，栅基引线）位于中心。然而，在可替换的实施例中，第二引线120可以位于朝向半导体芯片20的一个边缘。
第一引线框架10被部署在第二引线框架30之上。第二引线框架30可以高效地从半导体芯片20移除热量。在各种实施例中，第二引线框架30比第一引线框架10厚。在一个或者多个实施例中，第二引线框架30至少两倍于第一引线框架10的厚度。在一个实施例中，第二引线框架30具有大约2.4mm的厚度，而第一引线框架10具有小于1mm的厚度，而封装的厚度可以是大约4.4mm。在一个实施例中这样的尺寸可以遵从封装标准。然而，在可替换的实施例中，附加的散热装置通过使用在第二引线框架30中的、延伸穿过封装的孔或者洞35，可以被附着到半导体封装上。
在各种实施例中，半导体芯片20可以包括不同类型的包括集成电路或者分立器件的管芯。在一个或者多个实施例中，半导体芯片20可以包括逻辑芯片、存储芯片、模拟芯片、混合信号芯片和其组合，诸如芯片上的系统之类。半导体芯片20可以包括各种类型的有源和无源器件，诸如二极管、晶体管、晶闸管、电容器、电感器、电阻器、光电器件、传感器、微机电系统等等。
在各种实施例中，半导体芯片20可以被形成在硅衬底上。可替换地，在其它实施例中，半导体芯片20可以已经被形成在碳化硅（SiC）上。在一个实施例中，半导体芯片20可以已经至少部分地被形成在氮化镓（GaN）上。
在各种实施例中，半导体芯片20可以包括功率半导体器件，其在一个实施例中可以是分立器件。在一个实施例中，半导体芯片20可以是二端器件，诸如PIN二极管或者肖特基二极管。在一个或者多个实施例中，半导体芯片20可以是三端器件，诸如功率金属绝缘半导体场效应晶体管（MISFET）、结型场效应晶体管（JFET）、双极结型晶体管（BJT）、绝缘栅双极型晶体管（IGBT）或者晶闸管之类。
在一个实施例中，半导体芯片20包括在顶侧和在相对的底侧具有接触区域的垂直半导体器件。如所图示，半导体芯片20的一侧通过多个互连70来被耦合到第一引线框架10。在各种实施例中，多个互连70可以包括带、夹片、线结合和其它合适的导体。例如，在一个实施例中，多个互连70可以是平板。半导体芯片20的相对一侧也被直接耦合到第一引线框架10。因此，在图1A和1B中，在一个实施例中，第一引线110是漏极接触，第二引线120是栅极接触，而第三引线130是源极接触。
如在图1C中图示的，面向第一引线框架10的半导体芯片20的底侧包括第一接触区域21和第二接触区域22。在一个实施例中，第一接触区域21包括半导体器件的源极区域，而第二接触区域22包括半导体器件的控制区域。
如在图1A和1D中进一步图示，第一引线框架10、第二引线框架30和半导体芯片20被部署在灌封80之内。
图1D图示了根据本发明的实施例的半导体封装的横截面视图。如之前所描述的，第一引线框架10被部署在第二引线框架30之上。半导体芯片20被部署在第一引线框架10之上。如在图1D中所图示，半导体芯片20被部署在第一引线框架10的管芯踏板105之上，而第一引线框架10的管芯踏板105被部署在第二引线框架30的管芯附着115之上。第一接触区域21被直接部署在管芯踏板105之上，而且可以通过粘合层（例如，导电膏或者焊接层）来被耦合。管芯踏板105通过灌封80与第二引线120电绝缘。第二引线120通过粘合层（例如焊接层）来被耦合到第二接触区域22。半导体芯片20的第三接触区域23通过如同样在图1A和1B中所图示的多个互连70来被耦合到第一引线110。
有利地，第一引线框架10提供了低的电感路径来连接第一接触区域21（例如源极区域）和多个引线90。相比之下，在常规封装中，源极区域被线接合到引线框架的引线，从而具有较高的电感。此外，第二引线框架30有利地从第一引线框架10和半导体芯片20移除热量。
在一个或者多个实施例中，半导体封装是通孔封装（through hole package），诸如晶体管外形封装之类，诸如TO220之类。在可替换的实施例中，半导体封装是表贴封装（surface mount package），诸如晶体管外形封装之类，诸如TO263之类。
包括图2A-2B的图2，图示了根据可替换的实施例的半导体封装。
在各种实施例中，半导体封装尺寸可以通过改变第二引线框架30的厚度来被修改。在一个实施例中，第二引线框架30可以具有大约1.9mm的厚度，而第一引线框架10具有小于1mm的厚度，而封装的厚度可以是大约3.9mm。因此，在此图示中，半导体封装比在图1中所图示的半导体封装的一个实施例薄。
包括图3A-3B的图3，图示了根据本发明的实施例的具有增加的漏电距离（creepage distance）的半导体封装。
在此实施例中，第二引线框架30被防止短路第二引线120。第二引线框架30可以具有可以短路多个引线90中的各种引线的定位错误。例如，如果第二引线框架30延伸超过管芯踏板105，那么第一引线110可以与第二引线120短路，而且管芯踏板105可以与第二引线120短路。
参见图3B，为了避免这样的短路，在此实施例中，半导体封装的设计被改变，使得只有灌封80的薄部（thin section）81支撑多个引线90。因而，第二引线框架30不在多个引线90之下延伸。结果，任何这样的第二引线框架30的不正确的定位在模塑工艺中被解决。
在各种实施例中，薄部81的厚度小于第二引线框架30的管芯附着115的厚度。在一个或者多个实施例中，薄部81的厚度小于第二引线框架30的管芯附着115的厚度的一半。在一个或者多个实施例中，薄部81的厚度是大约0.1到0.6倍于第二引线框架30的管芯附着115的厚度。作为图示，在一个实施例中，第二引线框架30的管芯附着115的厚度是大约1.27mm，而薄部81的厚度小于0.6mm。
薄部81通过第一侧壁81A和第二侧壁81B来被形成。在一个或者多个实施中，第一侧壁81A可以被定位在管芯踏板105和第二引线120之间。在一些实施例中，第一侧壁81A可以被定位来重叠第一引线框架10的管芯踏板105。
因而，在各种实施中，薄部81的使用能够增加第二引线120和第二引线框架30之间的距离（漏电距离）。
图4图示了根据本发明的实施例的具有洞的第二引线框架。
如在图4中所图示，第二引线框架30包括洞35，其被用来固定贴近半导体封装的可选的散热装置。第二引线框架30包括被配置为固定半导体芯片的管芯附着115。
包括图5A-5B的图5，图示了根据本发明的实施例的具有多个引线和管芯踏板的第一引线框架。
参见图5A，第一引线框架10包括管芯踏板105和多个引线90。多个引线90包括沿着管芯踏板105延伸的第一引线110。多个引线还包括第二引线120和多个第三引线130。一些实施例可以只具有单个第三引线130。多个第三引线130被电耦合到管芯踏板105。相比之下，第一引线110和第二引线120被与管芯踏板105隔离。
图5B图示了第一引线框架10的可替换的实施例。不同于在图5A中所图示的实施例，在此实施例中，管芯踏板105具有非对称的形状。结果，第二引线120沿着第一引线框架10的边缘，而多个第三引线或者该第三引线130被部署在第一引线110和第二引线120之间。
图6-10图示了根据本发明的实施例的在制造的各种阶段期间的半导体封装。
图6图示了根据本发明的实施例的在半导体封装的制造期间的第一引线框架和第二引线框架的顶视图。参照图6，第一引线框架10被定位在第二引线框架30之上。在一个或者多个实施例中，第一引线框架10的管芯踏板105重叠第二引线框架30的管芯附着115。在一个或者多个实施例中，第二引线框架30的管芯附着115部分地重叠第一引线框架10的管芯踏板105。第一引线框架10通过使用可以是绝缘或者导电的粘合剂来被固定到第二引线框架30上。在一些实施例中，绝缘粘合层可以被用来附着第一引线框架10与第二引线框架30，以致隔离半导体芯片20与第二引线框架30上的电势。
包括图7A-7B的图7，图示了根据本发明的实施例的在放置半导体芯片之后正在被制造的半导体封装，其中图7A图示了顶视图，并且其中图7B图示了横截面视图。
如在图7A和7B中所图示，半导体芯片20被附着到第一引线框架10。在一个或者多个实施例中，半导体芯片20可以通过使用粘合层来被附着到第一引线框架10。在各种实施例中粘合层可以是导电膏或者焊接材料。
在一些实施例中，半导体芯片20可以在附着第一引线框架10与第二引线框架30之前被附着到第一引线框架10。半导体芯片20被与第一引线110间隔开，并且因此必须在分离的工艺中被互连。
半导体芯片20可以通过使用常规处理来被形成在例如晶片之内，所述晶片被切割来形成包括半导体芯片20的多个半导体芯片。如上所描述的，半导体芯片20可以被形成在诸如大块硅衬底或者绝缘衬底上的硅（SOI）衬底之类的硅衬底上。可替换地，半导体芯片20可以是形成在碳化硅（SiC）上的器件。本发明的实施例还可以包括形成在化合物半导体衬底上的器件，并且可以包括在异质外延（hetero-epitaxial）衬底上的器件。在一个实施例中，半导体芯片20是至少部分地形成在氮化镓（GaN）上的器件，其可以是在蓝宝石或者硅衬底上的 GaN。
在各种实施例中，半导体芯片20可以包括功率芯片，其例如引大电流（例如，大于30安培）。在各种实施例中，半导体芯片20可以包括诸如两端或者三端功率器件之类的分立垂直器件。半导体芯片20的例子包括PIN或者肖特基二极管、MISFET、JFET、BJT、IGBT或者晶闸管。
在各种实施例中，半导体芯片20可以是被配置为在大约20V到大约1000V工作的垂直半导体器件。在一个实施例中，半导体芯片20可以被配置为在大约20V到大约100V工作。在另一个实施例中，半导体芯片20可以被配置为在大约100V到大约500V工作。在还有另一个实施例中，半导体芯片20可以被配置为在大约500V到大约1000V工作。在一个实施例中，半导体芯片20可以是NPN晶体管。在另一个实施例中，半导体芯片20可以是PNP晶体管。在还有另一个实施例中，半导体芯片20可以是n沟道MISFET。在另一实施例中，半导体芯片20可以是p沟道MISFET。在一个或者多个实施例中，半导体芯片20可以包括诸如垂直MISFET和二极管、或者可替换地被绝缘区域分离的两个MISFET器件之类的多个器件。
在各种实施例中，半导体芯片20从顶表面到相对的底表面的厚度可以小于50μm。在一个或者多个实施例中，半导体芯片20的厚度可以小于20μm。在一个或者多个实施例中，半导体芯片20的厚度可以小于10μm。
包括图8A-8D的图8，图示了根据本发明的实施例的在半导体芯片之上形成互连之后正在制造的半导体封装，其中图8A和8B图示了在可替换的实施例中的顶视图，并且其中图8C和图8D图示了在可替换的实施例中的横截面视图。
如在图8A和8C中所图示，多个互连70被形成在半导体芯片20之上。多个互连70电耦合半导体芯片20的顶表面上的接触区域与第一引线110。多个互连70可以包括诸如线接合、夹片、引线、带等等之类的任何类型的互连。在各种实施例中，多个互连70可以通过使用第一粘合层60来被附着到半导体芯片20上。在一个实施例中第一粘合层60可以是焊接材料。在另一个实施例中，第一粘合层60可以包括诸如银膏之类的导电膏。类似地，多个互连70可以通过使用第二粘合层65来被附着到第一引线110。在各种实施例中，第二粘合层65可以是焊接材料和/或者导电膏。
在一个或者多个实施例中，如在图8B中所图示，多个互连70可以包括夹片平板。在一个实施例中，夹片平板可以作为单个平板被形成。
在一个或者多个实施例中，如在图8D中所图示，多个互连70可以包括线接合，其可以包括铝或者铜。在一个或者多个实施例中，这样的铝线的厚度可以是大约10μm到大约1000μm。在另一个实施例中，线接合330可以包括金。这样的金线的厚度可以是大约10μm到大约100μm。
在各种实施例中，球形接合或者楔形接合可以被用来附着多个互连70。在各种实施例中，多个互连70可以通过使用热超声接合、超声接合或者热压（thermo-compression）接合来被形成。热超声接合利用温度、超声波、和低冲击力、和球形/楔形方法。超声接合利用超声波和低冲击力、以及仅仅楔形方法。热压接合利用温度和高冲击力、以及仅仅楔形方法。
例如，在一种情况下，热超声接合可以与金线和铜线一起被使用。两种线接合针对每个互连被形成，其中一个在半导体芯片20的接触区域（例如，第三接触区域23）处，而另一个在多个引线90的第一引线110处。接合温度、超声波能量、和接合力和时间可以必须被严密控制，以形成可靠的连接。
在一个或者多个实施例中，针对互连工艺，焊剂（solder fulx）和焊接材料可以被沉积，以形成第一粘合层60和第二粘合层65。焊接材料可以被电镀，尽管，在其它实施例中，诸如化学镀或者诸如气相沉积之类的沉积工艺之类的其它工艺也可以被使用。焊接材料可以是单层，或者包括具有不同成分的多层。例如，在一个实施例中，焊接材料可以包括铅（Pb）层，随后是锡（Sn）层。在另一个实施例中，SnAg可以作为焊接材料被沉积。其它例子包括SnPbAg、SnPb、PbAg、PbIn和诸如SnBi、SnAgCu、SnTn和SiZn之类的无铅材料。在各种实施例中，其它合适的材料可以被沉积。
热处理可以被执行以形成图8C-8D中所图示的第一粘合层60和第二粘合层65。例如，在当Pb/Sb被沉积的实施例中，在回流（reflow）之后，包括95Pb/5Sn（95/5）或者90Pb/10Sn（90/10）的高铅合金用超过300℃的熔化温度来被形成。在不同的实施例中，共晶体（eutectic）63Pb/37Sn（63/37）用183℃的熔化温度来被形成。类似地，在一些实施例中，无铅粘合层可以被形成，而具有97.5Sn/2.6Ag（97.5/2.5）的成分。
包括图9A-9B的图9，图示了根据本发明的实施例的在灌封之后正在制造的半导体封装，其中图9A图示了顶视图，并且其中图9B图示了横截面视图。
如在图9A和9B中所图示，灌封80在第一引线框架10、第二引线框架30、半导体芯片20和多个互连70之上被形成。灌封80被应用到半导体芯片20之上并且至少部分地封闭半导体芯片20。在一个或者多个实施例中，灌封80通过使用诸如压缩模塑（compression molding）、转移模塑（transfer molding）工艺、注入模塑（injection molding）、起粒模塑（granulate molding）、粉末模塑（powder molding）、液体模塑（liquid molding）之类的模塑工艺以及诸如模板（stencil）或者丝网印刷（screen printing）之类的印刷工艺来被应用。
在各种实施例中，灌封80包括电介质材料，而且在一个实施例中可以包括模塑化合物（mold compound）。在其它实施例中，灌封80可以包括聚合物、共聚物、生物聚合物、纤维浸渍聚合物（例如，在树脂中的碳或者玻璃纤维）、颗粒填充聚合物和其它有机材料中的一个或者多个。在一个或者多个实施例中，灌封80包括不是通过使用模塑化合物以及诸如环氧树脂和/或硅树脂（silicone）之类的材料来被形成的密封剂。在各种实施例中，灌封80可以由任何适当的硬质塑料、热塑材料、热固材料或者叠层组成。在一些实施例中，灌封80的材料可以包括填料材料。在一个实施例中，灌封80可以包括环氧材料和填充材料或有机填充材料，所述填充材料包括小玻璃颗粒或者像氧化铝一样的其它电绝缘矿物填料材料。
灌封80可以被固化，即受到热工艺来被硬化，因而形成了保护半导体芯片20的气密密封。固化工艺使灌封80变硬，从而形成支持第一引线框架10、第二引线框架30和半导体芯片20的单个衬底。
图10图示了根据本发明的实施例的在切单片期间的半导体封装的顶视图。
如果在半导体封装的形成中使用了批量工艺（batch process），那么切单片工艺可以被执行来分离邻近的引线框架。例如，在批量工艺的情况下，邻近的半导体封装可以通过第一引线框架10和第二引线框架30来被连接。在切单片期间，例如，通过使用锯削工艺或者冲压工艺，第一引线框架10和第二引线框架30被分离，以形成单独的半导体封装。图10中的虚线图示了在切单片期间锯片的可能方向。切单片工艺可以分离第一引线110和第二引线120，以及类似地分离第二引线120和第三引线130。
随后的处理可以如在常规处理中那样被执行。例如，暴露的多个引线90的电镀可以被执行来改进随后的焊接工艺。
虽然参照作为说明性的实施例，本发明已经被描述，而本说明书不意图在限制意义上被理解。说明性的实施例的各种修改和组合以及本发明的其它实施例，根据参照本说明书，对于本领域的技术人员将是显然的。作为图示，在图1-10中所描述的实施例可以以各种实施例的方式被彼此组合。因此，所附的权利要求意图包括任何这样的修改或者实施例。
尽管本发明及其优点已经被详细地描述，但是应该理解的是，各种改变、置换和更改可以在这里被进行，而不离开如由所附权利要求所定义的本发明的精神和范围。例如，本领域的技术人员容易理解的是，在这里被描述的许多特征、功能、工艺和材料可以变化，而同时留在本发明的范围内。
此外，本申请的范围不意图被限制在说明中所描述的工艺、机器、制造、物质成分、手段、方法和步骤的特定实施例。如本领域的技术人员根据本发明的公开将容易领会的那样，根据本发明可以利用现存或者后来被发展的工艺、机器、制造、物质成分、手段、方法和步骤，其和相应的实施例执行基本上相同的功能或者实现基本上相同的结果。因此，所附的权利要求意图包括这样的工艺、机器、制造、物质成分、手段、方法和步骤在它们的范围之内。

Claims (27)

1.一种半导体封装，其包括：
第一引线框架；
被部署在第一引线框架之上的第二引线框架，而第二引线框架具有管芯踏板和多个引线；以及
被部署在第二引线框架之上的半导体芯片，而半导体芯片耦合到多个引线。
2.根据权利要求1所述的封装，其中，
半导体芯片包括在第一侧上的第一接触区域、在第一侧上的第二接触区域、和在第二侧上的第三接触区域，而第二侧与第一侧相对。
3.根据权利要求2所述的封装，其中，
半导体芯片的第一侧面向第二引线框架。
4.根据权利要求1所述的封装，其中，
第一引线框架比第二引线框架厚。
5.根据权利要求1所述的封装，其中，
半导体芯片包括垂直功率半导体芯片。
6.根据权利要求1所述的封装，其中，
半导体芯片与第一引线框架电绝缘。
7.根据权利要求1所述的封装，其中，
半导体芯片包括具有在第一侧上的源极区域、在第一侧上的栅极区域、在第二侧上的漏极区域的垂直晶体管，其中第二侧与第一侧相对。
8.根据权利要求7所述的封装，其中，
第二引线框架包括耦合到源极区域的管芯踏板，其中多个引线包括耦合到管芯踏板的源极引线、耦合到漏极区域的漏极引线和耦合到栅极区域的栅极引线。
9.根据权利要求1所述的封装，其中，
半导体芯片的主要表面由管芯踏板和多个引线中的至少一个引线来支撑。
10.根据权利要求1所述的封装，进一步包括：
部署在第一引线框架、第二引线框架和半导体芯片处的灌封，其中灌封具有部署在多个引线处的薄部。
11.一种半导体封装，其包括：
具有第一管芯踏板的第一引线框架;
第二引线框架，而第二引线框架具有第二管芯踏板和多个引线，第二管芯踏板被部署在第一管芯踏板之上；以及
被部署在第二管芯踏板之上的半导体芯片，而半导体芯片在面向第二引线框架的第一侧上具有多个接触区域，而多个接触区域被耦合到多个引线。
12.根据权利要求11所述的封装，其中，
半导体芯片具有相对于第一侧的第二侧，其中第二侧包括接触区域，其中在第二侧上的接触区域被耦合到多个引线中的引线。
13.根据权利要求11所述的封装，进一步包括：
被部署在第一引线框架、第二引线框架和半导体芯片处的灌封。
14.根据权利要求13所述的封装，其中，
灌封具有被部署在多个引线处的薄部。
15.根据权利要求14所述的封装，其中，
灌封具有第一侧壁和第二侧壁，以致形成薄部，并且其中第一侧壁被定位在第一管芯踏板和多个引线之间。
16.根据权利要求14所述的封装，其中，
灌封具有第一侧壁和第二侧壁，以致形成薄部，并且其中第一侧壁被定位在第二管芯踏板和多个引线之间。
17.根据权利要求14所述的封装，其中，
薄部具有第一厚度，其中第一管芯踏板具有第二厚度，并且其中第一厚度是第二厚度的大约10%到大约60%。
18.根据权利要求14所述的封装，其中，
半导体芯片包括垂直晶体管，而多个接触区域具有在第一侧上的源极区域和在第一侧上的栅极区域，其中垂直晶体管包括在第二侧上的漏极区域，并且其中第二侧与第一侧相对。
19.根据权利要求18所述的封装，其中，
第二管芯踏板被耦合到源极区域，其中多个引线包括耦合到第二管芯踏板的源极引线、耦合到漏极区域的漏极引线和耦合到栅极区域的栅极引线。
20.根据权利要求14所述的封装，其中，
半导体芯片的主要表面由第二管芯踏板和多个引线中的至少一个引线来支撑。
21.一种形成半导体封装的方法，该方法包括：
提供具有第一管芯踏板的第一引线框架；
提供具有第二管芯踏板和多个引线的第二引线框架；
附着第二管芯踏板到第一管芯踏板；以及
附着半导体芯片到第二管芯踏板，半导体芯片在面向第二引线框架的第一侧面上具有多个接触区域，而多个接触区域被耦合到多个引线。
22.根据权利要求21所述的方法，进一步包括：
在第一引线框架、第二引线框架和半导体芯片处形成灌封。
23.根据权利要求22所述的方法，其中，
形成灌封包括在多个引线处形成灌封的薄部。
24.根据权利要求21所述的方法，其中，
半导体芯片包括垂直功率半导体芯片。
25.根据权利要求21所述的方法，其中，
半导体芯片与第一引线框架电绝缘。
26.根据权利要求21所述的方法，其中，
半导体芯片包括垂直晶体管，其中多个接触区域包括在第一侧上的源极区域和栅极区域，其中垂直晶体管包括在第二侧上的漏极区域，并且其中第二侧与第一侧相对。
27.根据权利要求26所述的方法，其中，
第二管芯踏板被电耦合到源极区域，其中多个引线包括耦合到第二管芯踏板的源极引线、耦合到漏极区域的漏极引线和耦合到栅极区域的栅极引线。
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