CN112924853A

CN112924853A - CP/FT test method, device, system, electronic equipment and medium

Info

Publication number: CN112924853A
Application number: CN202110390325.5A
Authority: CN
Inventors: 曹祥荣; 唐伟; 周润; 黄赛飞
Original assignee: Hunan Goke Microelectronics Co Ltd
Current assignee: Hunan Goke Microelectronics Co Ltd
Priority date: 2021-04-12
Filing date: 2021-04-12
Publication date: 2021-06-08

Abstract

The application discloses a CP/FT test method, which comprises the following steps: generating a test stimulus according to the SPI timing diagram; injecting test excitation into a test chip through an SPI interface; acquiring an output value of a test chip under test excitation; and determining whether the test chip is qualified or not according to the output value. The method can greatly save the test time, reduce the test cost and avoid the defect that the test cost is higher because the transmission frequency is low when the serial port protocol is adopted to carry out CP/FT test in the related technology. The application also provides a CP/FT testing device, a CP/FT testing system, electronic equipment and a computer-readable storage medium, and the CP/FT testing device, the CP/FT testing system, the electronic equipment and the computer-readable storage medium have the beneficial effects.

Description

CP/FT test method, device, system, electronic equipment and medium

Technical Field

The present application relates to the field of CP/FT testing technologies, and in particular, to a CP/FT testing method, apparatus, system, electronic device, and computer-readable storage medium.

Background

During the manufacturing and packaging of chips, not every chip is a correctly functioning circuit due to many factors. In the CP test stage, the bad chips are screened out as much as possible before the chips are packaged, the packaging cost is reduced, only test items which have great influence on the yield are selected as much as possible, the test items which have great test difficulty, high cost and low fail rate can be put into the FT stage for retesting, the test significance of the items in the CP stage is not great, and the test cost is only increased; the FT test phase is a successful CP test after the chip is packaged, but the items not performed in the CP phase are tested.

In the related technology, a chip FT test program is updated based on a serial port protocol, the fastest baud rate of the serial port protocol is 921600b/s, the transmission frequency is still in a KHz level, the speed is very low, and the test cost is a great impact, because the CP/FT test charges according to a second level, the test time is long, the test cost is increased, the total generation cost of the chip is increased, and the chip profit is reduced.

Disclosure of Invention

The application aims to provide a CP/FT test method, which can greatly save test time and reduce test cost. The specific scheme is as follows:

in a first aspect, the application discloses a CP/FT testing method, comprising:

generating a test stimulus according to the SPI timing diagram;

injecting the test excitation into a test chip through an SPI interface;

acquiring an output value of the test chip under the test excitation;

and determining whether the test chip is qualified or not according to the output value.

Optionally, obtaining an output value of the test chip under the test excitation includes:

analyzing the test excitation by using the SPI interface, and determining a target test IP for testing in the test chip;

and acquiring an output value of the target test IP.

Optionally, obtaining the output value of the target test IP includes:

and measuring an output value of a pin corresponding to the target test IP, or reading a state value of a register of the target test IP, and taking the state value as the output value.

Optionally, before generating the test stimulus according to the SPI timing diagram, the method further includes:

and setting the byte number of data read and written each time in the data transmission format of the SPI interface to be equal to the bit number of the register of the target test IP.

Optionally, determining whether the test chip is qualified according to the output value includes:

comparing the output value with a preset expected value under the test excitation;

if the chip is the same as the test chip, determining that the test chip is qualified;

and if not, determining that the test chip is unqualified.

In a second aspect, the present application discloses a CP/FT testing apparatus, comprising:

the generating module is used for generating test excitation according to the SPI timing diagram;

the injection module is used for injecting the test excitation into the test chip through the SPI interface;

the acquisition module is used for acquiring an output value of the test chip under the test excitation;

and the determining module is used for determining whether the test chip is qualified or not according to the output value.

Optionally, the obtaining module includes:

the determining unit is used for analyzing the test excitation by using the SPI interface and determining a target test IP for testing in the test chip;

and the acquisition unit is used for acquiring the output value of the target test IP.

In a third aspect, the present application discloses a CP/FT testing system, comprising:

the test chip is used for testing under test excitation filled by the test machine table to generate an output value;

and the test machine is used for executing the steps of the CP/FT test method.

In a fourth aspect, the present application discloses an electronic device, comprising:

a memory for storing a computer program;

and the processor is used for realizing the steps of the CP/FT test method when executing the computer program.

In a fifth aspect, the present application discloses a computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the above CP/FT testing method.

The application provides a CP/FT test method, which comprises the following steps: generating a test stimulus according to the SPI timing diagram; injecting the test excitation into a test chip through an SPI interface; acquiring an output value of the test chip under the test excitation; and determining whether the test chip is qualified or not according to the output value.

It can be seen that, this application utilizes the SPI interface to test the test chip, because the clock frequency of SPI interface is at tens megahertz, transmission frequency is very fast, can practice thrift test time greatly, reduces test cost, has avoided adopting the serial port protocol to carry out CP/FT test among the correlation technique, because transmission frequency is low, leads to the great defect of test cost, and this application can greatly practice thrift test time, reduces test cost, improves the chip profit. The application also provides a CP/FT testing device, a CP/FT testing system, electronic equipment and a computer-readable storage medium, which have the beneficial effects and are not described herein again.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a flowchart of a CP/FT testing method provided in an embodiment of the present application;

FIG. 2 is a timing diagram of a 3-wire mode SPI interface protocol according to an embodiment of the present disclosure;

FIG. 3 is a block diagram illustrating a design of an embodiment of the present application;

fig. 4 is a schematic structural diagram of a CP/FT testing apparatus according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

A common CP/FT test method includes pulling a pins pin of a test IP (usually an analog IP or a hard core) to a PAD of a chip in a pin multiplexing manner, and in a test mode, testing a state of an output pins by controlling an input pins of the test IP, where the test Pattern generally provides a method in which an SoC design engineer runs out a VCD waveform through an EDA tool and then provides the VCD waveform to a CP/FT test engineer who converts the VCD waveform into a stimulus that can be recognized by a test machine through a tool for CP/FT testing, and if the test IP is simple, there are few pin pins, the method can be used; however, as the supply mode is a VCD waveform (waveform format output by an IC EDA simulation tool), the debugging may be iterated continuously, and the convergence time is long; if the testing IP is complex, pin pins are more, such as Hdmi Phy and Usb Phy, the multiplexing PAD mode is more difficult, the debugging iteration is more troublesome, for the IP needing Trim item, such as some DAC, after the Trim is finished, the value is immediately burned into OTP or Efuse, and the multiplexing PAD mode is more troublesome; the PAD, namely the IO PAD is a chip pin processing module, namely, a signal of a chip pin can be processed and sent to the inside of a chip, and a signal output by the inside of the chip can be processed and sent to the chip pin.

The method adopts a Pattern based on a serial protocol to update a chip FT test program, has no problem in the aspect of test flow, but has the defect that the test cost is not considered, the serial protocol is used for burning or updating the test program, the current fastest baud rate of the serial protocol is 921600b/s, the transmission frequency is in a KHz level, the speed is very low, the test cost is greatly impacted, the CP/FT test is charged according to a second level, the test time is long, the test cost is increased, the total generation cost of the chip is increased, the chip profit is reduced, and the method is not advisable in the aspect of providing or updating the FT test program by using the serial protocol.

Based on the above technical problems, the present embodiment provides a CP/FT testing method, which can greatly save testing time, reduce testing cost, and improve chip profits, specifically referring to fig. 1, where fig. 1 is a flowchart of the CP/FT testing method provided by the present embodiment, and specifically includes:

and S101, generating test excitation according to the SPI time sequence.

It can be understood that, in the present application, the SPI Interface protocol is used for the CP/FT test, and the SPI timing diagram is a timing diagram inherent to the SPI (Serial Peripheral Interface) Interface protocol. The specific process of generating the test stimulus is not limited in this embodiment, and the test program may be generated according to the SPI timing chart first, and then converted into the test stimulus. It can be understood that the test stimulus refers to a value to be loaded at an input end of a test chip, an IO interface is at a high level or a low level, and to enable a test, a large number of test stimuli must be provided for a test machine to use and load on the test chip, so as to activate an internally designed test circuit for a test purpose. It is understood that the test stimulus in this embodiment may include CSB timing, SCLK timing, and SDIO timing. It should be further noted that, the present embodiment does not limit the specific mode of the SPI interface, and may be a 3-line mode or a 4-line mode, and it is understood that the main difference between the configuration of the 3-line mode and the configuration of the 4-line mode is in the transmitted data format and I/O conversion.

In a specific embodiment, in order to effectively improve data transmission efficiency and optimize test time, in this embodiment, before generating a test stimulus according to the SPI timing chart, the method may further include:

and setting the byte number of data read and written each time in the data transmission format of the SPI interface to be equal to the bit number of a register of the target test IP.

It can be understood that the data transmission format of the SPI interface in this embodiment is composed of the control command + the address + the data, and this embodiment does not limit the specific data transmission format and can be set according to actual requirements. In the embodiment, the number of bytes of data read and written each time is set to be equal to the number of bits of the register of the target test IP, so that the data transmission efficiency can be effectively improved, and the test time is optimized. For example, when the number of bits of a register configured by a target test IP in the test chip is less than 8 bits, it is only necessary to set the number of bytes of data read and written each time to be equal to 1byte, and if the number of bytes of data read and written each time is set to be equal to 2bytes or 4bytes, redundant bits are meaningless, and transmission time is wasted.

And S102, injecting test excitation into the test chip through the SPI interface.

Adopt the SPI interface in this embodiment, pour test excitation into test chip. It can be understood that the interface protocol of the SPI interface is simple, and is a high-speed, half-duplex or full-duplex, synchronous communication bus. By using the SPI protocol, the updating iteration speed is high, so that the task of testing the test machine is more easily converged. The clock frequency of a general SPI interface is dozens of megahertz, if the SPI interface is selected in CP/FT test, the limit speed of the test is limited by the limit frequency of GPIO (input/output IO) and the time sequence constraint of PADs in the design of a test chip, and at present, under the 40nm technology and below, the common GPIO can reach about 100 MHz; on the other hand, limited by CP/FT test machine, IO of digital plate of general test machine can provide 1600Mbps, and can provide 800M test clock at the fastest, but with license restriction, and routing restriction of PCB of machine, default condition, can provide 50MHz clock; therefore, when the SPI is used as a CP/FT test interface, the SPI can be comprehensively considered, the SPI can be selected to operate to 50MHz, the speed is dozens of times faster than that of a serial port protocol, and compared with a data transmission mode of the serial port protocol, the data transmission bandwidth can be increased greatly, the test time is greatly saved, the test cost is reduced, and the profit of a chip is improved.

S103, obtaining an output value of the test chip under the test excitation.

It can be understood that after the test machine injects the test stimulus to the test chip, the CP/FT test of the test chip is performed to generate the output value. The embodiment does not limit the specific process of obtaining the output value of the test chip under the test excitation. In a specific embodiment, obtaining the output value of the test chip under the test stimulus may include:

and acquiring an output value of the target test IP.

It is understood that the target test IP in the present embodiment is a functional module in a test chip. In this embodiment, a target test IP to be tested can be determined by analyzing the test stimulus, and an output value of the target test IP is obtained.

The embodiment does not limit the specific classification corresponding to the obtained output value of the target test IP, for example, the target test IP may generate a state value under test excitation, and the state value may be stored in a register, so that the SP interface may be used to read the state value of the register, that is, obtain the output value of the target test IP; the output value of the target test IP can also be obtained by measuring the output value of the target test IP pin, for example, whether the test pll is normal or not, and measuring the output value of the test pll at the corresponding multiplexing pin under the filling test excitation.

In a specific embodiment, obtaining the output value of the target test IP may include:

and measuring the output value of the corresponding pin of the target test IP, or reading the state value of the register of the target test IP, and taking the state value as the output value.

And S104, determining whether the test chip is qualified or not according to the output value.

In this embodiment, whether the test chip is qualified or not is determined according to the output value. The specific process of determining whether the test chip is qualified according to the output value is not limited in this embodiment. In a specific embodiment, determining whether the test chip is qualified according to the output value may include:

comparing the output value with a preset expected value under test excitation;

if the two chips are the same, determining that the test chip is qualified;

if not, determining that the test chip is unqualified.

The specific size of the expected value is not limited in this embodiment, and may be determined according to a specific test. In this embodiment, the output value is compared with the preset expected value under the test excitation, and if the output value is the same as the preset expected value, the test chip is qualified, and if the output value is not the same as the preset expected value, the test chip is unqualified.

Based on the technical scheme, the SPI interface is utilized to test the test chip in the embodiment, and the clock frequency of the SPI interface is dozens of megahertz, so that the transmission frequency is high, the test time can be greatly saved, the test cost is reduced, and the defect that the test cost is high due to the low transmission frequency when a serial port protocol is adopted to carry out CP/FT test in the related technology is avoided.

The following provides a specific embodiment of a 3-wire mode SPI interface for CP/FT testing. Fig. 2 is a timing diagram of the SPI protocol in 3-wire mode provided in this embodiment. When the CSB is in read-write operation, the CSB must be pulled down, and after the read-write operation is finished, the CSB must be pulled up; with SDIO as input, data must be written each time on the rising edge of SCLK; when the SDIO is used as an output port, the register data is output at the falling edge of the SCLK each time; when R/W in SDIO is high, it indicates a read operation, and low indicates a write operation. W1, W0 indicates the number of Bytes of data to be read and written, and when { W1, W0} ═ 0, 0}, 8-bit register data, i.e. 1Bytes, are read and written each time; when { W1, W0} ═ 0, 1}, 16bit register data, i.e. 2Bytes, are read and written each time; when { W1, W0} - {1, 0} or {1, 1}, 32-bit register data, i.e., 4Bytes, is read and written each time. Appropriate W1, W0 choices may optimize test time. A31-A0 indicate register addresses of 32 bits. DN to D0 indicate the Nbit register data to be read or written.

When the SPI interface performs a write operation, { W1, W0} - {0, 0}, writing 1bit0+ 2bit 0+32bit address +8bit data; { W1, W0} - {0, 1}, writing 1bit0+1bit 0+1bit 1+32bit address +16bit data; and so on for the others. When a read operation of the SPI interface is executed, { W1, W0} - {0, 0}, a 1bit 1+2bit 0+32bit address needs to be written first, after the last 1bit address a0 writes SDIO on the rising edge of SCLK, the SDIO will change from the input port to the output port, and then on the next 8 falling edges of SCLK, the SDIO will output 8bit data of the register; { W1, W0} - {0, 1}, firstly, 1bit 1+1bit0+1bit 1+32bit address needs to be written, after the last 1bit address a0 writes SDIO at the rising edge of SCLK, SDIO will change from input port to output port, then at the next 16 falling edges of SCLK, SDIO will output the 16bit data of the register; and so on for the others.

Fig. 3 is a block diagram of a design of an embodiment provided in this embodiment. Wherein, GPIO _ MUX: the SPI protocol generally carries out multiplexing input and output with PAD on a test chip and is used for pin multiplexing; SPI SLAVE I/F: converting the time sequence of the SPI interface protocol into the interface time sequence of the internal register bus; the Reg Access arbiter is an arbitration module of a chip internal register bus, and when a plurality of masters (hosts) Access, one Master is selected to Access a TEST IP (target TEST IP). The method includes inputting an SPI interface in a three-wire mode to an SPI SLAVE I/F module in a multiplexing pinmux mode, wherein the SPI SLAVE I/F module is the implementation of an SPI timing chart in fig. 2, transferring the SPI interface to an interface timing sequence of an internal register bus, then hanging the internal register bus to a register arbiter Reg Access arbiter, and controlling the input end of a target test IP through a control register like other Master IPs (such as a DSP/CPU/MCU and other Master masters), thereby controlling the output behavior of the target test IP or reading the state of a register of the target test IP, namely the output value of a corresponding pin of the corresponding target test IP to be measured or the state value of the register of the target test IP to be read. The design is flexible in control of the TEST IP (target TEST IP), particularly the target TEST IP of the Trim item is required to be carried out, the Trim item can be directly carried out through the SPI (serial peripheral interface), the Trim value is calculated, and then the Trim value is directly burnt into the OTP or the Efuse through the SPI, so that the method is convenient and quick.

The data transmission format in this embodiment is not limited, and as long as the protocol with the CP/FT test engineer is good, the test engineer may develop a script based on the well-agreed SPI timing chart, and then may generate the data transmission format. For example, it may be spi _ write 0x 00x 1f6300000x5a, spi _ write 0x 30 x1f6300000x5a5a5a5a, spi _ read 0x 00x 1f630000, spi _ read 0x 30 x1f630000, where spi _ write/spi _ read is a write/read command, 0x0/0x1/0x3 is the number of bytes written/read, 0x1f630000 is the address of the read/write register, and 0x5a/0x5a5a5a is the data written.

Based on the technical scheme, the simple SPI interface is used as an input/output port of excitation of CP/FT test, so that the complexity can be effectively reduced, and the test cost is greatly saved.

Referring to fig. 4, fig. 4 is a schematic structural diagram of a CP/FT testing apparatus provided in an embodiment of the present application, where the CP/FT testing apparatus provided in the embodiment of the present application is described below, where the apparatus described below and the CP/FT testing method described above may be referred to correspondingly, and related modules are all disposed therein, and the CP/FT testing apparatus provided in the embodiment of the present application includes:

in some specific embodiments, the method specifically includes:

a generating module 401, configured to generate a test stimulus according to the SPI timing chart;

a pouring module 402, configured to pour a test stimulus into the test chip through the SPI interface;

an obtaining module 403, configured to obtain an output value of the test chip under the test excitation;

and a determining module 404, configured to determine whether the test chip is qualified according to the output value.

In some specific embodiments, the obtaining module 403 includes:

the determination unit is used for analyzing the test excitation by utilizing the SPI interface and determining a target test IP for testing in the test chip;

In some specific embodiments, the obtaining unit includes:

and the measurement reading unit is used for measuring the output value of the corresponding pin of the target test IP or reading the state value of the register of the target test IP, and taking the state value as the output value.

In some specific embodiments, the method further comprises:

and the setting module is used for setting the number of bytes of data read and written each time in the data transmission format of the SPI interface to be equal to the bit number of the register of the target test IP.

In some specific embodiments, the determining module 404 includes:

the comparison unit is used for comparing the output value with a preset expected value under test excitation;

the first determining unit is used for determining that the test chip is qualified if the test chips are the same;

and the second determining unit is used for determining that the test chip is unqualified if the test chips are different.

Since the embodiments of the CP/FT testing apparatus portion and the CP/FT testing method portion correspond to each other, please refer to the description of the embodiments of the CP/FT testing method portion for the embodiments of the CP/FT testing apparatus portion, and will not be described herein again.

The application also discloses a CP/FT test system, including:

and the test machine is used for executing the steps of the CP/FT test method.

Since the embodiments of the CP/FT test system part and the CP/FT test method part correspond to each other, please refer to the description of the embodiments of the CP/FT test method part for the embodiments of the CP/FT test system part, which is not repeated here.

In the following, an electronic device provided by an embodiment of the present application is introduced, and the electronic device described below and the CP/FT testing method described above may be referred to correspondingly.

The application also discloses an electronic device, including:

a memory for storing a computer program;

Since the embodiment of the electronic device portion corresponds to the embodiment of the CP/FT testing method portion, please refer to the description of the embodiment of the CP/FT testing method portion for the embodiment of the electronic device portion, which is not repeated here.

In the following, a computer-readable storage medium provided by an embodiment of the present application is described, and the computer-readable storage medium described below and the CP/FT testing method described above may be referred to correspondingly.

The application discloses a computer readable storage medium, on which a computer program is stored, which when executed by a processor implements the steps of the above-mentioned CP/FT testing method.

Since the embodiment of the computer-readable storage medium portion corresponds to the embodiment of the CP/FT testing method portion, please refer to the description of the embodiment of the CP/FT testing method portion for the embodiment of the computer-readable storage medium portion, which is not repeated here.

The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.

Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

The present application provides a CP/FT testing method, apparatus, system, electronic device, and computer readable storage medium. The principles and embodiments of the present application are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present application. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.

Claims

1. A CP/FT test method, comprising:

generating a test stimulus according to the SPI timing diagram;

injecting the test excitation into a test chip through an SPI interface;

acquiring an output value of the test chip under the test excitation;

2. The CP/FT test method according to claim 1, wherein obtaining the output value of the test chip under the test stimulus comprises:

and acquiring an output value of the target test IP.

3. The CP/FT test method according to claim 2, wherein obtaining the output value of the target test IP comprises:

4. The CP/FT test method of claim 2, further comprising, prior to generating test stimuli according to the SPI timing diagram:

5. The CP/FT test method of claim 1, wherein determining whether the test chip is qualified according to the output value comprises:

and if not, determining that the test chip is unqualified.

6. A CP/FT test apparatus, comprising:

7. The CP/FT test apparatus according to claim 1, wherein the obtaining module comprises:

8. A CP/FT test system, comprising:

a testing machine for performing the steps of the CP/FT testing method of any of the preceding claims 1 to 5.

9. An electronic device, comprising:

a memory for storing a computer program;

a processor for implementing the steps of the CP/FT testing method according to any of claims 1 to 5 when executing the computer program.

10. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored thereon a computer program which, when being executed by a processor, carries out the steps of the CP/FT testing method according to any of the claims 1 to 5.