CN105975691A - Method and device for SPI (Serial Peripheral Interface) to automatically regulating sampling phase position - Google Patents
Method and device for SPI (Serial Peripheral Interface) to automatically regulating sampling phase position Download PDFInfo
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- CN105975691A CN105975691A CN201610292396.0A CN201610292396A CN105975691A CN 105975691 A CN105975691 A CN 105975691A CN 201610292396 A CN201610292396 A CN 201610292396A CN 105975691 A CN105975691 A CN 105975691A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
Abstract
The invention provides a method and a device for a SPI (Serial Peripheral Interface) to automatically regulating a sampling phase position. The method comprises the following steps: before a normal work mode is carried out for the first time, adaptive training is carried out on a PCB (Printed Circuit Board), test incentive data is subjected to gating during testing and is transmitted according to the transmission clock frequency of a pre-stored data series, the test incentive data is sent to the data pin port of a main control chip after the test incentive data is delayed by two stages of registers, and then, the test incentive data is transmitted to the data pin of a SPI device through a PCB lead; meanwhile, the data transmission clock of the SPI is output to the clock pin port of the main control chip successively through phase position delay and register delay, and is transmitted to the clock pin of the SPI device via the PCB lead; and the phase position delay and the register delay are controlled until a chip internal phase delay configuration which is optimally matched with the PCB-stage phase delay for the main control chip to use during normal work. The method and the device can achieve optimal clock phase position adaptability under a default situation, can carry out adaptive regulation by aiming at different external circuit boards, and can achieve the optimal matching effect with different PCB electrical conditions.
Description
Technical field
The present invention relates to the design of a kind of SPI clock, automatically adjust sampling phase particularly to a kind of SPI
Method and device.
Background technology
SPI (Serial Peripheral Interface, Serial Peripheral Interface (SPI)) be a kind of high speed, full duplex,
The communication bus synchronized, and on the pin of chip, only take up four lines, save the pin of chip,
It is saving space in the layout of PCB, it is provided that convenient simultaneously, is just being in order at this characteristic easy to use,
Nowadays this communication protocol of increasing integrated chip.
SPI is current conventional data communication interface, is widely used in the communication between various chip, but
Being owing to SPI transmission speed is high, data receiver needs to use the clock received to sample reception simultaneously
The data arrived, so this just has the highest requirement to PCB fabric swatch, need exactissima diligentia clock and data
The track lengths of wire, is the most just otherwise easilying lead to clock that transmitting terminal sends out and data phase
Really, but after PCB trace time delay, arrive receiving terminal, receive clock and reception data phase is sent out
Changing and be unsatisfactory for sampling time sequence requirement, ultimately cause mistake sampling, simultaneously because different chip
SPI output phase place is different, and the SPI interface for different chips needs to design different PCB trace,
The SPI of one piece of circuit board universal adaptation difference chip can not be accomplished, cause the biggest physical resources and manpower
The wasting of resources.
It is to say, at present in the SPI design of chip, the phase place of SPI interface output is fixing, because of
And PCB fabric swatch is had the highest requirement, need the track lengths of exactissima diligentia clock and data conductor,
Otherwise easily lead to clock that transmitting terminal sends out and data phase is incorrect, but through PCB
When arriving receiving terminal after cabling time delay, receive clock and reception data phase changes and is unsatisfactory for adopting
Sample timing requirements, ultimately causes mistake sampling.It is additionally, since the SPI output phase place of different chips not
With, the SPI interface for different chips needs to design different PCB trace, can not accomplish one block of electricity
The SPI of road plate General adaptive difference chip, causes the biggest physical resources and waste of human resource.
Summary of the invention
The technical problem to be solved in the present invention, a kind of method being to provide SPI automatically to adjust sampling phase
And device, optimal clock phase adaptability can be reached in default situations, it is also possible to for different
The external circuit board carries out self-adaptative adjustment, can reach optimal coupling with different PCB electric conditions and imitate
Really.
SPI of the present invention automatically adjusts the method for sampling phase and is achieved in that a kind of SPI adjusts automatically
The method of sampling phase, including:
(1) adaptive training to pcb board before normal mode of operation first, first controls test pattern
Signal is set to effectively；
(2) test stimulus data is strobed, and according to the transfer clock frequency of the data sequence prestored
Send, after two-stage register delay, send the data pin port of main control chip. it is then passed through PCB wire
Transmit the data pin foot to SPI device；Simultaneously
The data transfer clock of SPI exports to main control chip after sequentially passing through Phase delay and register delay
Clock pins port, be then passed through PCB wire transmission to the clock pin foot of SPI device；
(3) by controlling described Phase delay and register delay, until finding optimal coupling pcb board level
The chip internal Phase delay configuration of Phase delay, completes training；
(4), after having trained, main control chip is when normally working, and the optimal delay obtained according to training is joined
Put and carry out SPI data transmission.
Wherein, described step (3) detailed process is as follows:
(31) control described Phase delay and register delay is initial delay configuration；
(32) clock through described Phase delay and register delay is sent to SPI device, then passes through
Isometric data feedback line and Clock feedback lines connect to return clock and data, then use connection to return
Clock and data are sampled and store；
(31) after sampled data reaches designated length, original sequence is read from test stimulus data unit
Row contrast；
If contrast is correct, then shows that the SPI device end sampling on pcb board is no problem, now adapt to instruction
Practicing and terminate, it is invalid that test mode signal is set to, and configures current clock delay as this PCB
The optimal adaptation of plate postpones configuration；
If contrasting incorrect, then control described Phase delay and register delay and postpone configuration for the next one
Training flow process, return to (32) and continue training, so constantly configuration until all configurations terminate or look for
Adaptive training is exited to delay configuration.
Further, described Phase delay includes the Phase delay configuration of 0 degree, 90 degree, 180 degree and 270 degree；
Described register delay includes the register delay configuration of zero level, one-level, two grades and three grades；The most described phase
Position postpones and the delay configuration of register delay includes following several:
Phase delay is configured to 0 degree, and register delay is configured to zero level；
Phase delay is configured to 90 degree, and register delay is configured to zero level；
Phase delay is configured to 180 degree, and register delay is configured to zero level；
Phase delay is configured to 270 degree, and register delay is configured to zero level；
Phase delay is configured to 0 degree, and register delay is configured to one-level；
Phase delay is configured to 90 degree, and register delay is configured to one-level；
Phase delay is configured to 180 degree, and register delay is configured to one-level；
Phase delay is configured to 270 degree, and register delay is configured to one-level；
Phase delay is configured to 0 degree, and register delay is configured to two grades；
Phase delay is configured to 90 degree, and register delay is configured to two grades；
Phase delay is configured to 180 degree, and register delay is configured to two grades；
Phase delay is configured to 270 degree, and register delay is configured to two grades；
Phase delay is configured to 0 degree, and register delay is configured to three grades；
Phase delay is configured to 90 degree, and register delay is configured to three grades；
Phase delay is configured to 180 degree, and register delay is configured to three grades；
Phase delay is configured to 270 degree, and register delay is configured to three grades.
SPI of the present invention automatically adjusts the device of sampling phase and is achieved in that a kind of SPI adjusts automatically
The device of sampling phase, selects unit, two-stage depositor including test stimulus data unit, data path
Delay cell, sample and contrast unit, clock generating unit, phase delay cell, Phase delay path
Select unit, register delay unit, register delay path selection unit and phase place to adjust and control list
Unit；
Described test stimulus data unit, data path select unit, two-stage register delay unit successively
It is connected to the data pin port of main control chip, and is passed through PCB by the data pin port of main control chip
Wire is connected to the data pin foot of SPI device；Described data path selects unit to be also connected with test pattern
Signal；
Described clock generating unit, phase delay cell, Phase delay path selection unit, depositor prolong
Slow unit, register delay path selection unit are sequentially connected to the clock pins port of main control chip, and
It is connected to the clock pin foot of SPI device by PCB wire by main control chip clock pins port；
The data pin foot of described SPI device and clock pin foot draw an isometric data feedback line respectively
It is also respectively connected with inside with Clock feedback lines to described sampling and contrast unit, described sampling and contrast unit
Memorizer, described test stimulus data unit and phase place adjust control unit, and this phase place adjusts control unit
Connect described Phase delay path selection unit and register delay path selection unit the most respectively.
Wherein, before normal mode of operation first, test mode signal is arranged to effective；
Data path selects one-cell switching test stimulus data unit, and test stimulus data unit is according in advance
The transfer clock frequency of the data sequence of storage is sent, and reaches two-stage depositor after path selection unit
The data pin port of main control chip is sent after delay cell. it is then passed through PCB wire transmission to SPI device
Data pin foot；Meanwhile, described clock generating unit is responsible for producing the data transfer clock of SPI in phase place
Postpone under the control of path selection unit and register delay path selection unit, sequentially pass through or without
The clock pins port to main control chip, then warp is exported after phase delay cell and register delay unit
Cross PCB wire transmission to the clock pin foot of SPI device；
Described phase place adjusts control unit by controlling described phase delay cell and register delay unit
Configuration, until finding the chip internal Phase delay configuration of optimal coupling pcb board level Phase delay, for
Main control chip uses when normal work.Specifically:
Described phase place adjusts the control unit described phase delay cell of control and register delay unit is initial
Postpone configuration；
Clock through described phase delay cell and register delay unit is sent to SPI device, then leads to
Cross isometric data feedback line and Clock feedback lines connects to return clock and data to described sampling and contrast list
Unit, the most described sampling and contrast unit use connect the clock returned and data carry out sampling and store to
Described internal storage；
After sampled data reaches designated length, described sampling and contrast unit are from test stimulus data unit
Read original test stimulus data sequence to contrast；
If contrast is correct, then shows that the SPI device end sampling on pcb board is no problem, now adapt to instruction
Practicing and terminate, it is invalid that test mode signal is set to, and configures current clock delay as this PCB
The optimal adaptation of plate postpones configuration；
If contrasting incorrect, then phase place adjusts the control unit described Phase delay of control and depositor prolongs
Being that the next training flow process postponing configuration continues training late, the most constantly configuration is until all configurations terminate
Or find delay configuration to exit adaptive training.
Further, described phase delay cell includes that 90 degree of phase delay cells, 180 degree of phase places are prolonged
Unit and 270 degree of phase delay cells late；Described clock generating unit is passed through directly and respectively by being somebody's turn to do
90 degree of phase delay cells, 180 degree of phase delay cells, 270 degree of phase delay cells connect described phase
Position postpones path selection unit；
Described register delay unit include one-level register delay unit, two-stage register delay cell and
Three grades of register delay unit；Described Phase delay path selection unit respectively by directly and by this one
Level register delay unit, two-stage register delay cell, three grades of register delay unit are posted described in connecting
Storage postpones path selection unit.
Present invention have the advantage that
(1) Danone, to optimal clock phase adaptability, at utmost improves this in default situations
The robustness of body；
(2) self-adaptative adjustment can be carried out for different the external circuit board, can be with different PCB electricity
Gas condition reaches optimal matching effect, can adaptive different circuit board, it is difficult to reduce PCB design
Degree, makes PCB can make General adaptive difference chip simultaneously, man power and material is greatly decreased；
(3) two-stage adjusts circuit cooperating, both can adjust on a large scale, Adjustment precision simultaneously
Can also be the highest.
Accompanying drawing explanation
The present invention is further illustrated the most in conjunction with the embodiments.
Fig. 1 is the structural representation of apparatus of the present invention, and shows that the method for the present invention performs flow process.
Detailed description of the invention
SPI of the present invention automatically adjusts the method for sampling phase and includes:
(1) adaptive training to pcb board before normal mode of operation first, first controls test pattern
Signal is set to effectively；
(2) test stimulus data is strobed, and according to the transfer clock frequency of the data sequence prestored
Send, after two-stage register delay, send the data pin port of main control chip. it is then passed through PCB wire
Transmit the data pin foot to SPI device；Simultaneously
The data transfer clock of SPI exports to main control chip after sequentially passing through Phase delay and register delay
Clock pins port, be then passed through PCB wire transmission to the clock pin foot of SPI device；
(3) by controlling described Phase delay and register delay, until finding optimal coupling pcb board level
The chip internal Phase delay configuration of Phase delay, completes training；
(4), after having trained, main control chip is when normally working, and the optimal delay obtained according to training is joined
Put and carry out SPI data transmission.
Wherein, described step (3) detailed process is as follows:
(31) control described Phase delay and register delay is initial delay configuration；
(32) clock through described Phase delay and register delay is sent to SPI device, then passes through
Isometric data feedback line and Clock feedback lines connect to return clock and data, then use connection to return
Clock and data are sampled and store；
(31) after sampled data reaches designated length, original sequence is read from test stimulus data unit
Row contrast；
If contrast is correct, then shows that the SPI device end sampling on pcb board is no problem, now adapt to instruction
Practicing and terminate, it is invalid that test mode signal is set to, and configures current clock delay as this PCB
The optimal adaptation of plate postpones configuration；
If contrasting incorrect, then control described Phase delay and register delay and postpone configuration for the next one
Training flow process, return to (32) and continue training, so constantly configuration until all configurations terminate or look for
Adaptive training is exited to delay configuration.
Described Phase delay includes the Phase delay configuration of 0 degree, 90 degree, 180 degree and 270 degree；Described deposit
Device postpones to include the register delay configuration of zero level, one-level, two grades and three grades；The most described Phase delay and
The delay configuration of register delay includes following several:
1) Phase delay is configured to 0 degree, and register delay is configured to zero level,
2) Phase delay is configured to 90 degree, and register delay is configured to zero level；
3) Phase delay is configured to 180 degree, and register delay is configured to zero level；
4) Phase delay is configured to 270 degree, and register delay is configured to zero level；
5) Phase delay is configured to 0 degree, and register delay is configured to one-level；
6) Phase delay is configured to 90 degree, and register delay is configured to one-level；
7) Phase delay is configured to 180 degree, and register delay is configured to one-level；
8) Phase delay is configured to 270 degree, and register delay is configured to one-level；
9) Phase delay is configured to 0 degree, and register delay is configured to two grades；
10) Phase delay is configured to 90 degree, and register delay is configured to two grades；
11) Phase delay is configured to 180 degree, and register delay is configured to two grades；
12) Phase delay is configured to 270 degree, and register delay is configured to two grades；
13) Phase delay is configured to 0 degree, and register delay is configured to three grades；
14) Phase delay is configured to 90 degree, and register delay is configured to three grades；
15) Phase delay is configured to 180 degree, and register delay is configured to three grades；
16) Phase delay is configured to 270 degree, and register delay is configured to three grades.
Wherein, Phase delay is configured to 0 degree is to represent to be straight-through without Phase delay, i.e. depositor prolongs
It is for zero level in like manner late.
Control Phase delay configuration and time register delay configures concrete, can be by above-mentioned listed 1) to 16)
Order carry out, but the invention is not restricted to this, it is possible in other orders, most postpone configuration move back until finding
Go out adaptive training.
As it is shown in figure 1, the method that the invention described above SPI adjusts sampling phase automatically can pass through the present invention
SPI automatically adjust the device of sampling phase and realize, this device includes test stimulus data unit
101, data path selects unit 102, two-stage register delay unit 103, samples and contrast unit
104, clock generating unit 105, phase delay cell 106, Phase delay path selection unit 107,
Register delay unit 108, register delay path selection unit 109 and phase place adjust control unit
110；Herein use two-stage register delay unit 103 be in order to allow output data chip in postpone base
Standard is two-stage register time delay, allows well the following register delay unit 108 the delayed selection culture path can
It is 3 grades of less 1 grade or bigger to adjust clock phase, allows register delay path selection unit
The path that postpones of 109 selects have two-way adjustment direction.
Described test stimulus data unit 101, data path select unit 102, two-stage register delay
Unit 103 is sequentially connected to the data pin port A1 of main control chip 100, and by main control chip 100
Data pin port A1 be connected to the data pin foot A2 of SPI device 200 by PCB wire；
Described data path selects unit 102 to be also connected with test mode signal；
Described clock generating unit 105, phase delay cell 106, Phase delay path selection unit
107, register delay unit 108, register delay path selection unit 109 are sequentially connected to master control
The clock pins port B1 of chip 100, and passed through by the clock pins port B1 of main control chip 100
PCB wire is connected to the clock pin foot B2 of SPI device 200；
It is isometric that the data pin foot A2 and clock pin foot B2 of described SPI device 200 draws one respectively
Data feedback line and Clock feedback lines are to described sampling and contrast unit 104, described sampling and contrast unit
104 are also respectively connected with internal storage 111, described test stimulus data unit 101 and phase place adjusts control
Unit 110 processed, this phase place adjusts control unit 110 and connects described Phase delay path selection list the most respectively
Unit 106 and register delay path selection unit 108.
Wherein, flow process is specifically trained:
(1) before normal mode of operation first, test mode signal is arranged to effective；
(2) data path selects unit 102 to gate test stimulus data list when test mode signal is effective
Unit 101, test stimulus data unit 101 is sent according to the transfer clock frequency of the data sequence prestored,
Main control chip is sent after reaching two-stage register delay unit 103 after data path selects unit 102
The data pin port A1. of 100 is then passed through PCB wire transmission to the data pin foot of SPI device 200
A2；
Meanwhile, the data transfer clock that described clock generating unit 105 is responsible for generation SPI leads at Phase delay
Road selects under the control of unit 107 and register delay path selection unit 109, sequentially pass through or without
The clock pins end to main control chip 100 is exported after phase delay cell 106 and register delay unit 108
Mouthful B1, is then passed through PCB wire transmission to the clock pin foot B2 of SPI device 200；
(3) described phase place adjusts control unit 110 by controlling described phase delay cell 106 and depositor
The configuration of delay cell 108, until finding the chip internal phase place of optimal coupling pcb board level Phase delay to prolong
Configuration late, uses when normal work for main control chip 100.Detailed process is as follows:
(31) described phase place adjustment control unit 110 controls described phase delay cell 106 and depositor prolongs
Unit 108 configures for initial delay late, can be i.e. the above-mentioned 1st) to plant, Phase delay is configured to 0 degree, posts
Storage postpones to be configured to the configuration of zero level；
(32) SPI will be sent to through the clock of described phase delay cell 106 and register delay unit 108
Device 200, then connects to return clock and data extremely by isometric data feedback line and Clock feedback lines
Described sampling and contrast unit 104, the most described sampling and contrast unit 104 use and connect the clock of returning
Carry out sampling and storing to described internal storage 111 with data；
(33) after sampled data reaches designated length, described sampling and contrast unit 104 are from test and excitation
Data cell 101 reads original test stimulus data sequence and contrasts；
If the sampling that contrast correctly, then shows the SPI device end on pcb board is no problem, now adapt to
Training terminates, and it is invalid that test mode signal is set to, and configures current clock delay as this PCB
The optimal adaptation of plate postpones configuration；
If contrasting incorrect, then phase place adjustment control unit 110 controls described phase delay cell 106
Be next to postpone configuration (such as the above-mentioned 2nd) and plant configuration with register delay unit 108) training stream
Journey, returns to step (32) and continues training, and the most constantly configuration is until all configurations terminate or find
Postpone configuration and exit adaptive training.
Described phase delay cell 106 includes 90 degree of phase delay cells, 180 degree of phase delay cells
With 270 degree of phase delay cells；Described clock generating unit 105 respectively by directly and by this 90
Degree phase delay cell, 180 degree of phase delay cells, 270 degree of phase delay cells connect described phase place
Postpone path selection unit 107；
It is single that described register delay unit 108 includes that one-level register delay unit, two-stage register postpone
Unit and three grades of register delay unit；Described Phase delay path selection unit passes through directly respectively and passes through
This one-level register delay unit, two-stage register delay cell, three grades of register delay unit connect institute
State register delay path selection unit 109.
In addition, it is necessary to explanation: the method and device of the present invention, need before testing to excited data
Unit 101 is stored in specific Serial No. data for testing；And when PCB design, need at SPI
The clock end (clock pin foot B2) of device 200 and data terminal (data pin foot A2) connect respectively
One isometric Clock feedback lines and isometric data feedback line are to SOC main control chip (the most described main control chip
100), due to needs reflection signal after main control chip 100 sends through PCB wire transmission to SPI
Real phase contrast during the clock pin foot A2 of device 200 and data pin foot B2, so in order to not draw
Enter new phase contrast, it is necessary to allow Clock feedback lines and data feedback line from the clock pin of SPI device 200
Foot B2 and data pin foot A2 arrives the clock feedback of main control chip 100 and receives foot C1 and data feedback
The distance receiving foot D1 is isometric；In like manner, when main control chip 100 designing wiring, constraint to be arranged,
The clock feedback making main control chip 100 receives foot C1 and data feedback reception foot D1 to sampling and contrast
The internal cabling time delay of the main control chip 100 of unit 104 is isometric.
Although the foregoing describing the detailed description of the invention of the present invention, but it is familiar with the technology people of the art
Member should be appreciated that our described specific embodiment is merely exemplary rather than for this
The restriction of bright scope, those of ordinary skill in the art are in the equivalence made according to the spirit of the present invention
Modify and change, all should contain in the scope of the claimed protection of the present invention.
Claims (7)
1. the method that a SPI adjusts sampling phase automatically, it is characterised in that:
(1) adaptive training to pcb board before normal mode of operation first, first controls test pattern
Signal is set to effectively；
(2) test stimulus data is strobed, and according to the transfer clock frequency of the data sequence prestored
Send, after two-stage register delay, send the data pin port of main control chip. it is then passed through PCB wire
Transmit the data pin foot to SPI device；Simultaneously
The data transfer clock of SPI exports to main control chip after sequentially passing through Phase delay and register delay
Clock pins port, be then passed through PCB wire transmission to the clock pin foot of SPI device；
(3) by controlling described Phase delay and register delay, until finding optimal coupling pcb board level
The chip internal Phase delay configuration of Phase delay, completes training；
(4), after having trained, main control chip is when normally working, and the optimal delay obtained according to training is joined
Put and carry out SPI data transmission.
SPI the most according to claim 1 adjusts the method for sampling phase automatically, it is characterised in that:
Described step (3) detailed process is as follows:
(31) control described Phase delay and register delay is initial delay configuration；
(32) clock through described Phase delay and register delay is sent to SPI device, then passes through
Isometric data feedback line and Clock feedback lines connect to return clock and data, then use connection to return
Clock and data are sampled and store；
(33) after sampled data reaches designated length, read original test stimulus data sequence and carry out
Contrast；
If contrast is correct, then shows that the SPI device end sampling on pcb board is no problem, now adapt to instruction
Practicing and terminate, it is invalid that test mode signal is set to, and configures current clock delay as this PCB
The optimal adaptation of plate postpones configuration；
If contrasting incorrect, then control described Phase delay and register delay and postpone configuration for the next one
Training flow process, return to (32) and continue training, so constantly configuration until all configurations terminate or look for
Adaptive training is exited to delay configuration.
SPI the most according to claim 2 adjusts the method for sampling phase automatically, it is characterised in that:
Described Phase delay includes the Phase delay configuration of 0 degree, 90 degree, 180 degree and 270 degree；
Described register delay includes the register delay configuration of zero level, one-level, two grades and three grades；
The delay configuration of the most described Phase delay and register delay includes following several:
Phase delay is configured to 0 degree, and register delay is configured to zero level；
Phase delay is configured to 90 degree, and register delay is configured to zero level；
Phase delay is configured to 180 degree, and register delay is configured to zero level；
Phase delay is configured to 270 degree, and register delay is configured to zero level；
Phase delay is configured to 0 degree, and register delay is configured to one-level；
Phase delay is configured to 90 degree, and register delay is configured to one-level；
Phase delay is configured to 180 degree, and register delay is configured to one-level；
Phase delay is configured to 270 degree, and register delay is configured to one-level；
Phase delay is configured to 0 degree, and register delay is configured to two grades；
Phase delay is configured to 90 degree, and register delay is configured to two grades；
Phase delay is configured to 180 degree, and register delay is configured to two grades；
Phase delay is configured to 270 degree, and register delay is configured to two grades；
Phase delay is configured to 0 degree, and register delay is configured to three grades；
Phase delay is configured to 90 degree, and register delay is configured to three grades；
Phase delay is configured to 180 degree, and register delay is configured to three grades；
Phase delay is configured to 270 degree, and register delay is configured to three grades.
4. a SPI adjusts the device of sampling phase automatically, it is characterised in that: include test and excitation number
Select unit, two-stage register delay unit according to unit, data path, sample and contrast unit, clock
Generation unit, phase delay cell, Phase delay path selection unit, register delay unit, deposit
Device postpones path selection unit and phase place adjusts control unit；
Described test stimulus data unit, data path select unit, two-stage register delay unit successively
It is connected to the data pin port of main control chip, and is passed through PCB by the data pin port of main control chip
Wire is connected to the data pin foot of SPI device；Described data path selects unit to be also connected with test pattern
Signal；
Described clock generating unit, phase delay cell, Phase delay path selection unit, depositor prolong
Slow unit, register delay path selection unit are sequentially connected to the clock pins port of main control chip, and
It is connected to the clock pin foot of SPI device by PCB wire by main control chip clock pins port；
The data pin foot of described SPI device and clock pin foot draw an isometric data feedback line respectively
It is also respectively connected with inside with Clock feedback lines to described sampling and contrast unit, described sampling and contrast unit
Memorizer, described test stimulus data unit and phase place adjust control unit, and this phase place adjusts control unit
Connect described Phase delay path selection unit and register delay path selection unit the most respectively.
SPI the most according to claim 4 adjusts the device of sampling phase automatically, it is characterised in that:
Before normal mode of operation first, test mode signal is arranged to effective；
Data path selects one-cell switching test stimulus data unit, and test stimulus data unit is according in advance
The transfer clock frequency of the data sequence of storage is sent, and reaches two-stage depositor after path selection unit
Send the data pin port of main control chip after delay cell, be then passed through PCB wire transmission to SPI device
Data pin foot；Meanwhile, described clock generating unit is responsible for producing the data transfer clock of SPI in phase place
Postpone under the control of path selection unit and register delay path selection unit, sequentially pass through or without
The clock pins port to main control chip, then warp is exported after phase delay cell and register delay unit
Cross PCB wire transmission to the clock pin foot of SPI device；
Described phase place adjusts control unit by controlling described phase delay cell and register delay unit
Configuration, until finding the chip internal Phase delay configuration of optimal coupling pcb board level Phase delay,
Use when normal work for main control chip.
SPI the most according to claim 5 adjusts the device of sampling phase automatically, it is characterised in that:
Described phase place adjusts control unit by controlling described phase delay cell and register delay unit
Configuration, until finding the chip internal Phase delay of optimal coupling pcb board level Phase delay to configure concrete mistake
Journey is as follows:
Described phase place adjusts the control unit described phase delay cell of control and register delay unit is initial
Postpone configuration；
Clock through described phase delay cell and register delay unit is sent to SPI device, then leads to
Cross isometric data feedback line and Clock feedback lines connects to return clock and data to described sampling and contrast list
Unit, the most described sampling and contrast unit use connect the clock returned and data carry out sampling and store to
Described internal storage；
After sampled data reaches designated length, described sampling and contrast unit are from test stimulus data unit
Read original test stimulus data sequence to contrast；
If contrast is correct, then shows that the SPI device end sampling on pcb board is no problem, now adapt to instruction
Practicing and terminate, it is invalid that test mode signal is set to, and configures current clock delay as this PCB
The optimal adaptation of plate postpones configuration；
If contrasting incorrect, then phase place adjusts the control unit described Phase delay of control and register delay
For the next one postpone the training flow process of configuration continue training, so constantly configuration until all configurations terminate or
Person finds delay configuration to exit adaptive training.
SPI the most according to claim 6 adjusts the device of sampling phase automatically, it is characterised in that:
Described phase delay cell includes 90 degree of phase delay cells, 180 degree of phase delay cells and 270
Degree phase delay cell；Described clock generating unit is passed through directly and respectively by these 90 degree of Phase delay
Unit, 180 degree of phase delay cells, 270 degree of phase delay cells connect the choosing of described Phase delay path
Select unit；
Described register delay unit include one-level register delay unit, two-stage register delay cell and
Three grades of register delay unit；Described Phase delay path selection unit respectively by directly and by this one
Level register delay unit, two-stage register delay cell, three grades of register delay unit are posted described in connecting
Storage postpones path selection unit.
Priority Applications (1)
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| CN107395208A (en) * | 2017-04-19 | 2017-11-24 | 电子科技大学 | Compression sampling structure based on multichannel non-uniform time delay |
| CN108255231A (en) * | 2016-12-28 | 2018-07-06 | 深圳市中兴微电子技术有限公司 | A kind of data sampling method and chip |
| CN109067563A (en) * | 2018-06-28 | 2018-12-21 | 福州瑞芯微电子股份有限公司 | A kind of Ethernet parameter adaptive adjusting method and system |
| CN112924853A (en) * | 2021-04-12 | 2021-06-08 | 湖南国科微电子股份有限公司 | CP/FT test method, device, system, electronic equipment and medium |
| CN113076276A (en) * | 2021-03-18 | 2021-07-06 | 四川和芯微电子股份有限公司 | SDO data phase adjustable SPI slave interface |
| CN113204514A (en) * | 2021-05-29 | 2021-08-03 | 郑州信大捷安信息技术股份有限公司 | Method for improving SPI interface frequency of chip |
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| CN113204514B (en) * | 2021-05-29 | 2022-03-25 | 郑州信大捷安信息技术股份有限公司 | Method for improving SPI interface frequency of chip |
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