CN112908966A - Buried layer alignment mark and manufacturing method thereof, and semiconductor device and manufacturing method thereof - Google Patents
Buried layer alignment mark and manufacturing method thereof, and semiconductor device and manufacturing method thereof Download PDFInfo
- Publication number
- CN112908966A CN112908966A CN202110074700.5A CN202110074700A CN112908966A CN 112908966 A CN112908966 A CN 112908966A CN 202110074700 A CN202110074700 A CN 202110074700A CN 112908966 A CN112908966 A CN 112908966A
- Authority
- CN
- China
- Prior art keywords
- layer
- alignment mark
- semiconductor substrate
- alignment
- buried
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
- H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a buried layer alignment mark and a manufacturing method thereof, and a semiconductor device and a manufacturing method thereof. The alignment mark manufacturing method comprises the following steps: providing a semiconductor substrate; etching the semiconductor substrate alignment mark region to form an alignment groove; forming an interlayer partition layer on the surface of the semiconductor substrate according to the shape of the alignment groove; defining an alignment mark region on the interlayer region layer, and selectively etching to remove the interlayer region layer outside the alignment mark region and on the first surface of the semiconductor substrate; an epitaxial layer is formed by an epitaxial process on the first surface including the alignment mark region and the exposed portion. The buried layer alignment mark is manufactured according to the buried layer alignment mark manufacturing method, the semiconductor device manufacturing method is that a buried layer is manufactured in a substrate according to the buried layer alignment mark, and ion implantation is carried out in an epitaxial layer in alignment with the buried layer. The semiconductor device is manufactured by the semiconductor device manufacturing method.
Description
Technical Field
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a buried layer alignment mark, a manufacturing method of the buried layer alignment mark, a semiconductor device and a manufacturing method of the semiconductor device.
Background
At present, the buried layer technology is widely used in semiconductor processes, such as bipolar semiconductor devices, image sensors, and Bi-CMOS devices.
Taking a bipolar semiconductor device as an example, the collector of the transistor needs to be led out from the bottom layer of the device, so that the series resistance of the collector is increased, which is not favorable for the circuit performance. In order to provide a low resistance path for the current flow to the collector and reduce the series resistance of the collector, a buried layer is usually formed in the substrate of the device in advance, then an epitaxial layer is formed, and the collector aligned with the buried layer is formed in the epitaxial layer. Therefore, in such devices, the buried layer alignment process is critical to the performance of the circuit.
In the related art, an alignment trench is usually formed on a substrate layer as a mark for buried layer implantation, and then an epitaxial layer is formed on the substrate layer according to the topography of the surface of the substrate layer on which the alignment trench is formed, wherein a corresponding groove is formed on the surface of the epitaxial layer corresponding to the alignment trench, and is used for aligning the buried layer when ion implantation is performed on the epitaxial layer.
However, once the width of the alignment trench is narrow, a shallow groove or no groove is formed on the surface of the epitaxial layer at a position corresponding to the narrow alignment trench, which is prone to cause a problem of unclear alignment marks and is not favorable for alignment accuracy.
Disclosure of Invention
The application provides a buried layer alignment mark and a manufacturing method thereof, a semiconductor device and a manufacturing method thereof, and can solve the problems that the alignment mark is not clear and alignment accuracy is not facilitated in the related technology.
In order to solve the above technical problem, an aspect of the present application provides a method for manufacturing a buried layer alignment mark, where the method for manufacturing a buried layer alignment mark includes the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first surface and a second surface which are opposite;
etching to form an alignment groove extending to the second surface on the first surface of the semiconductor substrate alignment mark region;
forming an interlayer partition layer on the first surface of the semiconductor substrate according to the appearance of the first surface of the semiconductor substrate etched with the alignment groove;
defining the alignment mark region on the interlayer region delamination, and selectively etching to remove the interlayer region delamination on the first surface of the semiconductor substrate, which is positioned outside the alignment mark region; exposing the first surface of the semiconductor substrate outside the alignment mark region;
and forming an epitaxial layer on the first surface including the alignment mark area and the exposed part by an epitaxial process.
Optionally, the steps of: forming an interlayer partition layer on the first surface of the semiconductor substrate according to the appearance of the first surface of the semiconductor substrate etched with the alignment groove, comprising:
forming a silicide layer on the first surface of the semiconductor substrate according to the appearance of the first surface of the semiconductor substrate etched with the alignment groove;
forming a polysilicon layer on the silicide layer according to the appearance of the silicide layer; so that the morphology of the polysilicon layer is consistent with the morphology of the silicide layer.
Optionally, the thickness of the silicide layer is 50nm to 200 nm.
Optionally, the thickness of the polysilicon layer is 50nm to 200 nm.
Optionally, the silicide layer includes any one or a combination of a silicon oxide layer and a silicon nitride layer.
Optionally, the depth of the alignment trench extending from the first surface to the second surface of the semiconductor substrate is 100nm to 500 nm.
Optionally, after forming an interlayer region separation layer on the first surface of the semiconductor substrate, in the step: defining an alignment mark region, and selectively etching to remove a layer located outside the alignment mark region, wherein before the layer on the first surface of the semiconductor substrate is processed, the following steps are further performed:
forming a buffer layer on the interlayer region.
Optionally, the thickness of the epitaxial layer is 1um to 5 um.
On the one hand, the buried layer alignment mark is provided and is manufactured by the buried layer alignment mark manufacturing method.
In one aspect, a method for manufacturing a semiconductor device is provided, where the method for manufacturing a semiconductor device includes the above method for manufacturing a buried alignment mark, and in the step: after forming an alignment trench extending to the second surface by etching on the first surface of the semiconductor substrate alignment mark region, in the step: according to the appearance of the first surface of the semiconductor substrate etched with the alignment groove, before forming silicide on the first surface of the semiconductor substrate, the following steps are further performed:
and implanting impurity ions into the semiconductor substrate by taking the alignment groove as an alignment mark to form a buried layer.
After forming the epitaxial layer, further performing:
determining the alignment trench according to the interlayer regional layer;
and taking the alignment groove as an alignment mark, aligning the buried layer in the semiconductor substrate, and implanting impurity ions into the epitaxial layer.
In one aspect, a semiconductor device is provided, which is manufactured by the manufacturing method of the semiconductor device as described above.
The technical scheme at least comprises the following advantages: according to the method, the epitaxial layers are formed on the alignment mark region with the interlayer region layering and the exposed first surface of the semiconductor substrate, even if the alignment groove in the alignment mark region is narrow, the alignment groove can be filled in the process of forming the epitaxial layer; however, since the interlayer spacer comprises a material having a different refractive index than both the substrate and the epitaxial layer, an optical spacer is formed at the interlayer spacer position during the optical alignment process. And the appearance of the interlayer regional layer at the position of the alignment mark region is consistent with that of the alignment mark region, so that the interlayer regional layer can strengthen the identification degree of the alignment groove in the optical alignment process.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 shows a flowchart of a method for fabricating a buried layer alignment mark according to an embodiment of the present application;
fig. 1a to fig. 1f show a schematic cross-sectional structure diagram of a device after completion of each step in a process of manufacturing a buried layer alignment mark according to an embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Fig. 1 shows a flowchart of a method for manufacturing a buried alignment mark according to an embodiment of the present application, and referring to fig. 1, the method for manufacturing a buried alignment mark includes the following steps:
step S11: providing a semiconductor substrate; the semiconductor substrate includes opposing first and second surfaces.
The semiconductor substrate may be a doped silicon substrate. Fig. 1a schematically shows a semiconductor substrate structure provided in the present application, and referring to fig. 1a, a first surface 11 of the semiconductor substrate 10 in this embodiment is an upper surface of the semiconductor substrate 10, and a second surface 12 of the semiconductor substrate 10 is a lower surface of the semiconductor substrate 10.
Step S12: and etching to form an alignment groove extending to the second surface on the first surface of the semiconductor substrate alignment identification area.
The alignment mark region of the semiconductor substrate can be located in a scribing groove of the semiconductor substrate, and the depth of the alignment groove extending from the first surface to the second surface of the semiconductor substrate is 100nm to 500 nm.
Referring to fig. 1b, which shows a schematic cross-sectional structure of the device after step S12 is completed, after step S12 is completed, the alignment trench 13 formed in the alignment mark region 14 extends from the first surface 11 of the semiconductor substrate 10 to the second surface 12 of the semiconductor substrate 10.
Step S13: forming an interlayer partition layer on the first surface of the semiconductor substrate according to the appearance of the first surface of the semiconductor substrate etched with the alignment groove; so that the topography of the interlayer region is consistent with the topography of the first surface of the semiconductor substrate.
In this embodiment, the interlayer region layer includes a silicide having a refractive index different from that of the semiconductor substrate, and the silicide may be silicon nitride or silicon oxide, or a composite layer of a silicon nitride layer and a silicon oxide layer; therefore, when optical alignment is carried out, reflection boundary is formed at the surface position of the alignment groove so as to enhance the alignment mark and be beneficial to the alignment accuracy.
Polysilicon can be formed on the silicide through deposition or growth, and because the lattice structure of the silicide is different from that of silicon, the formation of the polysilicon layer on the silicide is beneficial to the growth of an epitaxial layer in the subsequent steps.
Optionally, the thickness of the silicide layer is 50nm to 200nm, and the thickness of the polysilicon layer is 50nm to 200 nm.
Referring to fig. 1c, which shows a schematic cross-sectional structure of the device after step S13 is completed, the interlayer isolation layer 15 includes a silicide layer 151 and a polysilicon layer 152 stacked in sequence. Step S13 includes: forming a silicide layer 151 on the first surface of the semiconductor substrate 10 according to the topography of the first surface of the semiconductor substrate 10 etched with the alignment trench; forming a polysilicon layer 152 on the silicide layer 151 according to the profile of the silicide layer 151; so that the topography of the polysilicon layer 152 conforms to the topography of the silicide layer 152.
In other embodiments, a buffer layer may be formed on the interlayer isolation layer to buffer stress.
Step S14: defining the alignment mark region on the interlayer region delamination, and selectively etching to remove the interlayer region delamination on the first surface of the semiconductor substrate, which is positioned outside the alignment mark region; exposing the first surface of the semiconductor substrate outside the alignment mark region.
In this embodiment, fig. 1e is a schematic cross-sectional structure diagram of the device after step S14 is completed. Fig. 1d shows the structure of the device surface after step S13 is completed, where the alignment mark region is defined by photoresist. Referring to fig. 1d, an alignment mark region 14 is defined on the interlayer insulating layer 15 using a photoresist 20 as a mask layer. The interlayer isolation layer 15 on the first surface of the semiconductor substrate 10, which is located outside the alignment mark region 14, is selectively etched away by a wet etching process or a dry etching process, so that the remaining interlayer isolation layer 15 is located at the alignment mark region 14, and the structure shown in fig. 1e is formed.
Step S15: and forming an epitaxial layer on the first surface including the alignment mark area and the exposed part by an epitaxial process.
Referring to fig. 1f, a schematic cross-sectional structure of the device after step S15 is completed is shown. An epitaxial layer 20 is formed overlying the substrate including the alignment mark region 14 and the exposed first surface. In this embodiment, the thickness of the epitaxial layer may be 1um to 5 um.
As described in the background art, in the related art, if the alignment trench is narrow, after the epitaxial layer is formed, the mark trench at the corresponding position on the surface of the epitaxial layer is not obvious, and it is difficult to ensure the alignment accuracy.
By the embodiment, the epitaxial layers are formed on the alignment mark region formed with the interlayer region layer and the exposed first surface of the semiconductor substrate, even if the alignment groove in the alignment mark region is narrow, the alignment groove can be filled in the process of forming the epitaxial layer; however, since the interlayer spacer comprises a material having a different refractive index than both the substrate and the epitaxial layer, an optical spacer is formed at the interlayer spacer position during the optical alignment process. And the appearance of the interlayer regional layer at the position of the alignment mark region is consistent with that of the alignment mark region, so that the interlayer regional layer can strengthen the identification degree of the alignment groove in the optical alignment process.
According to the method for fabricating the buried alignment mark shown in fig. 1, the buried alignment mark shown in fig. 1f is fabricated, and referring to fig. 1f, the alignment mark includes an alignment trench formed in an alignment mark region 14 of a semiconductor substrate 10, and an interlayer region delamination 15 is covered according to the topography of the alignment mark region 14.
In the embodiment, the epitaxial layer is formed on the alignment mark region formed with the interlayer region layer and the exposed first surface of the semiconductor substrate, even if the alignment groove in the alignment mark region is narrow, the alignment groove can be filled in the process of forming the epitaxial layer; however, since the interlayer spacer comprises a material having a different refractive index than both the substrate and the epitaxial layer, an optical spacer is formed at the interlayer spacer position during the optical alignment process. And the appearance of the interlayer regional layer at the position of the alignment mark region is consistent with that of the alignment mark region, so that the interlayer regional layer can strengthen the identification degree of the alignment groove in the optical alignment process.
In an embodiment of the present application, on the basis of the buried layer alignment mark manufacturing method shown in fig. 1, after step S12 is completed and before step S13 is performed, the method for manufacturing a semiconductor device includes: and implanting impurity ions into the semiconductor substrate by taking the alignment groove as an alignment mark to form a buried layer. After the epitaxial layer is formed in step S15, the step of: determining the alignment trench according to the interlayer regional layer; and taking the alignment groove as an alignment mark, aligning the buried layer in the semiconductor substrate, and implanting impurity ions into the epitaxial layer.
In this embodiment, before the epitaxial layer is formed, a buried layer is formed in the semiconductor substrate according to the alignment trench, and after the epitaxial layer is formed, the alignment trench can be determined according to the interlayer dividing layer to perform ion implantation to the buried layer, so that the requirement of alignment accuracy between two times of ion implantation can be improved, and the alignment problem caused by unclear alignment marks can be avoided.
An embodiment of the present application further provides a semiconductor device manufactured according to the manufacturing method of the semiconductor device.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (11)
1. A buried layer alignment mark manufacturing method is characterized by comprising the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first surface and a second surface which are opposite;
etching to form an alignment groove extending to the second surface on the first surface of the semiconductor substrate alignment mark region;
forming an interlayer partition layer on the first surface of the semiconductor substrate according to the appearance of the first surface of the semiconductor substrate etched with the alignment groove;
defining the alignment mark region on the interlayer region delamination, and selectively etching to remove the interlayer region delamination on the first surface of the semiconductor substrate, which is positioned outside the alignment mark region; exposing the first surface of the semiconductor substrate outside the alignment mark region;
and forming an epitaxial layer on the first surface including the alignment mark area and the exposed part by an epitaxial process.
2. The buried layer alignment mark fabrication method of claim 1, wherein the step of: forming an interlayer partition layer on the first surface of the semiconductor substrate according to the appearance of the first surface of the semiconductor substrate etched with the alignment groove, comprising:
forming a silicide layer on the first surface of the semiconductor substrate according to the appearance of the first surface of the semiconductor substrate etched with the alignment groove;
forming a polysilicon layer on the silicide layer according to the appearance of the silicide layer; so that the morphology of the polysilicon layer is consistent with the morphology of the silicide layer.
3. The method for fabricating a buried alignment mark according to claim 2, wherein the silicide layer has a thickness of 50nm to 200 nm.
4. The buried alignment mark fabrication method of claim 2, wherein the polysilicon layer has a thickness of 50nm to 200 nm.
5. The method for fabricating a buried alignment mark according to claim 1, wherein the silicide layer comprises any one or a combination of a silicon oxide layer and a silicon nitride layer.
6. The buried alignment mark fabrication method of claim 1, wherein the alignment trench extends from the first surface to the second surface of the semiconductor substrate to a depth of 100nm to 500 nm.
7. The buried alignment mark fabrication method of claim 1, wherein, after the inter-layer formation on the first surface of the semiconductor substrate is performed, at the step of: defining an alignment mark region, and selectively etching to remove a layer located outside the alignment mark region, wherein before the layer on the first surface of the semiconductor substrate is processed, the following steps are further performed:
forming a buffer layer on the interlayer region.
8. The method for fabricating a buried alignment mark according to claim 1, wherein the thickness of the epitaxial layer is 1um to 5 um.
9. A buried layer alignment mark, wherein the buried layer alignment mark is manufactured by the method for manufacturing a buried layer alignment mark according to any one of claims 1 to 8.
10. A method for manufacturing a semiconductor device, wherein the method for manufacturing the semiconductor device comprises the method for manufacturing the buried alignment mark according to any one of claims 1 to 8, and in the step: after forming an alignment trench extending to the second surface by etching on the first surface of the semiconductor substrate alignment mark region, in the step: according to the appearance of the first surface of the semiconductor substrate etched with the alignment groove, before forming silicide on the first surface of the semiconductor substrate, the following steps are further performed:
and implanting impurity ions into the semiconductor substrate by taking the alignment groove as an alignment mark to form a buried layer.
After forming the epitaxial layer, further performing:
determining the alignment trench according to the interlayer regional layer;
and taking the alignment groove as an alignment mark, aligning the buried layer in the semiconductor substrate, and implanting impurity ions into the epitaxial layer.
11. A semiconductor device characterized by being manufactured by the manufacturing method of a semiconductor device according to claim 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110074700.5A CN112908966A (en) | 2021-01-20 | 2021-01-20 | Buried layer alignment mark and manufacturing method thereof, and semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110074700.5A CN112908966A (en) | 2021-01-20 | 2021-01-20 | Buried layer alignment mark and manufacturing method thereof, and semiconductor device and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112908966A true CN112908966A (en) | 2021-06-04 |
Family
ID=76116583
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110074700.5A Pending CN112908966A (en) | 2021-01-20 | 2021-01-20 | Buried layer alignment mark and manufacturing method thereof, and semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112908966A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023130805A1 (en) * | 2022-01-07 | 2023-07-13 | 长鑫存储技术有限公司 | Semiconductor device and preparation method therefor |
| CN117423613A (en) * | 2023-12-19 | 2024-01-19 | 荣芯半导体(淮安)有限公司 | Epitaxial wafer and manufacturing method thereof, and manufacturing method of semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020028528A1 (en) * | 2000-09-01 | 2002-03-07 | Shiro Ohtaka | Alignment marks and method of forming the same |
| CN102129178A (en) * | 2010-01-18 | 2011-07-20 | 上海华虹Nec电子有限公司 | Photoetching mark structure for SiGeC device |
-
2021
- 2021-01-20 CN CN202110074700.5A patent/CN112908966A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020028528A1 (en) * | 2000-09-01 | 2002-03-07 | Shiro Ohtaka | Alignment marks and method of forming the same |
| CN102129178A (en) * | 2010-01-18 | 2011-07-20 | 上海华虹Nec电子有限公司 | Photoetching mark structure for SiGeC device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023130805A1 (en) * | 2022-01-07 | 2023-07-13 | 长鑫存储技术有限公司 | Semiconductor device and preparation method therefor |
| CN117423613A (en) * | 2023-12-19 | 2024-01-19 | 荣芯半导体(淮安)有限公司 | Epitaxial wafer and manufacturing method thereof, and manufacturing method of semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112908966A (en) | Buried layer alignment mark and manufacturing method thereof, and semiconductor device and manufacturing method thereof | |
| KR0178823B1 (en) | Method of making a semiconductor device with alignment marks | |
| EP0782185A2 (en) | Process of fabricating semiconductor device having isolating oxide rising out of groove | |
| US7470589B2 (en) | Semiconductor device | |
| JP2010003970A (en) | Manufacturing method of semiconductor device | |
| CN115863159A (en) | Semiconductor device manufacturing method | |
| JP2002134701A (en) | Method for manufacturing semiconductor device | |
| US8268688B2 (en) | Production of VDMOS-transistors having optimized gate contact | |
| US8017511B2 (en) | Method of manufacturing semiconductor device | |
| US20070298584A1 (en) | Method for fabricating semiconductor device | |
| CN112908916A (en) | Buried layer alignment mark and manufacturing method thereof | |
| JP2012199468A (en) | Method of manufacturing semiconductor device | |
| CN113594042A (en) | Manufacturing method of MOSFET | |
| US20050250259A1 (en) | SOI-type semiconductor device, and production method for manufacturing such SOI-type semiconductor device | |
| CN113937056A (en) | Semiconductor device and method for manufacturing the same | |
| KR100558201B1 (en) | Photo align key and method for manufacturing semiconductor device having the same | |
| CN112259567A (en) | Method for forming microlens of CIS | |
| KR20080057178A (en) | Method for manufacturing a semiconductor device | |
| KR20050002443A (en) | Manufacturing method for semiconductor device | |
| CN111725305B (en) | Semiconductor device and method for manufacturing the same | |
| CN110739273B (en) | Manufacturing method of ultra-thin grid CMOS device | |
| JP5248905B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP3164381B2 (en) | Method for manufacturing semiconductor device | |
| TW200419699A (en) | Process for integrating alignment and trench device | |
| US20210384059A1 (en) | Semiconductor device and method of fabrication the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210604 |