CN117423613A - Epitaxial wafer and manufacturing method thereof, and manufacturing method of semiconductor device - Google Patents
Epitaxial wafer and manufacturing method thereof, and manufacturing method of semiconductor device Download PDFInfo
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- CN117423613A CN117423613A CN202311744096.8A CN202311744096A CN117423613A CN 117423613 A CN117423613 A CN 117423613A CN 202311744096 A CN202311744096 A CN 202311744096A CN 117423613 A CN117423613 A CN 117423613A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
The invention provides an epitaxial wafer, a manufacturing method thereof and a manufacturing method of a semiconductor device. The amorphous epitaxial layer is formed in the edge area of the amorphous substrate wafer, the crystallized epitaxial layer is formed in the area (the central area except the edge area) of the crystallized substrate wafer, the occurrence probability of slip dislocation defects on the epitaxial wafer can be reduced, the physical performance of the epitaxial wafer can be improved, the leakage path generated by the slip dislocation defects can be further reduced, and the device performance and the yield based on the epitaxial wafer are improved.
Description
Technical Field
The present invention relates to the field of semiconductor device manufacturing technologies, and in particular, to an epitaxial wafer, a manufacturing method thereof, and a manufacturing method of a semiconductor device.
Background
At present, in various manufacturing scenes of semiconductor devices, an epitaxial growth process is often adopted, and epitaxial layers which are the same as the substrate wafer in crystal orientation and different in resistivity and structure are grown on the substrate wafer, so that the epitaxial wafer is manufactured.
However, in the existing epitaxial wafer manufacturing technology, slip dislocation (Slip Dislocation or Slip Line Faults) defects are easily generated on the epitaxial wafer by high temperature processes such as rapid thermal annealing, and as clearly seen under a microscope, the slip dislocation defects often are linear defects (also called slip line defects), which extend from the crystal edge of the wafer to the center of the wafer, and a distinct boundary exists between the portion of the wafer where the slip dislocation defects are generated and the portion where the slip dislocation defects are not generated. And as the high temperature process proceeds, the slip dislocation defects further worsen (e.g., further toward the center of the wafer). The slip dislocation defect causes the following problems:
(1) The physical properties, especially mechanical properties and optical properties, of the wafer are deteriorated, and the wafer has great adverse effects;
(2) Affecting Alignment (Alignment) and Overlay (Overlay) accuracy of subsequent photolithography processes;
(3) The slip dislocation defects may cause leakage paths along grain boundaries, which may cause semiconductor devices formed on the wafer to have significant leakage currents, thereby causing performance degradation of the semiconductor devices;
(4) The slip dislocation defects create paths that enhance diffusion, deviate photolithography from registration, attract impurities to unwanted sites, and act as sites for dislocation generation to reduce device yield.
Disclosure of Invention
The invention aims to provide an epitaxial wafer, a manufacturing method thereof and a manufacturing method of a semiconductor device, which can reduce the probability of occurrence of slip dislocation defects in the epitaxial wafer.
In order to achieve the above object, the present invention provides a method for manufacturing an epitaxial wafer, comprising the steps of:
providing a substrate wafer with at least surface crystallization and defining an edge area of the substrate wafer;
amorphizing a defined edge area surface of the substrate wafer;
an epitaxial layer is formed on the substrate wafer to form an epitaxial wafer, and the epitaxial layer in an edge region of the epitaxial wafer is amorphized and the epitaxial layer in the remaining regions is crystallized.
Optionally, the step of defining an edge region of the substrate wafer includes: and gluing and baking the substrate wafer, and exposing the edge area of the substrate wafer by a photomask or adopting a wafer edge exposure method.
Optionally, the width of the edge region of the substrate wafer is less than or equal to 5cm; and/or the amorphization thickness of the edge area surface of the substrate wafer is less than or equal to 10 μm.
Optionally, the edge region surface of the substrate wafer is amorphized by a combination of one or more of ion implantation, ion thermal diffusion, surface carbonization, surface oxidation, and surface metallization.
Optionally, at least one impurity ion including N-type impurity ions and P-type impurity ions is doped into the surface layer of the edge region of the substrate wafer by ion implantation or ion thermal diffusion to amorphize the surface of the edge region of the substrate wafer.
Optionally, the N-type impurity ions comprise at least one of arsenic, antimony and phosphorus; and/or the P-type impurity ions comprise at least one of boron, indium and gallium; and/or the metallization ions comprise at least one of aluminum, tungsten, copper, manganese, chromium.
Optionally, the doping concentration of the impurity ions is 1E12atoms/cm2 to 1E15atoms/cm2.
Optionally, the implantation energy of the impurity ions is 1mev to 10mev.
Optionally, the method for manufacturing an epitaxial wafer further includes, before defining the edge region of the substrate wafer:
covering a mask layer on the substrate wafer;
etching the mask layer and a part of the thickness of the substrate wafer to form a zero-layer optical alignment structure with a groove in the substrate wafer;
removing the mask layer;
and when an epitaxial layer is formed on the substrate wafer, the epitaxial layer also covers the grooves in a conformal manner to form a new zero-layer optical alignment structure in a conformal manner.
Based on the same inventive concept, the present invention also provides an epitaxial wafer comprising a substrate wafer and an epitaxial layer formed on the substrate wafer, wherein the surface of the substrate wafer in an edge region of the epitaxial wafer and the epitaxial layer are both amorphized, and the surface of the substrate wafer and the epitaxial layer in the remaining regions are both crystallized.
Optionally, the width of the edge region of the substrate wafer is less than or equal to 5cm.
Optionally, the amorphized surface of the edge region of the substrate wafer contains one or more of N-type impurity ions, P-type impurity ions, oxygen elements, carbon elements, nitrogen elements, and metal elements.
Optionally, the amorphized thickness of the edge area surface of the substrate wafer is less than or equal to 10 μm.
Based on the same inventive concept, the present invention also provides a method of manufacturing a semiconductor device, comprising:
providing an epitaxial wafer by adopting the manufacturing method of the epitaxial wafer;
and forming a required device structure on the crystallized epitaxial layer of the epitaxial wafer.
Based on the same inventive concept, the present invention also provides a method of manufacturing a semiconductor device, comprising:
providing an epitaxial wafer by adopting the manufacturing method of the epitaxial wafer;
and forming a required device structure on the crystallized epitaxial layer of the epitaxial wafer.
Compared with the prior art, the technical scheme of the invention is that the surface of the edge area of the substrate wafer is amorphized, and then the epitaxial layer is epitaxially grown on the substrate wafer to form the epitaxial wafer. In the epitaxial growth process, an amorphous epitaxial layer is formed on the edge area of the amorphous substrate wafer, a crystallized epitaxial layer is formed on the area (the central area except the edge area) of the crystallized substrate wafer, and the epitaxial growth rate on the edge area of the wafer is slower than that on the central area of the wafer, and the stress generated in the epitaxial growth process on the edge area of the wafer is relatively smaller, so that the occurrence probability of slip dislocation defects on the epitaxial wafer can be reduced, the physical performance of the epitaxial wafer can be improved, the leakage path generated by the slip dislocation defects can be further reduced, and the performance and the yield of devices manufactured based on the epitaxial wafer are improved.
In addition, before the epitaxial layer is formed, a zero-layer optical alignment structure is formed in the substrate wafer, and after the epitaxial layer is formed, a new zero-layer optical alignment structure is formed based on the zero-layer optical alignment structure, so that alignment and alignment precision of a subsequent photoetching process in the process of manufacturing a device based on the epitaxial wafer can be improved.
Drawings
Those of ordinary skill in the art will appreciate that the figures are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention. Wherein:
fig. 1 is a flow chart of a method for manufacturing an epitaxial wafer according to an embodiment of the invention.
Fig. 2 is a schematic cross-sectional view of a device in a method of manufacturing an epitaxial wafer according to an embodiment of the present invention.
Fig. 3 is a schematic cross-sectional view of a semiconductor device in a method of manufacturing the semiconductor device according to an embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without one or more of these details. In other instances, well-known features have not been described in detail in order to avoid obscuring the invention. It should be understood that the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout. It will be understood that when an element is referred to as being "connected to," "coupled to" another element, it can be directly connected to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" another element, there are no intervening elements present. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
The technical scheme provided by the invention is further described in detail below with reference to the attached drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Referring to fig. 1, an embodiment of the present invention provides a method for manufacturing an epitaxial wafer, which includes the following steps:
s1, providing a substrate wafer with at least surface crystallized, and covering a mask layer on the substrate wafer;
s2, etching the mask layer and the substrate wafer with partial thickness to form a groove-shaped zero-layer optical alignment structure in the substrate wafer;
s3, removing the mask layer;
s4, gluing and baking are carried out on the surface of the substrate wafer, and the edge area of the wafer is exposed to define the edge area of the substrate wafer;
s5, amorphizing the surface of the edge area of the defined substrate wafer;
and S6, removing the photoresist on the substrate wafer, and forming an epitaxial layer on the substrate wafer to form an epitaxial wafer, wherein the epitaxial layer in the edge area of the epitaxial wafer is amorphized, and the epitaxial layer in the other areas is crystallized.
In step S1, referring to fig. 2 (a), first, at least a surface crystallized substrate wafer 100 may be any suitable semiconductor wafer, such as a monocrystalline silicon wafer, a silicon-on-insulator (SOI) wafer, a silicon-germanium wafer, or a group iii-v element compound wafer, etc., and the surface (or surface layer) of the substrate wafer 100 is crystallized and may be doped with a concentration of N-type impurity ions or P-type impurity ions, and then the concentration of N-type impurity ions or P-type impurity ions doped into the edge region surface of the substrate wafer 100 in step S5 is sufficiently high (above the amorphization threshold) to amorphize the edge region surface of the substrate wafer 100. A mask layer 101 is deposited over the substrate wafer 100 by any suitable process, such as thermal Oxidation (Thermal Oxidation), wet Oxidation (Wet Oxidation), in situ vapor generation (ISSG), chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), sputtering (Sputtering), and the like. In an example, the mask layer 101 can be a hard mask material (hard mask film stack) that can include one or a combination of at least two of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, amorphous carbon, and the like. The mask layer 101 may be a film structure formed by stacking a hard mask material and a soft mask material, and may include a soft mask material such as a photoresist.
In step S2, please refer to (B) in fig. 2, an appropriate patterning process may be selected to pattern the mask layer 101 according to the material of the mask layer 101, so as to form a pattern of the desired zero-layer optical alignment structure in the mask layer 101. As an example, the mask layer 101 is a hard mask material, and a first patterned photoresist layer (not shown) is formed on the mask layer 101 through a photolithography process. Then, the mask layer 101 and a portion of the thickness of the substrate wafer 100 are etched using the first patterned photoresist layer as a mask, thereby forming a zero layer optical alignment structure having grooves 102 in the substrate wafer 100. The first patterned photoresist layer is then removed.
It should be understood that the location and shape of the zero layer optical alignment structure with grooves 102, etc. are designed as desired, and the invention is not limited in detail. As an example, a zero layer optical alignment structure with grooves 102 is formed on one side of the substrate wafer 100 within and at a distance from the inside of the edge region of the substrate wafer 100 to be amorphized.
In step S3, please refer to fig. 2 (B) and (C), any suitable process is selected to remove the mask layer 101 according to the material of the mask layer 101, so as to re-expose the global surface of the substrate wafer 100 with the zero-layer optical alignment structure. The mask layer 101 is removed, for example, by a wet etching process.
In step S4, please refer to (C) in fig. 2, first, a photoresist layer 200 is formed by applying a photoresist layer (e.g. spin coating) on the substrate wafer 100 and baking, wherein the photoresist layer 200 may fill the recess 102 and have a flat upper surface; then, the photoresist layer 200 is exposed (i.e., only the photoresist on the edge area of the substrate wafer 100 is exposed using an edge exposure apparatus without using a photomask) using a wafer edge exposure method (wafer edge exposure, WEE); thereafter, the exposed portions of the photoresist layer 200 are removed (i.e., the edge regions of the photoresist layer 200 are removed) by a developing process, thereby defining edge regions 100a of the substrate wafer 100 to be surface amorphized, and the portions of the substrate wafer 100 other than the edge regions 100a may be referred to as a central region 100b (or as a device region) of the substrate wafer.
In other embodiments of the present invention, the edge region 100a of the substrate wafer 100 may be further defined by a mask in step S4. For example, referring to fig. 2 (C), first, a positive photoresist is coated on the substrate wafer 100 and baked to form a photoresist layer 200, wherein the photoresist layer 200 may fill the recess 102 and have a flat upper surface; then, a mask is used to block the central region 100b of the substrate wafer 100, and the photoresist on the exposed region of the mask (i.e. the edge region 100a of the substrate wafer 100) is exposed; the exposed portions of the photoresist layer 200 are then removed (i.e., the edge regions of the photoresist layer 200 are removed) by a development process, thereby defining edge regions 100a of the substrate wafer 100 to be surface amorphized. For another example, referring to fig. 2 (C), first, a negative photoresist is coated on a substrate wafer 100 and baked to form a photoresist layer 200, wherein the photoresist layer 200 may fill the recess 102 and have a flat upper surface; then, a mask is used to block the edge area 100a of the substrate wafer 100, and the photoresist on the exposed area of the mask (i.e. the central area 100b of the substrate wafer 100) is exposed; thereafter, the unexposed portions of the photoresist layer 200 are removed (i.e., the edge regions of the photoresist layer 200 are removed) by a development process, thereby defining edge regions 100a of the substrate wafer 100 to be surface amorphized.
As an example, the width W of the edge region 100a of the substrate wafer 100 (i.e., the width of the amorphized region 103) is less than or equal to 5cm. Further, the width W may be less than or equal to 3 μm, thereby making the area of the subsequently formed epitaxial layer as large as possible while avoiding slip dislocation defects in the edge region as much as possible.
In step S5, please continue to refer to (C) in fig. 2, under the masking effect of the photoresist layer 200, the surface of the edge region 100a of the substrate wafer 100 may be amorphized by one or more of ion implantation, ion thermal diffusion, doping of the wafer surface, surface carbonization, surface oxidation, and surface metallization, so as to convert the surface layer of the edge region 100a of the substrate wafer 100 with a thickness H into the amorphized region 103. After the surface amorphization of the edge region 100a of the substrate wafer 100 is completed, the photoresist layer 200 may be removed by any suitable process, such as a dry photoresist removal process or a wet photoresist removal process, to re-expose the surface of the central region 100b of the substrate wafer 100, ready for subsequent epitaxial layer formation.
Wherein the ions or elements that cause amorphization of the surface of the edge region 100a of the substrate wafer 100 include one or more of N-type impurity ions, P-type impurity ions, oxygen elements, carbon elements, nitrogen elements, and metal elements, i.e., the amorphized region 103 includes one or more of N-type impurity ions, P-type impurity ions, oxygen elements, carbon elements, nitrogen elements, and metal elements.
As an example, please continue to refer to (C) in fig. 2, in step S5, the photoresist layer 200 is used as a mask, and one or more of N-type impurity ions, P-type impurity ions, oxygen ions, carbon ions, nitrogen ions, and metal ions are used to perform ion implantation on the exposed edge region 100a of the substrate wafer 100, where parameters such as energy and dose of the ion implantation are set to an extent that the surface of the edge region 100a of the substrate wafer 100 is amorphized. Thereby, the surface of the edge region 100a of the substrate wafer 100 is amorphized, i.e., the surface layer of the edge region 100a of the substrate wafer 100 having a thickness H is converted into an amorphized region 103. The amorphized region 103 is used to amorphize (also known as amorphous) the epitaxial layer on the wafer edge during a subsequent epitaxial growth process. When the substrate wafer 100 is monocrystalline silicon, the amorphized region 103 is amorphous silicon (α -Si).
In the present example step S5, the implantation depth (i.e., the amorphization thickness H) is deeper (e.g., up to 5 μm) as the implantation energy is larger when implanting impurity ions into the edge region 100a of the substrate wafer 100. Optionally, in the step S5, the implantation energy when implanting the impurity ions into the surface layer of the edge region 100a of the substrate wafer 100 is 1mev to 10mev, so as to implant the impurity ions to a proper depth of the surface layer of the edge region 100a of the substrate wafer 100. Preferably, the implantation energy when implanting impurity ions into the surface layer of the edge region 100a of the substrate wafer 100 is 2MeV to 5MeV (may be 3MeV or 4 MeV), so that the implantation depth of the impurity ions into the surface layer of the edge region 100a of the substrate wafer 100 can reach 1 μm to 3 μm.
In this example step S5, impurity ions may be heavily doped when implanting into the edge region 100a of the substrate wafer 100, thereby causing a sufficient degree of amorphization in that region. Optionally, the impurity ions (used to form the amorphized region 103) doped into the surface of the edge region 100a of the substrate wafer 100 have a doping concentration of 1E12atoms/cm 2 ~1E15atoms/cm 2 (may be 5E12 atoms/cm) 2 、1E13 atoms/cm 2 、5E13atoms/cm 2 、1E14atoms/cm 2 、5E14atoms/cm 2 Etc.), thereby inducing a sufficient degree of amorphization in the surface layer of the edge region 100a of the substrate wafer 100 at the corresponding implantation depth.
Optionally, N-type impurity ions (for forming the amorphized region 103) doped to the surface of the edge region 100a of the substrate wafer 100 include at least one of arsenic (As), antimony (Sb), and phosphorus (P).
Optionally, P-type impurity ions (for forming the amorphized region 103) doped to the surface of the edge region 100a of the substrate wafer 100 include at least one of boron (B), indium (In), and gallium (Ga).
In another example, in step S5, one or more of N-type impurity ions, P-type impurity ions, oxygen ions, carbon ions, nitrogen ions, and metal ions may be doped into the surface of the edge region 100a of the substrate wafer 100 by an ion thermal diffusion method (i.e., an ion doping process different from ion implantation) under the masking effect of the photoresist layer 200, so as to amorphize the surface of the edge region 100a of the substrate wafer 100.
Optionally, the amorphized thickness H of the surface of the edge area 100a of the substrate wafer 100 (i.e., the thickness of the amorphized regions 103) is less than or equal to 10 μm. Further, the amorphization thickness H may be less than or equal to 5 μm, thereby avoiding excessive implantation energy required to increase implantation costs.
In step S6, please refer to (E) in fig. 2, an Epitaxial layer is formed on the surface of the substrate wafer 100 by any suitable process such as an Epitaxial growth process (epi-axial growth), thereby obtaining an Epitaxial wafer. Wherein the epitaxial layer 105 in the edge region of the epitaxial wafer is amorphized and the epitaxial layer 104 in the remaining region (i.e., the central region within the edge region) is crystallized. I.e., epitaxial layer 104 and epitaxial layer 105, together comprise an epitaxial layer on substrate wafer 100. When the epitaxial layer 104 is monocrystalline silicon, the epitaxial layer 105 is amorphous silicon (α -Si). As an example, epitaxial layers 104, 105 are epitaxially grown on the surface of substrate wafer 100 at a temperature greater than 1100 ℃ to increase the growth rate and uniformity of the epitaxial layers.
In addition, epitaxial layer 104 is conformal, so it covers and fills recess 102 of the zero-layer optical alignment structure, and a new optical alignment structure with recess 106 is conformal at recess 102, the new optical alignment structure with recess 106 being used as an alignment mark and an overlay mark in a subsequent photolithography process for fabricating semiconductor devices in epitaxial layer 104.
In other embodiments of the present invention, the formation of the mask layer in step S1 and the omission of step S2 and step S3 may be omitted as needed.
In the method for manufacturing the epitaxial wafer, the surface of the edge area of the substrate wafer is amorphized, and then an epitaxial layer is epitaxially grown on the substrate wafer to form the epitaxial wafer. In the epitaxial growth process, an amorphous epitaxial layer is formed on an edge region of the amorphous substrate wafer (i.e., the amorphous epitaxial layer is located in the edge region of the epitaxial wafer), a crystallized epitaxial layer is formed on a region of the crystallized substrate wafer (i.e., a central region of the substrate wafer except for the edge region) (i.e., the crystallized epitaxial layer is located in the central region of the epitaxial wafer), and because the epitaxial growth rate on the edge region of the wafer is slower than that on the central region of the wafer, and the stress generated in the epitaxial growth process on the edge region of the wafer is relatively smaller, the occurrence probability of slip dislocation defects on the epitaxial wafer can be reduced, so that the physical properties of the epitaxial wafer can be improved, the alignment and alignment accuracy of the subsequent photolithography process based on the epitaxial wafer manufacturing device can be improved, and the leakage path generated due to the slip dislocation defects can be further reduced, so that the performance and yield of the device based on the epitaxial wafer manufacturing device can be improved.
In addition, the epitaxial growth rate on the edge area of the wafer is slower than that on the central area of the wafer, so that the edge of the epitaxial wafer is thin and the middle is thick, and the problem of wafer warping caused by epitaxial layer growth can be avoided.
In addition, the technical scheme of the invention reduces the occurrence probability of slip dislocation defects on the epitaxial wafer mainly by amorphizing the surface of the edge area of the substrate wafer, so that the process is simple, the realization cost is low, the modification of process parameters of a thermal process (including thermal annealing and the like) for epitaxial layer growth can be avoided, and meanwhile, the problems of wafer warpage and the like caused by overlong cycle time in a furnace during epitaxial layer growth can be avoided.
Based on the same inventive concept, please refer to fig. 2 (E), an embodiment of the present invention further provides an epitaxial wafer, which may be obtained by using the manufacturing method of the epitaxial wafer of the present invention, or any other suitable manufacturing method.
The epitaxial wafer of the present embodiment includes a substrate wafer 100 and an epitaxial layer formed on the substrate wafer 100, wherein the surface of the substrate wafer 100 and the epitaxial layer in the edge region of the epitaxial wafer are both amorphized, and the surface of the substrate wafer 100 and the epitaxial layer in the remaining region are both crystallized. I.e. the surface of the substrate wafer 100 in the edge region 100a is an amorphized region 103, the epitaxial layer 105 formed on the amorphized region 103 is also amorphized; the surface of the substrate wafer 100 in the central region 100b, the substrate wafer 100 below the amorphized region 103, and the epitaxial layer 104 in the central region 100b are all crystallized.
The substrate wafer 100 may be any suitable semiconductor wafer, such as a single crystal silicon wafer, a silicon-on-insulator (SOI) wafer, a silicon germanium wafer, or a group iii-v compound wafer, among others.
Optionally, zero-layer optical alignment structures having grooves 102 are also formed at corresponding locations of the substrate wafer 100 within the amorphized regions 103 (i.e., the central region 100 b). As an example, a zero layer optical alignment structure with grooves 102 is located on one side of the substrate wafer 100 within the amorphized region 103, with a distance between the grooves 102 and the amorphized region 103.
Optionally, the amorphized region 103 is formed by amorphizing the surface of the edge region 100a of the substrate wafer 100 by one or more of ion implantation, ion thermal diffusion, surface carbonization, surface oxidation, and surface metallization, and thus the amorphized region 103 (i.e., the amorphized surface of the edge region 100a of the substrate wafer 100) is doped with one or more of N-type impurity ions, P-type impurity ions, oxygen elements, carbon elements, nitrogen elements, and metal elements.
Further alternatively, the amorphized region 103 is doped with N-type impurity ions (including at least one of arsenic, antimony, and phosphorus) or P-type impurity ions (including at least one of boron, indium, and gallium) for amorphization, or mixed impurity ions composed of N-type impurity ions and P-type impurity ions. As an example, the impurity ions in the amorphized region 103 have a doping concentration of 1E12atoms/cm 2 ~1E15atoms/cm 2 。
As an example, the lateral width W of the amorphized region 103 is less than or equal to 5cm.
As an example, the amorphized thickness H of the surface of the edge area 100a of the substrate wafer 100 (i.e., the thickness of the amorphized region 103) is less than or equal to 10 μm.
In the epitaxial wafer of this embodiment, the amorphous epitaxial layer 105 is remained in the edge region, the central region is the crystallized epitaxial layer 104, the epitaxial layer 105 and the epitaxial layer 104 are formed in the same epitaxial growth process, the amorphous epitaxial layer 105 is formed based on the epitaxial growth of the amorphous surface of the edge region 100a of the substrate wafer 100, the epitaxial layer 104 is formed based on the epitaxial growth of the crystalline surface of the substrate wafer 100, and the probability of occurrence of slip dislocation defects on the epitaxial wafer can be reduced by utilizing the characteristic that the internal stress generated in the edge region by the amorphous epitaxial layer 105 is smaller, and the thickness of the epitaxial layer 105 is thinner than that of the epitaxial layer 104, so that wafer warpage can be avoided.
Further, an optical alignment structure having a recess 106 is also formed in the epitaxial layer 104, and the optical alignment structure having a recess 106 is formed based on the optical alignment structure having a recess 102 in the substrate wafer 100.
Based on the same inventive concept, an embodiment of the present invention also provides a method of manufacturing a semiconductor device, including:
referring first to fig. 3 (a), an epitaxial wafer is provided by the method for manufacturing an epitaxial wafer according to the present invention, the epitaxial wafer includes a substrate wafer 100 and an epitaxial layer formed on the substrate wafer 100, the surface of the substrate wafer 100 and the epitaxial layer in an edge region of the epitaxial wafer are amorphous, and the surface of the substrate wafer 100 and the epitaxial layer in the remaining region are crystalline. I.e. the surface of the substrate wafer 100 in the edge region is an amorphized region 103, the epitaxial layer 105 formed on the amorphized region 103 is also amorphized; the substrate wafer 100 in the central region, the substrate wafer 100 under the amorphized region 103, and the epitaxial layer 104 in the central region are all crystallized.
Then, referring to fig. 3 (B), a desired device structure 107 is formed on the crystallized epitaxial layer 104 of the epitaxial wafer.
According to the manufacturing method of the semiconductor device, the epitaxial wafer is provided based on the manufacturing method of the epitaxial wafer, and the occurrence probability of slip dislocation defects on the epitaxial wafer can be reduced based on the device structure required by the epitaxial wafer manufacturing, so that the physical performance of the epitaxial wafer can be improved, the leakage path generated by the slip dislocation defects can be reduced, and the performance and the yield of the manufactured device can be improved.
The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention in any way, and any changes and modifications made by those skilled in the art in light of the foregoing disclosure will be deemed to fall within the scope and spirit of the present invention.
Claims (14)
1. A method of manufacturing an epitaxial wafer, comprising the steps of:
providing a substrate wafer with at least surface crystallization and defining an edge area of the substrate wafer;
amorphizing a defined edge area surface of the substrate wafer;
an epitaxial layer is formed on the substrate wafer to form an epitaxial wafer, and the epitaxial layer in an edge region of the epitaxial wafer is amorphized and the epitaxial layer in the remaining regions is crystallized.
2. The method of manufacturing an epitaxial wafer of claim 1, wherein the step of defining an edge region of the substrate wafer comprises: and gluing and baking the substrate wafer, and further exposing the edge area of the substrate wafer by a photomask or adopting a wafer edge exposure method.
3. The method of manufacturing an epitaxial wafer of claim 1, wherein the edge region of the substrate wafer has a width of less than or equal to 5cm; and/or the amorphization thickness of the edge area surface of the substrate wafer is less than or equal to 10 μm.
4. The method of claim 1, wherein the edge region surface of the substrate wafer is amorphized by a combination of one or more of ion implantation, ion thermal diffusion, surface carbonization, surface oxidation, and surface metallization.
5. The method of manufacturing an epitaxial wafer according to claim 4, wherein the surface of the edge region of the substrate wafer is amorphized by doping at least one impurity ion including N-type impurity ions and P-type impurity ions into the surface layer of the edge region of the substrate wafer by ion implantation or ion thermal diffusion.
6. The method of manufacturing an epitaxial wafer according to claim 5, wherein the N-type impurity ions include at least one of arsenic, antimony, and phosphorus; and/or the P-type impurity ions comprise at least one of boron, indium and gallium; and/or the metallization ions comprise at least one of aluminum, tungsten, copper, manganese, chromium.
7. The method of manufacturing an epitaxial wafer according to claim 5, wherein the impurity ions have a doping concentration of 1E12atoms/cm 2 ~1E15atoms/cm 2 。
8. The method of claim 5, wherein the implantation energy of the impurity ions is 1mev to 10mev.
9. The method of manufacturing an epitaxial wafer of any one of claims 1-8, further comprising, prior to defining the edge region of the substrate wafer:
covering a mask layer on the substrate wafer;
etching the mask layer and a part of the thickness of the substrate wafer to form a zero-layer optical alignment structure with a groove in the substrate wafer;
removing the mask layer;
and when an epitaxial layer is formed on the substrate wafer, the epitaxial layer also covers the grooves in a conformal manner to form a new zero-layer optical alignment structure in a conformal manner.
10. An epitaxial wafer comprising a substrate wafer and an epitaxial layer formed on the substrate wafer, wherein the surface of the substrate wafer in an edge region of the epitaxial wafer and the epitaxial layer are both amorphized and the surface of the substrate wafer and the epitaxial layer in the remaining regions are both crystallized.
11. The epitaxial wafer of claim 10, wherein the edge region of the substrate wafer has a width of less than or equal to 5cm.
12. The epitaxial wafer of claim 10, wherein the amorphized surface of the edge region of the substrate wafer comprises one or more combinations of N-type impurity ions, P-type impurity ions, oxygen elements, carbon elements, nitrogen elements, and metal elements.
13. The epitaxial wafer of claim 12, wherein the amorphized thickness of the edge area surface of the substrate wafer is less than or equal to 10 μιη.
14. A method of manufacturing a semiconductor device, comprising:
providing an epitaxial wafer by using the method for manufacturing an epitaxial wafer according to any one of claims 1 to 9;
and forming a required device structure on the crystallized epitaxial layer of the epitaxial wafer.
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