CN112908916A - Buried layer alignment mark and manufacturing method thereof - Google Patents

Buried layer alignment mark and manufacturing method thereof Download PDF

Info

Publication number
CN112908916A
CN112908916A CN202110074698.1A CN202110074698A CN112908916A CN 112908916 A CN112908916 A CN 112908916A CN 202110074698 A CN202110074698 A CN 202110074698A CN 112908916 A CN112908916 A CN 112908916A
Authority
CN
China
Prior art keywords
layer
alignment mark
semiconductor substrate
manufacturing
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110074698.1A
Other languages
Chinese (zh)
Inventor
范晓
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hua Hong Semiconductor Wuxi Co Ltd
Original Assignee
Hua Hong Semiconductor Wuxi Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hua Hong Semiconductor Wuxi Co Ltd filed Critical Hua Hong Semiconductor Wuxi Co Ltd
Priority to CN202110074698.1A priority Critical patent/CN112908916A/en
Publication of CN112908916A publication Critical patent/CN112908916A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/544Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54426Marks applied to semiconductor devices or parts for alignment

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a buried layer alignment mark and a manufacturing method thereof. The manufacturing method of the buried layer alignment mark comprises the following steps: providing a semiconductor substrate; the semiconductor substrate comprises a first surface and a second surface which are opposite; forming an interlayer spacing layer on the first surface of the semiconductor substrate; defining an alignment mark pattern on the interlayer spacing layer; etching and removing the interlayer spacing layer outside the alignment mark pattern according to the alignment mark pattern to form an alignment mark structure; the first surface of the semiconductor substrate in the region except the alignment mark is exposed; and forming an epitaxial layer on the semiconductor substrate, so that the epitaxial layer covers the alignment mark structure and the exposed first surface of the semiconductor substrate. The buried layer alignment mark is manufactured by the method. The method and the device can solve the problems that alignment marks are not clear and alignment accuracy is not facilitated in the related technology.

Description

Buried layer alignment mark and manufacturing method thereof
Technical Field
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a buried layer alignment mark and a manufacturing method thereof.
Background
Buried layer technology is widely used in semiconductor processes, such as bipolar semiconductor devices, image sensors, and Bi-CMOS devices. Taking a bipolar semiconductor device as an example, the collector of the transistor needs to be led out from the bottom layer of the device, so that the series resistance of the collector is increased, which is not favorable for the circuit performance. In order to provide a low resistance path for the current flow to the collector and reduce the series resistance of the collector, a buried layer is usually formed in the substrate of the device in advance, then an epitaxial layer is formed, and the collector aligned with the buried layer is formed in the epitaxial layer. Therefore, in such devices, the buried layer alignment process is critical to the performance of the circuit.
In the related art, an alignment trench is usually formed on a substrate layer as a mark for buried layer implantation, and then an epitaxial layer is formed on the substrate layer according to the topography of the surface of the substrate layer on which the alignment trench is formed, wherein a corresponding groove is formed on the surface of the epitaxial layer corresponding to the alignment trench, and is used for aligning the buried layer when ion implantation is performed on the epitaxial layer.
However, once the width of the alignment trench is narrow, a shallow groove or no groove is formed on the surface of the epitaxial layer at a position corresponding to the narrow alignment trench, which is prone to cause a problem of unclear alignment marks and is not favorable for alignment accuracy.
Disclosure of Invention
The application provides a buried layer alignment mark and a manufacturing method thereof, which can solve the problems that alignment marks are not clear and alignment accuracy is not facilitated in the related technology.
In order to solve the above technical problem, the present application provides a method for manufacturing a buried layer alignment mark, where the method includes:
providing a semiconductor substrate; the semiconductor substrate comprises a first surface and a second surface which are opposite;
forming an interlayer spacing layer on the first surface of the semiconductor substrate;
defining an alignment mark pattern on the interlayer spacing layer;
etching and removing the interlayer spacing layer outside the alignment mark pattern according to the alignment mark pattern to form an alignment mark structure; the first surface of the semiconductor substrate in the region except the alignment mark is exposed;
and forming an epitaxial layer on the semiconductor substrate, so that the epitaxial layer covers the alignment mark structure and the exposed first surface of the semiconductor substrate.
Optionally, the steps of: forming an interlayer spacer on a first surface of the semiconductor substrate, comprising:
manufacturing and forming a silicide layer on the first surface of the semiconductor substrate;
and manufacturing and forming a polycrystalline silicon layer on the silicide layer.
Optionally, the steps of: and in the step of manufacturing and forming the silicide layer on the first surface of the semiconductor substrate, the thickness of the formed silicide is 50nm to 300 nm.
Optionally, the silicide layer includes any one or a combination of a silicon oxide layer and a silicon nitride layer.
Optionally, the steps of: and in the step of manufacturing and forming a polycrystalline silicon layer on the silicide layer, the thickness of the formed polycrystalline silicon layer is 30nm to 200 nm.
Optionally, in the step: after forming an interlayer spacing layer on the first surface of the semiconductor substrate is completed, in the step: before defining the alignment mark pattern on the interlayer spacing layer, the method further comprises the following steps:
and manufacturing and forming a silicon oxide buffer layer on the interlayer spacing layer.
Optionally, the steps of: defining an alignment mark pattern on the interlayer spacing layer, comprising:
and selectively etching the silicon oxide buffer layer to enable the silicon oxide buffer layer to be on the interlayer spacing layer and define an alignment mark pattern.
Optionally, the thickness of the epitaxial layer is 1um to 5 um.
As a second aspect of the present application, there is provided a buried layer alignment mark, which is manufactured by the method for manufacturing a buried layer alignment mark according to the first aspect of the present application.
The technical scheme at least comprises the following advantages: by arranging the interlayer spacing layer to comprise a material with a refractive index different from that of the substrate and the epitaxial layer, an optical layering can be formed at the position of the interlayer spacing layer in the optical alignment process, so that the interlayer spacing layer can strengthen the identification degree of the alignment groove in the optical alignment process.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flowchart illustrating a method for manufacturing a buried layer alignment mark according to an embodiment of the present disclosure;
FIG. 1a illustrates a semiconductor substrate structure provided herein;
FIG. 1b is a schematic cross-sectional view of the device after step S2 is completed;
FIG. 1c is a schematic cross-sectional view of the device after step S4 is completed;
fig. 1d shows a schematic cross-sectional structure of the device after step S5 is completed.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Fig. 1 shows a flowchart of a method for manufacturing a buried layer alignment mark according to an embodiment of the present application, and referring to fig. 1, the method for manufacturing a buried layer alignment mark includes the following steps:
step S1: providing a semiconductor substrate; the semiconductor substrate includes opposing first and second surfaces.
The semiconductor substrate may be a doped silicon substrate. Fig. 1a schematically shows a semiconductor substrate structure provided in the present application, and referring to fig. 1a, a first surface 11 of the semiconductor substrate 10 in this embodiment is an upper surface of the semiconductor substrate 10, and a second surface 12 of the semiconductor substrate 10 is a lower surface of the semiconductor substrate 10.
Step S2: an interlayer spacer is formed on the first surface of the semiconductor substrate.
In this embodiment, the interlayer spacer includes a silicide having a refractive index different from that of the semiconductor substrate, and the silicide may be silicon nitride or silicon oxide, or a composite layer of a silicon nitride layer and a silicon oxide layer. Referring to fig. 1b, which shows a schematic cross-sectional structure of the device after step S2 is completed, an interlayer spacer 12 is formed on the first surface 11 of the semiconductor substrate 10, and the interlayer spacer 12 includes a silicide layer 121 and a polysilicon layer 122 stacked in sequence. Optionally, the thickness of the silicide layer 121 is 50nm to 300nm, and the thickness of the polysilicon layer 122 is 30nm to 200 nm.
Step S3: and defining an alignment mark pattern on the interlayer spacing layer.
In this embodiment, the pattern of the alignment mark may be defined on the interlayer spacer by using a photoresist. Firstly, coating a photoresist layer on the interlayer spacing layer, and forming an alignment mark pattern on the photoresist layer through an exposure and development process. It should be explained that, according to the alignment mark pattern, in the subsequent steps, the interlayer spacer layer is continuously etched, so that the alignment mark pattern can be transferred onto the interlayer spacer layer, an alignment mark structure is further formed, and the remaining photoresist layer is removed after the alignment mark structure is formed.
In addition, a silicon oxide buffer layer can be formed on the interlayer spacing layer, and the alignment mark pattern can be defined through the silicon oxide buffer layer. Firstly, forming a silicon oxide buffer layer on the interlayer spacing layer, then coating photoresist on the silicon oxide buffer layer, forming an alignment mark pattern on the photoresist layer through an exposure and development process, and then etching the silicon oxide buffer layer according to the alignment mark pattern so as to transfer the alignment mark pattern to the silicon oxide buffer layer. It should be explained that, according to the alignment mark pattern defined by the silicon oxide buffer layer, in the subsequent steps, the interlayer spacer is continuously etched, so that the alignment mark pattern can be further transferred onto the interlayer spacer, an alignment mark structure is further formed, and the remaining silicide buffer layer is removed after the alignment mark structure is formed.
Step S4: etching and removing the interlayer spacing layer outside the alignment mark pattern according to the alignment mark pattern to form an alignment mark structure; the first surface of the semiconductor substrate in the region outside the alignment mark is exposed.
Referring to fig. 1c, a schematic cross-sectional structure of the device after step S4 is completed is shown. Referring to fig. 1c, the remaining interlayer spacers 12 form spaced alignment mark structures 120.
After the alignment mark structure on the semiconductor substrate is manufactured, ion implantation may be performed on the semiconductor substrate according to the alignment mark structure, and a buried layer is formed in the semiconductor substrate.
Step S5: and forming an epitaxial layer on the semiconductor substrate, so that the epitaxial layer covers the alignment mark structure and the exposed first surface of the semiconductor substrate.
Referring to fig. 1d, which shows a schematic cross-sectional structure of the device after step S5 is completed, referring to fig. 1d, an epitaxial layer 20 is formed to cover the semiconductor substrate 10, the epitaxial layer 20 covers the alignment mark structure 120, and the exposed first surface 11 of the semiconductor substrate 10. In this embodiment, the thickness of the epitaxial layer may be 1um to 5 um.
It is understood that, since the alignment mark structure 120 includes a silicide layer having a refractive index different from that of the semiconductor substrate 10 and a lattice structure of the silicide layer is different from that of the epitaxial layer, the polycrystalline silicon layer formed on the silicide layer has a lattice structure identical to that of the epitaxial layer, which facilitates the growth of the epitaxial layer thereon.
After step S5 is completed, the epitaxial layer covers the alignment mark structure and the exposed first surface of the semiconductor substrate, and since the alignment mark structure includes an interlayer spacer layer having a refractive index different from that of both the substrate and the epitaxial layer, an optical interface may be formed at the interlayer spacer layer according to optical alignment to determine a position where the optical interface is formed as the alignment mark structure, so as to align the buried layer in the semiconductor substrate according to the alignment mark, and perform epitaxial layer ion implantation.
In this embodiment, the interlayer spacer layer is made of a material having a refractive index different from that of the substrate and the epitaxial layer, so that an optical layer is formed at the interlayer spacer layer during the optical alignment process, and the interlayer spacer layer can enhance the identification degree of the alignment trench during the optical alignment process.
The application also provides a buried layer alignment mark which is manufactured and formed according to the manufacturing method of the buried layer alignment mark shown in the figure 1.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims (9)

1. A method for manufacturing a buried layer alignment mark is characterized by comprising the following steps:
providing a semiconductor substrate; the semiconductor substrate comprises a first surface and a second surface which are opposite;
forming an interlayer spacing layer on the first surface of the semiconductor substrate;
defining an alignment mark pattern on the interlayer spacing layer;
etching and removing the interlayer spacing layer outside the alignment mark pattern according to the alignment mark pattern to form an alignment mark structure; the first surface of the semiconductor substrate in the region except the alignment mark is exposed;
and forming an epitaxial layer on the semiconductor substrate, so that the epitaxial layer covers the alignment mark structure and the exposed first surface of the semiconductor substrate.
2. The method for fabricating a buried layer alignment mark according to claim 1, wherein the step of: forming an interlayer spacer on a first surface of the semiconductor substrate, comprising:
manufacturing and forming a silicide layer on the first surface of the semiconductor substrate;
and manufacturing and forming a polycrystalline silicon layer on the silicide layer.
3. The method for fabricating a buried layer alignment mark according to claim 2, wherein the step of: and in the step of manufacturing and forming the silicide layer on the first surface of the semiconductor substrate, the thickness of the formed silicide is 50nm to 300 nm.
4. The method for fabricating the buried layer alignment mark according to claim 2, wherein the silicide layer comprises any one or a combination of a silicon oxide layer and a silicon nitride layer.
5. The method for fabricating a buried layer alignment mark according to claim 2, wherein the step of: and in the step of manufacturing and forming a polycrystalline silicon layer on the silicide layer, the thickness of the formed polycrystalline silicon layer is 30nm to 200 nm.
6. The method for fabricating a buried layer alignment mark according to claim 1, wherein in the step: after forming an interlayer spacing layer on the first surface of the semiconductor substrate is completed, in the step: before defining the alignment mark pattern on the interlayer spacing layer, the method further comprises the following steps:
and manufacturing and forming a silicon oxide buffer layer on the interlayer spacing layer.
7. The method for fabricating a buried layer alignment mark according to claim 6, wherein the step of: defining an alignment mark pattern on the interlayer spacing layer, comprising:
and selectively etching the silicon oxide buffer layer to enable the silicon oxide buffer layer to be on the interlayer spacing layer and define an alignment mark pattern.
8. The method for fabricating a buried layer alignment mark according to claim 1, wherein the epitaxial layer has a thickness of 1um to 5 um.
9. A buried layer alignment mark, characterized in that it is fabricated by the method of fabricating a buried layer alignment mark according to any one of claims 1 to 8.
CN202110074698.1A 2021-01-20 2021-01-20 Buried layer alignment mark and manufacturing method thereof Pending CN112908916A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110074698.1A CN112908916A (en) 2021-01-20 2021-01-20 Buried layer alignment mark and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110074698.1A CN112908916A (en) 2021-01-20 2021-01-20 Buried layer alignment mark and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN112908916A true CN112908916A (en) 2021-06-04

Family

ID=76116644

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110074698.1A Pending CN112908916A (en) 2021-01-20 2021-01-20 Buried layer alignment mark and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN112908916A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020028528A1 (en) * 2000-09-01 2002-03-07 Shiro Ohtaka Alignment marks and method of forming the same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020028528A1 (en) * 2000-09-01 2002-03-07 Shiro Ohtaka Alignment marks and method of forming the same

Similar Documents

Publication Publication Date Title
JP2000058857A (en) Transistor having improved soi body contact structure
US9188883B2 (en) Alignment mark
CN111725247A (en) Self-alignment etching method for drain-source contact hole of CIS chip
US8278770B2 (en) Overlay mark
CN112908966A (en) Buried layer alignment mark and manufacturing method thereof, and semiconductor device and manufacturing method thereof
CN115863159A (en) Semiconductor device manufacturing method
WO2012028109A1 (en) Semicondunctor device and method of fabricating the same
CN112908916A (en) Buried layer alignment mark and manufacturing method thereof
US7504313B2 (en) Method for forming plural kinds of wells on a single semiconductor substrate
CN112259568B (en) Contact hole forming method applied to image sensor
CN112635504A (en) Manufacturing method of ultra-deep photodiode in CIS device and CIS device
CN111370297A (en) Method for manufacturing super junction
CN108766879B (en) Preparation method of transistor gate and transistor structure
CN112259567A (en) Method for forming microlens of CIS
CN114823308A (en) Ion implantation method
JP5644466B2 (en) Manufacturing method of semiconductor device
CN111725305B (en) Semiconductor device and method for manufacturing the same
US11527428B2 (en) Semiconductor device and method of fabrication the same
CN110739273B (en) Manufacturing method of ultra-thin grid CMOS device
CN113611606B (en) Voltage stabilizing diode and manufacturing method thereof
TWI829376B (en) Method for manufacturing semiconductor structure
JPS6387762A (en) Manufacture of semiconductor device
TW200419699A (en) Process for integrating alignment and trench device
JP2820465B2 (en) Method for manufacturing semiconductor device
CN117855044A (en) Preparation method of L & R structure SGT device and SGT device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20210604

RJ01 Rejection of invention patent application after publication