CN112908884A - LED wafer yield detection method - Google Patents
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- H01L22/10—Measuring as part of the manufacturing process
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Abstract
The invention discloses a method for detecting the yield of an LED wafer, which comprises the following steps: s1, capturing the same wafer defect characteristics on the wafer to be detected as those in the process defect characteristic module by using the machine vision capturing module; and S2, counting and recording the defect characteristic positions and the defect number of the wafer to be detected through the wafer defect processing module, and distinguishing the positions with defects by using red frames and green frames, wherein the red frames represent the positions with defect characteristics of the wafer, and the green frames represent the positions with no defect characteristics of the wafer. Compared with the existing method for detecting the yield of the wafer by manually and visually inspecting the wafer after the wafer needs to be cut, the method for detecting the yield of the wafer can pre-judge the yield of the wafer without cutting the wafer, avoid the situation that the yield is abnormal only when the wafer is cut and packaged, improve the wafer inspection efficiency and enable the wafer inspection efficiency to follow the manufacturing speed.
Description
Technical Field
The invention relates to the technical field of wafer yield detection, in particular to a method for detecting the yield of an LED wafer.
Background
The wafer refers to a silicon wafer used for manufacturing a silicon semiconductor integrated circuit, and is called a wafer because the wafer is circular in shape, and the wafer includes a plurality of dies (die), wherein some of the dies are defective dies that cannot be used, and the rest are qualified dies, and the yield of the wafer is defined as: as a wafer foundry, it is often necessary to provide a wafer product with a yield of 85% or more, or even more than 90%, to a customer, otherwise the customer determines the wafer product as a waste wafer.
In order to avoid the generation of waste wafers in wafer products provided for customers, a factory sets up a plurality of inspection stations in the process of producing wafers, the inspection stations are arranged after some key-level processes, the factory gives a predicted yield value to each wafer analysis, if the predicted yield value of a certain wafer is lower than the requirement of the customer, the wafer is scrapped in the factory, so as to prevent the outflow from causing larger loss to the factory.
The existing wafer yield detection method is to cut the wafer after the wafer production is finished, and judge the wafer yield through manual visual inspection, however, because the manual visual inspection efficiency cannot keep up with the manufacturing speed and is easy to neglect, the yield abnormality is often found after the wafer is cut and packaged, and the packaging waste is caused.
Disclosure of Invention
In order to solve the above mentioned problems in the background art, a method for detecting the yield of LED wafer is proposed.
In order to achieve the purpose, the invention adopts the following technical scheme:
the LED wafer yield detection method is characterized by comprising an artificial intelligent detection system, wherein the artificial intelligent detection system comprises a process defect characteristic module, a machine vision capture module, a wafer defect processing module, a wafer yield calculation module and a result display module:
the process defect feature module records various wafer defect features;
the machine vision capturing module is used for capturing defect characteristics on the wafer to be detected;
the wafer defect processing module is used for recording the characteristic positions and the defect numbers of the wafer defects;
the wafer yield calculation module is used for calculating the wafer prejudgment yield value;
the result display module displays the pre-judging yield result of the wafer to be detected;
the method for detecting the wafer yield through the artificial intelligence detection system comprises the following steps:
s1, capturing the same wafer defect characteristics on the wafer to be detected as in the process defect characteristic module by using the machine vision capturing module, acquiring the rotation angle of the whole picture through the average minimum value of pixels of the horizontal and vertical directions of part of the wafer, and filling black pixels around the rotation to ensure the integrity of the image;
s2, obtaining a detection part through local threshold segmentation and expansion and contraction by a wafer defect processing module, and removing a non-detection area similar to the wafer according to feature selection, and only leaving a wafer detection area;
determining the position of each wafer frame through the average minimum value of pixels in the horizontal direction and the vertical direction, and detecting four edges by a caliper tool to judge whether defects exist or not;
counting and recording the defect characteristic positions and defect numbers of the wafer to be detected, and distinguishing positions with defects by using a red frame and a green frame, wherein the red frame represents the positions with the defect characteristics of the wafer, and the green frame represents the positions with the defect-free characteristics of the wafer;
s3, calculating by the wafer yield calculation module to obtain a predetermined yield value:
wherein, the formula for calculating the prejudged yield value is as follows:
specifically, the number of unqualified grains-the number of defects, and the total number of grains is a known quantity;
and S4, displaying the pre-judging yield result of the wafer to be detected through the result display module.
As a further description of the above technical solution:
the defect characteristics of the various wafers are from the statistical sum of the defect characteristics of all the test base stations.
As a further description of the above technical solution:
each of the test base stations is disposed after a process of a main level, the main level including: the method comprises the following steps of field oxide, source-drain photoetching, source-drain doping, grid region photoetching, grid oxidation, contact hole photoetching, metal layer deposition, metal layer photoetching, an alloy metal layer, passivation layer deposition and passivation layer photoetching.
As a further description of the above technical solution:
the wafer defect features include wafer surface redundancy, crystal defects, and mechanical damage.
As a further description of the above technical solution:
the redundancy includes nano-sized minute particles, micro-sized dust, and residues of related processes.
As a further description of the above technical solution:
the pre-judging yield result is one or more of a numerical value, a histogram or a pie chart.
As a further description of the above technical solution:
and the wafer defect processing module is a counting module which records the total number of crystal grains, qualified crystal grains and unqualified crystal grains of the wafer to be detected.
As a further description of the above technical solution:
the total number of the crystal grains is the number of qualified crystal grains plus the number of unqualified crystal grains, and the number of the unqualified crystal grains is the number of defects.
In summary, due to the adoption of the technical scheme, the invention has the beneficial effects that:
1. compared with the existing method for detecting the yield of the wafer by manually and visually inspecting the wafer after the wafer is required to be cut, the method has the advantages that the defect characteristics of the wafer to be detected are captured through the machine vision capture module, the wafer defect characteristics in the process defect characteristic module are compared with the wafer defect characteristics, the wafer defect characteristic positions and the defect number are recorded through the wafer defect processing module, the defect number is calculated through the wafer yield calculation module, the wafer pre-judgment yield value is obtained, the wafer yield can be pre-judged before the wafer is cut, the packaging waste is reduced, the situation that the yield is abnormal only when the wafer is cut and packaged can be avoided, the wafer inspection efficiency is improved, and the wafer inspection efficiency can be close to the manufacturing speed.
2. According to the invention, the defect characteristic position and the defect number of the wafer to be detected are recorded through the wafer defect processing module, the defect-free positions are distinguished by the red frame and the green frame, the red frame represents the position of the defect characteristic of the wafer, the green frame represents the position of the defect-free characteristic of the wafer, the region where the abnormality is concentrated is judged according to the red frame display region, equipment adjustment can be carried out in the front-end processing procedure, so that the abnormal defect of the wafer is reduced, and the production yield is improved.
Drawings
FIG. 1 is a schematic diagram illustrating a predetermined yield result of an LED wafer yield detection method according to an embodiment of the present invention;
fig. 2 is a pie chart illustrating the predetermined yield result of the LED wafer yield testing method according to the embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without any inventive step, are within the scope of the present invention.
Example one
Referring to fig. 1 and fig. 2, the present invention provides a technical solution: the LED wafer yield detection method comprises an artificial intelligence detection system, wherein the artificial intelligence detection system comprises a process defect characteristic module, a machine vision capturing module, a wafer defect processing module, a wafer yield calculation module and a result display module:
the process defect characteristic module records various wafer defect characteristics;
the machine vision capturing module is used for capturing defect characteristics on the wafer to be detected;
the wafer defect processing module is used for recording the characteristic positions and the defect number of the wafer defects;
the wafer yield calculation module is used for calculating the wafer pre-judging yield value;
the result display module displays the pre-judging yield result of the wafer to be detected;
the method for detecting the wafer yield through the artificial intelligence detection system comprises the following steps:
s1, capturing the same wafer defect characteristics on the wafer to be detected as in the process defect characteristic module by using the machine vision capturing module, acquiring the rotation angle of the whole picture through the average minimum value of pixels of the horizontal and vertical directions of part of the wafer, and filling black pixels around the rotation to ensure the integrity of the image;
s2, obtaining a detection part through local threshold segmentation and expansion and contraction by a wafer defect processing module, and removing a non-detection area similar to the wafer according to feature selection, and only leaving a wafer detection area;
determining the position of each wafer frame through the average minimum value of pixels in the horizontal direction and the vertical direction, and detecting four edges by a caliper tool to judge whether defects exist or not;
counting and recording the defect characteristic positions and defect numbers of the wafer to be detected, and distinguishing positions with defects by using a red frame and a green frame, wherein the red frame represents the positions with the defect characteristics of the wafer, and the green frame represents the positions with the defect-free characteristics of the wafer;
according to the red frame display area, judging which area the abnormality is concentrated in, and adjusting equipment in the front-end process to reduce the generation of abnormal defects of the wafer so as to improve the production yield;
s3, calculating by the wafer yield calculation module to obtain a predetermined yield value:
wherein, the formula for calculating the prejudged yield value is as follows:
specifically, the number of unqualified grains-the number of defects, and the total number of grains is a known quantity;
and S4, displaying the pre-judging yield result of the wafer to be detected through the result display module.
Specifically, the defect characteristics of the multiple wafers are from the statistical sum of the defect characteristics of each test base station, and each test base station is arranged after the process of the main level, wherein the main level comprises: the method comprises the following steps of field oxide, source-drain photoetching, source-drain doping, grid region photoetching, grid oxidation, contact hole photoetching, metal layer deposition, metal layer photoetching, alloy metal layer, passivation layer deposition and passivation layer photoetching.
Specifically, the wafer defect characteristics comprise wafer surface redundancy, crystal defects and mechanical damages, and the redundancy comprises nanometer-scale tiny particles, micrometer-scale dust and residues of related processes.
Referring to fig. 1 and 2, the yield prediction result is one or more of a numerical value, a histogram, or a pie chart.
Specifically, the wafer defect processing module records the total number of crystal grains of the wafer to be detected, the number of qualified crystal grains and the number of unqualified crystal grains, wherein the total number of crystal grains is the number of qualified crystal grains plus the number of unqualified crystal grains, and the number of unqualified crystal grains is the number of defects;
the feasibility of the wafer yield detection result in the invention is demonstrated through a feasibility proving experiment of prejudging the yield value:
specifically, firstly, a plurality of wafers to be detected are selected to detect the pre-determined yield value of each wafer to be detected by the detection method of the invention, secondly, the wafer to be detected is cut and the actual yield value of the wafer to be detected is calculated, and compared with the pre-determined yield value obtained by the detection method of the invention, the results obtained after comparison are shown in the following table 1:
wherein, the difference value is the actual rate value-the prejudgment rate value;
TABLE 1 statistical table of difference between predicted yield and actual yield of wafer to be tested
| Prediction of yield value (%) | Actual yield value (%) | Difference (%) | |
| Wafer 1 to be tested | 80.6 | 82.1 | 1.5 |
| Wafer 2 to be tested | 94.4 | 91.7 | -2.7 |
| Wafer 3 to be detected | 86.2 | 82.4 | -3.8 |
| Wafer 4 to be detected | 92.2 | 90.7 | -1.5 |
| Wafer 5 to be detected | 89.4 | 90.4 | -1.0 |
| Wafer 6 to be detected | 88.4 | 87.2 | -1.2 |
As can be seen from table 1, the difference between the predicted yield value and the actual yield value of the wafer to be detected is-1.2% -3.8%, that is, if the number of the unqualified wafers of the wafer to be detected is 10, the actual number of the unqualified wafers of the wafer to be detected is 8-14, and the number of the unqualified wafers belongs to the allowable range, so that the predicted yield value obtained by the wafer yield detection method provided by the invention can be used as a value for judging the actual yield of the wafer;
compared with the existing method for detecting the yield of the wafer by manually and visually checking the wafer after the wafer needs to be cut, the method can be used for prejudging the yield of the wafer before the wafer is cut, so that the packaging waste is reduced, the situation that the yield is abnormal only when the wafer is cut and packaged can be avoided, the wafer checking efficiency is improved, and the wafer checking efficiency can follow the manufacturing speed.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be able to cover the technical scope of the present invention, the technical solutions and the inventive concepts of the present invention with equivalent or modified alternatives and modifications within the technical scope of the present invention.
Claims (8)
1. The LED wafer yield detection method is characterized by comprising an artificial intelligence detection system, wherein the artificial intelligence detection system comprises a process defect characteristic module, a machine vision capture module, a wafer defect processing module, a wafer yield calculation module and a result display module:
the process defect feature module records various wafer defect features;
the machine vision capturing module is used for capturing defect characteristics on the wafer to be detected;
the wafer defect processing module is used for recording the characteristic positions and the defect numbers of the wafer defects;
the wafer yield calculation module is used for calculating the wafer prejudgment yield value;
the result display module displays the pre-judging yield result of the wafer to be detected;
the method for detecting the wafer yield through the artificial intelligence detection system comprises the following steps:
s1, capturing the same wafer defect characteristics on the wafer to be detected as in the process defect characteristic module by using the machine vision capturing module, acquiring the rotation angle of the whole picture through the average minimum value of pixels of the horizontal and vertical directions of part of the wafer, and filling black pixels around the rotation to ensure the integrity of the image;
s2, obtaining a detection part through local threshold segmentation and expansion and contraction by a wafer defect processing module, and removing a non-detection area similar to the wafer according to feature selection, and only leaving a wafer detection area;
determining the position of each wafer frame through the average minimum value of pixels in the horizontal direction and the vertical direction, and detecting four edges by a caliper tool to judge whether defects exist or not;
counting and recording the defect characteristic positions and defect numbers of the wafer to be detected, and distinguishing positions with defects by using a red frame and a green frame, wherein the red frame represents the positions with the defect characteristics of the wafer, and the green frame represents the positions with the defect-free characteristics of the wafer;
s3, calculating by the wafer yield calculation module to obtain a predetermined yield value:
wherein, the formula for calculating the prejudged yield value is as follows:
specifically, the number of unqualified grains-the number of defects, and the total number of grains is a known quantity;
and S4, displaying the pre-judging yield result of the wafer to be detected through the result display module.
2. The method as claimed in claim 1, wherein the defect characteristics of the plurality of wafers are derived from a statistical sum of defect characteristics of each testing station.
3. The method as claimed in claim 2, wherein each of the testing stations is disposed after a main level process, the main level process comprising: the method comprises the following steps of field oxide, source-drain photoetching, source-drain doping, grid region photoetching, grid oxidation, contact hole photoetching, metal layer deposition, metal layer photoetching, alloy metal layer, passivation layer deposition and passivation layer photoetching.
4. The method as claimed in claim 3, wherein the wafer defect features include wafer surface redundancy, crystal defects and mechanical damage.
5. The method as claimed in claim 4, wherein the redundancy includes nanometer-sized micro particles, micrometer-sized dust and residues of related processes.
6. The method as claimed in claim 5, wherein the predetermined yield result is one or more of a numerical value, a histogram, or a pie chart.
7. The method as claimed in claim 6, wherein the wafer defect processing module includes a statistical module for recording the total number of dies, the qualified dies and the unqualified dies of the wafer to be tested.
8. The method as claimed in claim 7, wherein the total number of dies is the number of qualified dies + the number of unqualified dies, and the number of unqualified dies is the number of defects.
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| CN114295959A (en) * | 2021-12-17 | 2022-04-08 | 珠海市科迪电子科技有限公司 | Double-line driving chip testing method and device |
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