CN112904254A

CN112904254A - Upper computer system for Memory VRTT dynamic response test and working method thereof

Info

Publication number: CN112904254A
Application number: CN202110087087.0A
Authority: CN
Inventors: 朱致远; 潘喜光
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2021-01-22
Filing date: 2021-01-22
Publication date: 2021-06-04
Anticipated expiration: 2041-01-22
Also published as: CN112904254B

Abstract

The application discloses a host computer system for Memory VRTT dynamic response test and a working method thereof, wherein the host computer system comprises: the device comprises an upper computer, a board card to be tested, a logic switch wiring module, a digital multimeter, an oscilloscope, a VRTT Tool and a data processing module. The board card to be tested, the logic switch wiring module, the digital multimeter and the oscilloscope form a self-correction realization area, the board card to be tested, the oscilloscope and the VRTT Tool form a data acquisition area, and the data processing module forms a data processing area. The method comprises the following steps: building a test environment; electrifying according to the Memory VRTT standard; carrying out probe self-correction and probe precision self-correction; starting an initial test; judging whether the initial test result meets the SPEC standard or not; if yes, generating a test report by using a data processing module; otherwise, debugging is carried out; after debugging, carrying out probe self-correction and probe precision self-correction again until a test report is obtained; powering down according to the Memory VRTT standard. Through the method and the device, the testing efficiency and the accuracy of the testing result can be effectively improved.

Description

Upper computer system for Memory VRTT dynamic response test and working method thereof

Technical Field

The application relates to the technical field of server Memory (internal Memory) dynamic response testing, in particular to an upper computer system for Memory VRTT dynamic response testing and a working method thereof.

Background

With the development of server technology, the requirements on the quality of the server are higher and higher. The dynamic response of the server Memory is a key item to be considered when the server Memory is designed in Power. Therefore, it is an important technical problem how to Test the dynamic response of the Memory VRTT (Voltage Regulator Test Tool, which is a special Test Tool for Intel) of the server, so as to determine the dynamic response characteristic of the Memory of the server.

At present, a method for testing the Memory VRTT dynamic response of a server generally adopts manual testing. Specifically, the oscilloscope probe is corrected in a manual mode, multiple manual adjustments are sometimes needed, the VRTT tool parameters are manually adjusted, and data and waveforms need to be manually filled into the test report module in the analysis process.

However, in the current method for testing the Memory VRTT dynamic response of the server, because there are many links adopting manual adjustment and some links need to be repeatedly verified, the testing efficiency is low and the accuracy of the testing result is not high enough.

Disclosure of Invention

The application provides an upper computer system for Memory VRTT dynamic response testing and a working method thereof, and aims to solve the problems that the testing efficiency is low and the accuracy of a testing result is not high enough in a testing method in the prior art.

In order to solve the technical problem, the embodiment of the application discloses the following technical scheme:

a host computer system for Memory VRTT dynamic response testing, the system comprising: the device comprises an upper computer, a board to be tested, a logic switch wiring module, a digital multimeter, an oscilloscope, a VRTT Tool and a data processing module, wherein the board to be tested, the logic switch wiring module, the digital multimeter and the oscilloscope form a self-correction realization area, the board to be tested, the oscilloscope and the VRTT Tool form a data acquisition area, the data processing module forms a data processing area, the upper computer is in communication connection with the board to be tested through JTAG-USB and PMBUS-Dongle-USB, the upper computer is respectively connected with the logic switch wiring module and the VRTT Tool through USB cables, the upper computer is respectively connected with the digital multimeter, the oscilloscope and the data processing module through GPIB cables, the board to be tested is connected with the oscilloscope through a differential probe rod and a single-ended probe rod, the board to be tested is connected with the digital multimeter through the logic switch wiring module, the board to be tested is also connected with the oscilloscope through the logic switch, the board card to be tested is connected with the VRTT Tool through a USB cable;

the self-correction realization area is used for realizing probe self-correction and determining probe precision self-correction of final SPEC;

the data acquisition area is used for executing initial test and reinspection test in the debugging process according to the control of the upper computer;

the data processing area is used for acquiring and processing data from the upper computer, generating a test report and returning the test report to the upper computer when a processing result meets the SPEC standard, returning an adjusting command to the upper computer when the processing result does not meet the SPEC standard, and adjusting the loop PID and the nonlinear parameter and retransmitting the data by the upper computer until the processing result of the data processing module meets the SPEC standard;

the logic switch wiring module is used for realizing different state modes by adopting different switch modes according to the acquired command, and the state modes comprise: the device comprises a normal test mode, a probe self-correction mode and a probe precision self-correction mode.

Optionally, the logic switch wiring module includes: the device comprises a single chip microcomputer, a first logic switch and a second logic switch, wherein the single chip microcomputer is in communication connection with an upper computer, one end of the first logic switch is connected with an oscilloscope probe channel through a differential probe, the other end of the logic switch is connected with an oscilloscope correction area, one end of the second logic switch is connected with a digital multimeter, and the other end of the second logic switch is connected with a board to be tested through the first logic switch.

An operating method of an upper computer system for Memory VRTT dynamic response testing is applied to the upper computer system for Memory VRTT dynamic response testing, and comprises the following steps:

building a test environment;

electrifying an upper computer, a board card to be tested, a logic switch wiring module, a digital multimeter, an oscilloscope, a VRTT Tool and a data processing module according to the electrifying sequence of the Memory VRTT standard;

utilizing a self-correction realization area to carry out probe self-correction and probe precision self-correction;

starting an initial test according to a command of an upper computer;

judging whether the initial test result meets the Memory VRTT dynamic response SPEC standard or not;

if yes, generating a test report by using a data processing module;

if not, debugging the board card to be tested by using the upper computer and the data processing area;

after debugging is finished, the self-correction realization area is reused for carrying out probe self-correction and probe precision self-correction until a test report is obtained;

and powering down the upper computer, the board card to be tested, the logic switch wiring module, the digital multimeter, the oscilloscope, the VRTT Tool and the data processing module according to the power down sequence of the Memory VRTT standard.

Optionally, the performing, by using the self-calibration implementation area, probe self-calibration and probe precision self-calibration includes:

controlling the logic switch wiring module to enter a probe self-correction mode by using the upper computer, and performing probe self-correction by using the interaction of the upper computer, the logic switch wiring module and the oscilloscope;

and controlling the logic switch wiring module to enter a probe precision self-correction mode by using the upper computer, and performing probe precision self-correction by using the interaction of the upper computer, the board card to be detected, the logic switch wiring module, the digital multimeter, the oscilloscope, the VRTT Tool and the data processing module.

Optionally, the upper computer is used for controlling the logic switch wiring module to enter a probe self-correction mode, and interaction of the upper computer, the logic switch wiring module and the oscilloscope is used for probe self-correction, wherein the probe self-correction mode comprises the following steps:

according to the obtained upper computer command, a first logic switch is used for communicating the oscilloscope probe correction module and the differential probe, and the differential probe is completely separated from the board card to be tested;

and the upper computer controls the oscilloscope to start the probe correcting program through the GPIB cable.

Optionally, the upper computer is used to control the logic switch wiring module to enter a probe precision self-correction mode, and the probe precision self-correction is performed by using the interaction of the upper computer, the board card to be detected, the logic switch wiring module, the digital multimeter, the oscilloscope, the VRTT Tool and the data processing module, and the method includes the following steps:

communicating the board card to be tested and the universal digital meter by using the first logic switch and the second logic switch according to the obtained upper computer command;

according to the obtained command, using VRTT Tool to pull and load the set precision error test current;

acquiring a first voltage to be tested of the first test point and a third voltage to be tested of the second test point by using a digital multimeter according to the set precision error test current;

transmitting the first voltage to be measured and the third voltage to be measured to a data processing module through an upper computer;

acquiring a second voltage to be measured of the first test point and a fourth voltage to be measured of the second test point by the oscilloscope through the differential probe according to the acquired command;

transmitting the second voltage to be measured and the fourth voltage to be measured to a data processing module through an upper computer;

calculating a voltage difference value of the first test point according to the first voltage to be tested and the second voltage to be tested by using a formula delta V1-V1-V2, wherein delta V1 is the voltage difference value, V1 is the first voltage to be tested of the first test point, and V2 is the second voltage to be tested of the second test point;

and calculating a voltage difference value of the second test point according to the third voltage to be tested and the fourth voltage to be tested by using a formula of delta V2-V3-V4, wherein delta V2 is the voltage difference value, V3 is the third voltage to be tested of the first test point, and V4 is the fourth voltage to be tested of the second test point.

Optionally, the starting of the initial test according to the command of the upper computer includes:

the upper computer acquires VRTT Tool software through the VRTT Tool;

adjusting parameters in VRTT Tool software according to set test conditions, wherein the parameters comprise: a voltage value for the trigger current;

performing 3D frequency sweep on VRTT dynamic response of Memory output voltage by using the parameters;

according to the frequency sweeping result, the upper computer obtains the frequency and the duty ratio of the maximum value and the minimum value of the two differential probes;

utilizing a self-correction realization area to carry out probe self-correction;

controlling a logic switch wiring module to enter a normal test mode by utilizing an upper computer;

inputting the frequency and the duty ratio into VRTT Tool software and then pulling and loading;

and transmitting the waveforms, the frequencies and the duty ratios of the maximum value and the minimum value of the two differential probes to an upper computer.

Optionally, debugging the board card to be tested by using the upper computer and the data processing area includes:

connecting an upper computer and a board card to be tested by utilizing a PMBUS-Dongle-USB, wherein the upper computer is in communication connection with the data processing area;

running debugging software in the upper computer according to the acquired instruction;

adjusting VR Code in the debugging software according to the obtained instruction, and writing the VR Code into a board card to be tested, wherein the VR Code comprises: PID and nonlinear parameters;

re-entering a probe self-correction mode, and performing self-correction on the differential probe;

restarting the initial test according to the corrected result, and verifying whether dynamic response data pulled by frequencies and duty ratios at the maximum value and the minimum value of the two differential probes obtained in the 3D frequency sweep meet the SPEC standard or not;

if so, according to the obtained upper computer command, the oscilloscope uses the single-ended probe to test the Jitter at the maximum value and the minimum value to obtain Jitter test data;

transmitting the Jitter test data to a data processing module through an upper computer;

judging whether the Jitter test data meet the SPEC standard or not by using a data processing module;

and if not, adjusting the VR Code in the debugging software again according to the acquired command, and writing the VR Code into the board card to be tested until the dynamic response data and the Jitter test data simultaneously meet the SPEC standard.

Optionally, after the dynamic response data and the Jitter test data simultaneously satisfy the SPEC criterion, the method further comprises:

the updated VR Code is utilized, the upper computer is executed again to obtain the VRTT Tool software through the VRTT Tool to execute a normal test mode;

and testing the Jitter at the maximum value and the minimum value by using the single-ended probe by the oscilloscope again according to the obtained upper computer command to obtain Jitter test data until the dynamic response data and the Jitter test data simultaneously meet the SPEC standard

The technical scheme provided by the embodiment of the application can have the following beneficial effects:

the application provides a host computer system for Memory VRTT dynamic response test, and the system mainly comprises: the automatic testing device comprises an upper computer, a board card to be tested, a logic switch wiring module, a digital multimeter, an oscilloscope, a VRTT Tool and a data processing module, wherein the upper computer serves as a host, the board card to be tested, the logic switch wiring module, the digital multimeter, the oscilloscope, the VRTT Tool and the data processing module serve as six slave machines, and the self-correcting Memory VRTT dynamic response automatic test can be realized by controlling the six slave machines through the upper computer. In the present embodiment, six slaves are divided into three areas: a self-calibration realization area, a data acquisition area and a data processing area. The upper computer can adopt different logic switch modes to realize three different state modes through the logic switch wiring module, so that the self-correction of the differential probe and the self-correction of the probe precision are realized, and the accuracy of the Memory VRTT dynamic response test result is effectively improved. The data processing area is processed by the data processing module, VR Code in debugging software can be automatically adjusted, loop PID and nonlinear parameters can be adjusted, the range of trial and error in debugging is reduced, debugging is automatically achieved, and further improvement of testing efficiency and accuracy of testing results is facilitated.

The method comprises the steps of firstly installing an upper computer system to build a test environment, then electrifying the upper computer system, secondly utilizing a self-correction realization area to carry out probe self-correction and probe precision self-correction double correction, starting an initial test after the correction is qualified, then judging whether a test result meets an SPEC Standard, debugging and re-correcting if the test result does not meet the Standard until the test result meets the SPEC (Standard Performance Evaluation Corporation) Standard and a test report is obtained, and finally powering off. The embodiment can realize double correction by utilizing the self-correction realization area, is favorable for improving the accuracy of the test result, can automatically execute the debugging program according to the acquired command when the SPEC standard is not met in the test process, automatically executes re-correction after the debugging is finished, does not need manual adjustment and setting in the whole process, is favorable for improving the accuracy of the test result and improves the test efficiency.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an upper computer system for Memory VRTT dynamic response test according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a logic switch junction module according to an embodiment of the present disclosure;

fig. 3 is a schematic flowchart of a working method of an upper computer system for Memory VRTT dynamic response test according to an embodiment of the present application.

Detailed Description

In order to make those skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

For a better understanding of the present application, embodiments of the present application are explained in detail below with reference to the accompanying drawings.

Example one

Referring to fig. 1, fig. 1 is a schematic structural diagram of a host computer system for Memory VRTT dynamic response test according to an embodiment of the present application. As can be seen from fig. 1, the upper computer system for Memory VRTT dynamic response test in this embodiment mainly includes: the device comprises seven parts, namely an upper computer, a board card to be tested, a logic switch wiring module, a digital multimeter, an oscilloscope, a VRTT Tool and a data processing module. The upper computer is used as a host, and the board card to be tested, the logic switch wiring module, the digital multimeter, the oscilloscope, the VRTT Tool and the data processing module are respectively used as a slave 1, a slave 2, a slave 3, a slave 4, a slave 5 and a slave 6. Six slaves implement three zones: a self-calibration implementation area, a data processing area and a data acquisition area. The board card to be tested, the logic switch wiring module, the digital multimeter and the oscilloscope form a self-correction realization area, the board card to be tested, the oscilloscope and the VRTT Tool form a data acquisition area, and the data processing module forms a data processing area. The data acquisition area and the self-calibration implementation area have cross-overlapped parts. The probe self-correction and the final SPEC probe precision self-correction can be realized through the self-correction realization area, the two corrections are flexibly switched through the logic switch wiring module, the improvement of the test efficiency is facilitated, and the accuracy of the test result can be improved through the double corrections. Moreover, the automatic switching of different correction modes can be realized, the test environment of the former correction mode is prevented from being manually dismantled, the test environment of the latter correction mode is prevented from being rebuilt, a large amount of manual operations of building and dismantling the test environment can be omitted, and therefore the test efficiency is further effectively improved. According to the control command of the upper computer, the logic switch wiring module can be divided into three state modes: the device comprises a normal test mode, a probe self-correction mode and a probe precision self-correction mode. Different state modes can meet different requirements in the testing process. The setting of data acquisition district can realize the reinspection test of initial test and debugging in-process according to the control of host computer, and the adjustment of this testing in-process parameter and the beginning and end of test all are through command control, avoid manual operation, can improve efficiency of software testing greatly.

The data processing area mainly comprises a data processing module which is used for acquiring and processing data from the upper computer, generating a test report and returning the test report to the upper computer when a processing result meets the SPEC standard, and returning an adjusting command to the upper computer when the processing result does not meet the SPEC standard, and the upper computer adjusting a loop PID (Proportional-Integral Derivative) and a nonlinear parameter and re-sending the data until the processing result of the data processing module meets the SPEC standard.

Specifically, after acquiring data from the upper computer, the data processing area integrates and processes the data, and when a processing result meets the SPEC standard, a test report is generated and transmitted back to the upper computer; and when the processing result does not accord with the SPEC standard, returning an adjusting command to the upper computer, testing the dynamic response again after the upper computer tries to adjust the dynamic response according to the adjusting command, the adjusting loop PID and the nonlinear parameter, returning the test data to the data processing area for secondary data processing, adjusting the dynamic response by the upper computer and the data processing module through the coordination mode until the processing result accords with the SPEC standard, and generating a test report and returning the test report to the upper computer.

As can be seen from fig. 1, in this embodiment, the connection modes between the upper computer and the different slaves are different, and the connection relationships between the different slaves are different. Specifically, the upper computer is in communication connection with the board card to be tested through JTAG-USB and PMBUS-Dongle-USB, the upper computer is respectively connected with the logic switch wiring module and the VRTT Tool through USB cables, the upper computer is respectively connected with the digital multimeter, the oscilloscope and the data processing module through GPIB (General-Purpose-voltage Interface Bus) cables, the board card to be tested is connected with the oscilloscope through a differential probe and a single-ended probe, the board card to be tested is connected with the digital multimeter through the logic switch wiring module, the board card to be tested is further connected with the oscilloscope through the logic switch wiring module, and the board card to be tested is connected with the VRTT Tool through the USB cables.

Further, the logic switch connection module in this embodiment includes: the device comprises a single chip microcomputer, a first logic switch and a second logic switch, wherein the single chip microcomputer is in communication connection with an upper computer, one end of the first logic switch is connected with an oscilloscope probe channel through a differential probe, the other end of the logic switch is connected with an oscilloscope correction area, one end of the second logic switch is connected with a digital multimeter, and the other end of the second logic switch is connected with a board to be tested through the first logic switch. The logic switch wiring module is controlled by the single chip microcomputer, the single chip microcomputer is a control component of the logic switch wiring module, and the first logic switch and the second logic switch are execution components. The working principle schematic diagram of the logic switch wiring module can be seen in fig. 2. In fig. 2, the logic switch 1 is a first logic switch, and the logic switch 2 is a second logic switch.

The logic switch wiring module in the embodiment has three state modes: the normal test mode, the probe self-calibration mode and the probe precision self-calibration mode are respectively defined as mode 1, mode 2 and mode 3. As can be seen from fig. 2, in the normal test mode, the host computer controls the slave 2 to enter the mode 1. At this moment, the control of the upper computer to the logic switch wiring module specifically is as follows: logic switch 1: a-2, b-4; logic switch 2: c-5 and d-6.

When the differential probe needs to be corrected, the host computer controls the slave computer 2 to enter the mode 2, and the control of the host computer to the logic switch wiring module is specifically as follows: logic switch 1: a-1, b-3; logic switch 2: the differential probe rod and the oscilloscope correction module are independently connected without control in the connection mode, and the differential probe rod is completely separated from the test point on the board card to be tested, so that the test point can still obtain a reliable correction result when corrected in an electrified state, the accuracy and reliability of the test result can be improved, the electrified state correction can be realized, the shutdown is avoided, and the test efficiency is improved. After the switch wiring mode of the logic switch wiring module is adjusted, the upper computer controls the slave computer 4 to start a probe correction program through a GPIB (general purpose interface bus) line, so that the self-correction of the differential probe is completed.

The precision correction of the differential probe mainly comprises the steps of measuring the voltage V1 and the voltage V2 of the same test point by using a digital multimeter and the differential probe respectively for the precision error test current set by the output pulling load to be tested, calculating the difference value delta V1 between the two test points to be V1-V2, and including the delta V in the final SPEC standard. Due to the two differential probes at the near end and the far end, voltages V3 and V4 at the other test point at two sides can be calculated in the same way, and the difference delta V2 is V3-V4. Because the final SPEC judgment is only influenced by the correction, only one test is needed to be completed for each group of Memory VRTT dynamic response tests, namely the difference values delta V1 and delta V2 of the two difference detecting rods at the near end and the far end are obtained, and the test efficiency is favorably improved. The invention realizes the function through the cooperation of the upper computer, the self-correction realization area, the data acquisition area and the data processing area.

Specifically, when the differential probe precision correction is required, the host computer controls the slave 2 to enter the mode 3, and the switching state is as follows: logic switch 1: a-2, b-4; logic switch 2: c-5 and d-6. In the connection mode of the switch, the switch is connected,

the slave 1 and the digital multimeter, namely the slave 3 are changed from open circuit to open circuit, namely the slave 1 and the slave 3 are communicated through the slave 2. The upper computer controls the slave 5 to pull the set current for the output of the slave 1, at the moment, the slave 3 can measure the voltage V1 to be measured of the slave 1 due to conduction, and transmits the data of V1 back to the upper computer through a GPIB (general purpose interface bus) line, and the upper computer transmits the data to the data processing module of the slave 6; meanwhile, one end of the differential probe is connected with the oscilloscope of the slave 4, the other end of the differential probe is connected with the slave 2, and the differential probe and the slave 1 are in a conducting state at this time, so that the slave 4 can measure the voltage V2 (Mean value) to be measured of the slave 1 through the differential probe, and transmits V2 data back to the upper computer through a GPIB (general purpose interface bus) line, and the upper computer transmits the data to the slave 6; subsequently, from the computer 6, using the obtained data V1 and V2, Δ V1 — V1-V2, and similarly Δ V2 — V3-V4; finally, the slave 6 calculates the data of Δ V1 and Δ V2 into the final SPEC of dynamic response, and saves the SPEC for subsequent test result analysis.

The data acquisition area in this embodiment mainly includes: the board card to be tested, the oscilloscope and the VRTT Tool are mainly used for executing initial test and reinspection test in the debugging process according to the control of the upper computer. The data acquisition area mainly comprises two control logics. Logic 1: initial testing and data acquisition. Logic 2: debugging and rechecking.

Aiming at logic 1, the initial test and data acquisition mainly comprises the following steps:

A1) building a standard test environment, checking the problems of correct connection of equipment, no short circuit of a circuit and the like, and then supplying power to the equipment and the board card to be tested according to a standard power-on sequence;

A2) after electrification, the STBY of the board card to be tested (the slave 1) is electrified, the CPLD of the slave 1 transmits signals to the upper computer through the JTAG-USB interface, the upper computer judges that electrification of the slave 1 is completed, and the upper computer returns a starting signal to the CPLD through the USB-JTAG interface, so that all cores of the slave 1 are electrified, namely, non-STBY (Standby switch) electricity.

A3) And (3) waiting for the self-correction realization area to finish all correction work, namely controlling the slave 2 to enter the mode 2 by the upper computer to finish the correction of the differential probe, and then controlling the slave 2 to enter the mode 3 to finish the correction of the accuracy of the differential probe. After the correction is finished, the slave machine 2 returns the Δ V1 and the Δ V2 obtained in the mode 3 to the upper machine, finally, a signal that the correction is finished is returned to the upper machine, and the slave machine 2 is controlled to enter the mode 1 after the upper machine receives the signal;

A4) the upper computer is connected with the VRTT Tool software, parameters in the software (including a pull load reference corresponding to voltage conversion for determining trigger current) are adjusted according to test conditions until the parameters meet the test conditions, 3D frequency sweeping is completed on VRTT dynamic response of Memory output voltage by using the parameters, and after the frequency sweeping is finished, the upper computer reads the frequency and duty ratio when the maximum value and the minimum value of the probe 1 and the probe 2 in the VRTT Tool software occur;

A5) the upper computer controls the slave computer 2 in the self-correction realization area to enter a mode 2, and corrects the differential probe again; subsequently, the upper computer controls the slave 2 to return to the mode 1; inputting the most significant frequency and duty ratio parameters into a VRTT Tool, then carrying out pull loading, and returning the waveforms and the most significant data of the maximum value and the minimum value of the probe 1 and the probe 2 to an upper computer;

A6) and (3) simultaneously transmitting the waveforms and the data returned in the step (5) and the values of the delta V1 and the delta V2 returned in the step (2) to a data processing module (slave unit 6) by the upper computer to generate an initial test report. If the test result is within the range of the dynamic response SPEC, the test is judged to be finished; and if the test result exceeds the SPEC, continuing to enter a debugging stage.

Aiming at the logic 2, the debugging and the double-check mainly comprise the following steps:

B1) and if the test result exceeds the SPEC, continuing to enter a debugging stage. The PMBUS of the slave 1 is used for connecting the slave 1 and the upper computer through Dongle, and debugging software is operated in the upper computer;

B2) upper computer control software adjusts VR Code, and writes into the slave 1, aiming at dynamic response, usually adjusts loop PID and nonlinear parameter, such as ATR;

B3) after the adjustment is completed, the upper computer control system repeats the step 5 and the step 6 in the logic 1, and verifies whether the dynamic response data pulled by the maximum frequency point (frequency and duty ratio) obtained in the initial 3D frequency sweep meets the SPEC;

B4) when the SPEC is met, the upper computer controls the oscilloscope (the slave 4) to measure the Jitter of the point by using the single-ended probe, the measured data is returned to the upper computer and then transmitted to the slave 6 by the upper computer to judge whether the Jitter meets the SPEC, if the Jitter does not meet the SPEC, the steps B2) and B3) in the logic 2 are repeated, the VR Code is readjusted, and the check is carried out until the dynamic response and the Jitter meet the SPEC at the same time;

B5) and after the SPEC is met, judging that debug is successful, and operating the steps A4) -A6) in the logic 1 and the B4 in the logic 2 again by using the latest VR Code to eliminate the data change possibly caused by the new frequency point obtained by 3D scanning again after adjustment, wherein the change is usually small.

As can be seen from fig. 1, the upper computer system of this embodiment further includes a data processing area, which is mainly used to process and analyze the data transmitted by the upper computer, generate a Pass or Fail report, and transmit the processed report back to the upper computer to serve as a criterion for subsequent actions of the upper computer. The data processing area comprises a data processing module, and the data processing module can be realized by adopting a processor.

The operating logic of the data processing module is as follows:

C1) calculating Δ V1 and Δ V2 to be within SPEC, and assuming that the upper limit of the dynamic response in SPEC is Vu and the lower limit is Vd, the upper limit of the final dynamic response SPEC for the probe 1 is Vuf ═ Vu — Δ V1 and the lower limit Vdf ═ Vd — Δ V1; SPEC is calculated in the same way as probe 1 for probes 2 and Δ 2;

C2) in the initial testing or debugging stage, the measured data transmitted by the upper computer is compared with the SPEC in the report, if the SPEC is not met, the 'SPEC is not met and a test result Fail' signal is returned to the upper computer, and debugging is continued according to the logic 1 and the logic 2 in the data acquisition area; if the SPEC is finally met, the data processing area generates a final test report by using the final test waveform and data, simultaneously generates a Bug analysis and debugging report by using the original test waveform, the original VR Code and the final VR Code after debugging is completed, and returns the test report and the Bug analysis and debugging report to the upper computer;

C3) when the upper computer uses debugging software through Dongle, loop PID and nonlinear parameters meeting dynamic response SPEC theoretically are calculated, the range needing to be tried during debugging is narrowed, possible results are returned to the upper computer, the upper computer uses the debugging software according to the results, and then subsequent operation is carried out.

In summary, the present embodiment adopts the upper computer and the 6 slave computers to set up the self-calibration realization area, the data processing area and the data acquisition area, so as to automatically realize the probe self-calibration and determine the probe precision self-calibration of the final SPEC, thereby greatly improving the test efficiency and the accuracy of the test result. And the data processing area and the data acquisition area are interacted, and a test report is transferred to debugging or directly and automatically output according to different test results, so that the test efficiency is further improved.

Example two

Referring to fig. 3, with reference to fig. 3 based on the embodiments shown in fig. 1 and fig. 2, fig. 3 is a flowchart illustrating an operating method of an upper computer system for Memory VRTT dynamic response test according to an embodiment of the present disclosure. As can be seen from fig. 3, the working method of the upper computer system for Memory VRTT dynamic response test in this embodiment mainly includes the following processes:

s1: and building a test environment.

In this embodiment, an upper computer serving as a host is connected with a board card to be tested serving as a slave, a logic switch wiring module, a digital multimeter, an oscilloscope, a VRTT Tool and a data processing module according to the connection mode shown in fig. 1, and meanwhile, the interactive connection between different slaves is established.

S2: and electrifying the upper computer, the board card to be tested, the logic switch wiring module, the digital multimeter, the oscilloscope, the VRTT Tool and the data processing module according to the electrifying sequence of the Memory VRTT standard.

And after the test environment is built, the equipment and the board card to be tested are powered according to the power-on sequence of the Memory VRTT standard after the equipment is correctly connected and the circuit is not short-circuited, and simultaneously, the module which is not powered in the system is powered.

After the power-on is completed, step S3 is executed: and (4) utilizing a self-correction realization area to carry out probe self-correction and probe precision self-correction.

The self-calibration in this embodiment includes the following two processes:

s31: and the upper computer is used for controlling the logic switch wiring module to enter a probe self-correction mode, and the interaction of the upper computer, the logic switch wiring module and the oscilloscope is used for carrying out probe self-correction.

Specifically, the probe self-correction comprises the following processes:

s311: and according to the obtained upper computer command, the first logic switch is used for communicating the oscilloscope probe correction module and the differential probe, and the differential probe is completely separated from the board card to be tested.

S312: and the upper computer controls the oscilloscope to start the probe correcting program through the GPIB cable.

S32: and controlling the logic switch wiring module to enter a probe precision self-correction mode by using the upper computer, and performing probe precision self-correction by using the interaction of the upper computer, the board card to be detected, the logic switch wiring module, the digital multimeter, the oscilloscope, the VRTT Tool and the data processing module.

Specifically, the probe precision self-correction comprises the following processes:

s321: and communicating the board card to be tested and the universal digital meter by using the first logic switch and the second logic switch according to the acquired upper computer command.

S322: and according to the acquired command, using the VRTT Tool to pull and load the set precision error test current.

S323: and according to the set precision error test current, acquiring a first voltage to be tested of the first test point and a third voltage to be tested of the second test point by using a digital multimeter.

S324: and transmitting the first voltage to be measured and the third voltage to be measured to a data processing module through an upper computer.

S325: and acquiring a second voltage to be measured of the first test point and a fourth voltage to be measured of the second test point by the oscilloscope through the differential probe according to the acquired command.

S326: and transmitting the second voltage to be measured and the fourth voltage to be measured to a data processing module through an upper computer.

S327: and calculating a voltage difference value of the first test point according to the first voltage to be tested and the second voltage to be tested by using a formula of delta V1-V1-V2, wherein delta V1 is the voltage difference value, V1 is the first voltage to be tested of the first test point, and V2 is the second voltage to be tested of the second test point.

S328: and calculating a voltage difference value of the second test point by using a formula delta V2-V3-V4 according to the third voltage to be tested and the fourth voltage to be tested, wherein delta V2 is the voltage difference value, V3 is the third voltage to be tested of the first test point, and V4 is the fourth voltage to be tested of the second test point.

After the correction is completed, step S4 is executed: and starting the initial test according to the command of the upper computer.

Specifically, the initial testing process includes the steps of:

s41: the upper computer acquires VRTT Tool software through the VRTT Tool;

s42: adjusting parameters in VRTT Tool software according to set test conditions, wherein the parameters comprise: a voltage value for the trigger current;

s43: performing 3D frequency sweep on VRTT dynamic response of Memory output voltage by using parameters;

s44: according to the frequency sweeping result, the upper computer obtains the frequency and the duty ratio of the maximum value and the minimum value of the two differential probes;

s45: utilizing a self-correction realization area to carry out probe self-correction;

s46: controlling a logic switch wiring module to enter a normal test mode by utilizing an upper computer;

s47: inputting the frequency and the duty ratio into VRTT Tool software and then pulling and loading;

s48: and transmitting the waveforms, the frequencies and the duty ratios of the maximum value and the minimum value of the two differential probes to an upper computer.

S5: and judging whether the initial test result meets the Memory VRTT dynamic response SPEC standard or not.

If the initial test result meets the Memory VRTT dynamic response SPEC standard, go to step S6: and generating a test report by using the data processing module.

If the initial test result does not meet the Memory VRTT dynamic response SPEC standard, go to step S7: and debugging the board card to be tested by utilizing the upper computer and the data processing area.

Specifically, step S7 includes the following processes:

s70: connecting an upper computer and a board card to be tested by utilizing a PMBUS-Dongle-USB, wherein the upper computer is in communication connection with the data processing area;

through the communication connection between the upper computer and the data processing area, when the test result does not accord with the SPEC standard, the data processing area can timely return a debugging instruction to the upper computer.

S71: running debugging software in the upper computer according to the acquired instruction;

s72: and adjusting the VR Code in the debugging software according to the acquired command, and writing the VR Code into the board card to be tested. Wherein, VR Code includes: PID and non-linear parameters. In the embodiment, multiple times of debugging are adopted, the data processing module is used for recording the codes which are tried to be debugged and writing the codes into the instruction, so that repeated debugging is avoided, and the test efficiency is improved.

S73: re-entering a probe self-correction mode, and performing self-correction on the differential probe;

s74: restarting the initial test according to the corrected result, and verifying whether dynamic response data pulled by frequencies and duty ratios at the maximum value and the minimum value of the two differential probes obtained in the 3D frequency sweep meet the SPEC standard or not;

if the SPEC criterion is satisfied, execute step S75: according to the obtained upper computer command, the oscilloscope uses a single-ended probe to test the Jitter at the maximum value and the minimum value to obtain Jitter test data;

s76: transmitting the Jitter test data to a data processing module through an upper computer;

s77: judging whether the Jitter test data meet the SPEC standard or not by using a data processing module;

if the SPEC criterion is not satisfied, go to step S78: and regulating the VR Code in the debugging software again according to the acquired command, and writing the VR Code into the board card to be tested until the dynamic response data and the Jitter test data simultaneously meet the SPEC standard.

Further, after the dynamic response data and the Jitter test data satisfy the SPEC standard, the method further includes step S79: and re-executing the upper computer to acquire VRTT Tool software through the VRTT Tool by using the updated VR Code to execute a normal test mode.

Returning to the step S75, according to the obtained upper computer command again, the oscilloscope uses the single-ended probe to test the Jitter at the maximum value and the minimum value, and obtains Jitter test data until the dynamic response data and the Jitter test data simultaneously meet the SPEC standard.

And after debugging is finished, returning to the step S3, and reusing the self-correction realization area to perform probe self-correction and probe precision self-correction until a test report is obtained.

After the test report is generated, step S8 is executed: and powering down the upper computer, the board card to be tested, the logic switch wiring module, the digital multimeter, the oscilloscope, the VRTT Tool and the data processing module according to the power down sequence of the Memory VRTT standard.

The parts not described in detail in this embodiment can be referred to the embodiments shown in fig. 1 and fig. 2, and the two embodiments can be referred to each other, and are not described again here.

The above description is merely exemplary of the present application and is presented to enable those skilled in the art to understand and practice the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A host computer system for Memory VRTT dynamic response testing, the system comprising: the device comprises an upper computer, a board to be tested, a logic switch wiring module, a digital multimeter, an oscilloscope, a VRTT Tool and a data processing module, wherein the board to be tested, the logic switch wiring module, the digital multimeter and the oscilloscope form a self-correction realization area, the board to be tested, the oscilloscope and the VRTT Tool form a data acquisition area, the data processing module forms a data processing area, the upper computer is in communication connection with the board to be tested through JTAG-USB and PMBUS-Dongle-USB, the upper computer is respectively connected with the logic switch wiring module and the VRTT Tool through USB cables, the upper computer is respectively connected with the digital multimeter, the oscilloscope and the data processing module through GPIB cables, the board to be tested is connected with the oscilloscope through a differential probe rod and a single-ended probe rod, the board to be tested is connected with the digital multimeter through the logic switch wiring module, the board to be tested is also connected with the oscilloscope through the logic switch, the board card to be tested is connected with the VRTT Tool through a USB cable;

2. The host computer system for Memory VRTT dynamic response testing of claim 1, wherein the logic switch wiring module comprises: the device comprises a single chip microcomputer, a first logic switch and a second logic switch, wherein the single chip microcomputer is in communication connection with an upper computer, one end of the first logic switch is connected with an oscilloscope probe channel through a differential probe, the other end of the logic switch is connected with an oscilloscope correction area, one end of the second logic switch is connected with a digital multimeter, and the other end of the second logic switch is connected with a board to be tested through the first logic switch.

3. An operating method of an upper computer system for Memory VRTT dynamic response testing, the operating method being applied to the upper computer system for Memory VRTT dynamic response testing described in claim 1 or 2, the operating method comprising:

building a test environment;

starting an initial test according to a command of an upper computer;

if yes, generating a test report by using a data processing module;

4. The operating method of the upper computer system for Memory VRTT dynamic response testing of claim 3, wherein the performing of probe self-calibration and probe accuracy self-calibration by using the self-calibration implementation area comprises:

5. The working method of the upper computer system for Memory VRTT dynamic response testing of claim 4, wherein the upper computer is used to control the logic switch wiring module to enter a probe self-correction mode, and interaction of the upper computer, the logic switch wiring module and an oscilloscope is used to perform probe self-correction, comprising:

6. The operating method of the upper computer system for Memory VRTT dynamic response testing according to claim 4, wherein the upper computer is used to control the logic switch wiring module to enter a probe precision self-correction mode, and the probe precision self-correction is performed by using the interaction of the upper computer, the board card to be tested, the logic switch wiring module, the digital multimeter, the oscilloscope, the VRTT Tool and the data processing module, and comprises the following steps:

7. The operating method of the upper computer system for Memory VRTT dynamic response test according to claim 4, wherein the starting of the initial test according to the command of the upper computer comprises:

the upper computer acquires VRTT Tool software through the VRTT Tool;

8. The operating method of the upper computer system for Memory VRTT dynamic response test according to claim 7, wherein the debugging the board to be tested by using the upper computer and the data processing area includes:

9. The operating method of the upper computer system for Memory VRTT dynamic response testing of claim 8, wherein after the dynamic response data and the Jitter test data simultaneously satisfy the SPEC standard, the method further comprises:

and testing the Jitter at the maximum value and the minimum value by using the single-ended probe by the oscilloscope according to the obtained upper computer command again to obtain Jitter test data until the dynamic response data and the Jitter test data simultaneously meet the SPEC standard.