CN112885849B - Display panel and display device - Google Patents

Display panel and display device Download PDF

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Publication number
CN112885849B
CN112885849B CN202110127089.8A CN202110127089A CN112885849B CN 112885849 B CN112885849 B CN 112885849B CN 202110127089 A CN202110127089 A CN 202110127089A CN 112885849 B CN112885849 B CN 112885849B
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layer
display panel
flexible substrate
film transistor
semiconductor layer
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CN112885849A (en
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杲皓冉
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Abstract

The invention provides a display panel and a display device. The display panel comprises a flexible substrate and a thin film transistor layer arranged on the flexible substrate; and a positively charged first semiconductor layer is arranged between the flexible substrate and the thin film transistor layer. According to the invention, the positively charged first semiconductor layer is arranged between the flexible substrate and the thin film transistor layer, and the positively charged first semiconductor layer can repel the diffusion of positively charged impurity particles in the flexible substrate, so that the positively charged impurity particles cannot enter the interface between polycrystalline silicon in the thin film transistor layer and the grid electrode insulating layer, and the negative bias temperature instability effect of the thin film transistor layer is effectively improved.

Description

Display panel and display device
Technical Field
The invention relates to the technical field of display, in particular to a display panel and a display device.
Background
Since the P-type MOS (Metal-Oxide-Semiconductor) Transistor has a simple circuit process and a Low price, it is widely used in a Thin Film Transistor (TFT) device of LTPS (Low Temperature polysilicon). In the actual use process, due to the influence of the gate electric field, the ambient Temperature and other factors, the absolute value of the threshold voltage of the TFT device is increased, the carrier mobility is reduced, the transconductance is reduced, and the on-state current is reduced, that is, the NBTI (Negative Bias Temperature Instability) effect is an important cause of the TFT device failure.
In the prior art, a flexible substrate is usually adopted as a substrate base plate of a bendable display panel, and experiments show that the NBTI effect of the TFT device adopting the flexible substrate is more remarkable than that of a TFT device with a glass substrate. According to the current research, the main reasons causing the NBTI effect are that silicon-hydrogen bonds (Si-H) on the surface of polycrystalline silicon are broken under the action of gate voltage and high temperature, H atoms escape, Si dangling bonds are generated, and interface traps are formed, so that the NBTI effect occurs. When the flexible substrate is adopted, positive ions in the flexible substrate are diffused to the interface of the polycrystalline silicon and the grid insulating layer under the action of a grid electric field and are captured by an interface trap, so that the NBTI effect is aggravated, and the TFT device is caused to lose efficacy. Therefore, it is necessary to improve this defect.
Disclosure of Invention
The embodiment of the invention provides a display panel, which is used for solving the technical problem that in the display panel in the prior art, a flexible substrate is used as a substrate, but positive ions in the flexible substrate can be diffused to a thin film transistor layer, so that the thin film transistor layer fails.
The embodiment of the invention provides a display panel, which comprises a flexible substrate and a thin film transistor layer arranged on the flexible substrate; and a positively charged first semiconductor layer is arranged between the flexible substrate and the thin film transistor layer.
In the display panel provided in the embodiment of the present invention, the display panel further includes a barrier layer disposed on the flexible substrate, and a first buffer layer disposed on the barrier layer, wherein the first semiconductor layer is disposed between the barrier layer and the first buffer layer.
In the display panel provided in the embodiment of the present invention, the display panel further includes a barrier layer disposed on the flexible substrate, a first buffer layer disposed on the barrier layer, and a second buffer layer disposed on the first buffer layer, wherein the first semiconductor layer is disposed between the first buffer layer and the second buffer layer.
In the display panel provided in the embodiment of the present invention, the display panel further includes a second semiconductor layer, and the second semiconductor layer is disposed between the barrier layer and the first buffer layer.
In the display panel provided by the embodiment of the invention, the second semiconductor layer is positively charged.
In the display panel provided by the embodiment of the invention, the display panel further includes a power line, and the first semiconductor layer is electrically connected to the power line through the first via hole.
In the display panel provided by the embodiment of the invention, the thin film transistor layer is a P-type metal oxide semiconductor transistor layer.
In the display panel provided in the embodiment of the invention, the first semiconductor layer is a P-type semiconductor layer.
In the display panel provided by the embodiment of the invention, the P-type semiconductor layer is doped with boron ions.
The embodiment of the invention also provides a display device which comprises the display panel.
Has the beneficial effects that: according to the display panel and the display device provided by the embodiment of the invention, the positively charged first semiconductor layer is arranged between the flexible substrate and the thin film transistor layer, and the positively charged first semiconductor layer can repel the diffusion of positively charged impurity particles in the flexible substrate, so that the positively charged impurity particles cannot enter the interface between polycrystalline silicon in the thin film transistor layer and the grid insulation layer, and the negative bias temperature instability effect of the thin film transistor layer is effectively improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below.
Fig. 1 is a schematic diagram of a basic structure of a display panel according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a basic structure of another display panel according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a basic structure of another display panel according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of a basic structure of another display panel according to an embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. In the drawings, the size and thickness of components illustrated in the drawings are not to scale for clarity and ease of understanding and description.
As shown in fig. 1, a basic structure of a display panel according to an embodiment of the present invention includes a flexible substrate 10, a thin-film transistor layer 20 disposed on the flexible substrate 10; a positively charged first semiconductor layer 30 is disposed between the flexible substrate 10 and the thin-film transistor layer 20.
The flexible substrate 10 is an organic thin film made of carbon, hydrogen, or the like, such as polyimide. The polyimide is mainly synthesized from dicarboxylic anhydride and diamine, has excellent mechanical property and dielectric property, and can keep flexibility and bendability.
It should be noted that the thin-film transistor layer 20 specifically includes: an active layer 201, a first gate insulating layer 202, a first gate layer 203, a second gate insulating layer 204, a second gate layer 205, an interlayer insulating layer 206, and a source/drain metal layer 207. Wherein the active layer 201 comprises an n-type substrate 2011 and a p-channel 2012; the first gate insulating layer 202 is positioned above the flexible substrate 10 and covers the active layer 201; the first gate layer 203 is located over the first gate insulating layer 202; the second gate insulating layer 204 is located over the first gate insulating layer 202 and covers the first gate layer 203; the second gate layer 205 is located over the second gate insulating layer 204; the interlayer insulating layer 206 is located on the second gate insulating layer 204 and covers the second gate layer 205; the source/drain metal layer 207 is disposed on the interlayer insulating layer 206 and electrically connected to the p-channel 2012 of the active layer 201 through a via hole, the via hole penetrates through the interlayer insulating layer 206, the second gate insulating layer 204 and a portion of the first gate insulating layer 202, and the source/drain metal layer 207 includes a source 2071 and a drain 2072.
In an embodiment, the second gate layer 205 is ac grounded, and the embodiment of the invention may perform an electrostatic shielding function by disposing the second gate layer 205 between the first gate layer 203 and the source/drain metal layer 207, so as to reduce a parasitic capacitance between the first gate layer 203 and the source/drain metal layer 207.
In one embodiment, the thin-film transistor layer 20 is a P-type metal-oxide-semiconductor transistor layer. It is understood that the P-type metal oxide semiconductor transistor layer is used for transmitting current by the flowing of holes. Wherein, when not powered, the source 2071 and the drain 2072 are not conductive; when a sufficient positive voltage is applied to the source 2071 (the first gate layer 203 is grounded), a p-type inversion layer appears on the surface of the n-type substrate 2011 under the first gate layer 203, which becomes a channel connecting the source 2071 and the drain 2072. That is, the P-type metal oxide semiconductor transistor layer can be turned on or off by controlling a voltage difference between the source 2071 and the first gate layer 203.
It can be understood that, since the pmos transistor layer is an n-type substrate 2011, the majority carriers are electrons, the minority carriers are holes, and the doping type of the contact region corresponding to the source/drain metal layer 207 is P-type (i.e., P-channel 2012), the operating condition of the pmos transistor layer is that a negative voltage is applied on the first gate layer 203 relative to the source 2071, i.e., negative charge electrons are applied on the first gate layer 203, and if the display panel is in a high temperature environment, Negative Bias Temperature Instability (NBTI) effect is caused, which may cause an increase in the absolute value of the threshold voltage of the thin-film transistor layer 20, a decrease in the carrier mobility, a decrease in transconductance, and a decrease in the on-state current, resulting in a failure of the thin-film transistor layer 20.
Specifically, after applying negative bias and temperature stress to thin-film transistor layer 20, Si and SiO in thin-film transistor layer 20 2 The following electrochemical reaction model occurs at the interface and within the oxide layer: this model assumes that some species Y diffuses into Si and SiO 2 The interface and Si-H bond are subjected to electrochemical reaction to generate an interface state Si ≡ Si & and an unknown substance X, Si ≡ SiH + Y → Si ≡ Si ● + X, namely, a silicon-hydrogen bond (Si-H) is broken under the effects of gate voltage and high temperature, H atoms are escaped, a dangling bond of Si is generated, and an interface trap is formed.
In summary, Si and SiO 2 Is the primary cause of failure of thin-film-transistor layer 20. Specifically, the thin-film transistor layer 20 fails due to the generation and passivation of positive charges, i.e., the formation of interface states (interface traps), during the NBTI effect. Wherein, under high temperature and negative gate pressure, the cavity of the inversion layer of the thin film transistor layer 20 is thermally excited to tunnel into Si and SiO 2 Due to the presence of a large number of Si-H bonds at the interface, the thermally excited holes react with the Si-H bonds under certain conditions to form H atomsSeed, H + Or a substance containing H, thereby leaving a dangling bond of Si at the interface, and H atoms, H + Or instability of H-containing substances, H atoms, H + Or the H-containing substance diffuses away from the interface of the active layer 201 toward the interface of the first gate layer 203, thereby generating interface defects and positive charges. In addition, SiO 2 Will result in a reduction of the number of majority carriers (holes) in the inversion layer due to the generation of positive charges, SiO 2 The generation of positive charges in (b) will create an electric field opposite to the gate voltage electric field, which may impair the performance of the thin-film transistor layer 20 (e.g., increase in absolute value of threshold voltage, decrease in carrier mobility, decrease in transconductance, decrease in on-state current, etc.), and over time, may cause the thin-film transistor layer 20 to fail.
By treating the surface of the active layer 201 and replacing silicon-hydrogen (Si-H) bonds with silicon-fluorine (Si-F) bonds or silicon-deuterium (Si-D) bonds, the silicon-hydrogen bonds (Si-H) can be improved to be broken under the gate voltage and high temperature, H atoms escape, Si dangling bonds are generated, interface traps are formed, and therefore the Negative Bias Temperature Instability (NBTI) effect is caused. Specifically, the fluorine or deuterium has a stronger bonding force with a silicon atom and is not easily broken. However, if the flexible substrate 10 is used as a substrate of a display panel, the flexible substrate 10 may also be decomposed and generate positive ions under the influence of a gate voltage and a high temperature, and the positive ions may diffuse in the direction of the thin-film transistor layer 20, which further aggravates a Negative Bias Temperature Instability (NBTI) effect. In the embodiment of the present invention, the positively charged first semiconductor layer 30 is disposed between the flexible substrate 10 and the thin film transistor layer 20, and the positively charged first semiconductor layer 30 can repel diffusion of positively charged impurity particles in the flexible substrate 10, so that the positively charged impurity particles cannot enter an interface between the active layer 201 and the first gate insulating layer 202, thereby effectively improving a Negative Bias Temperature Instability (NBTI) effect of the thin film transistor layer 20.
In one embodiment, the first semiconductor layer 30 is a P-type semiconductor layer. That is, the first semiconductor layer 30 is an impurity semiconductor having a hole concentration much greater than a free electron concentration. The method for forming the first semiconductor layer 30 includes: and doping trivalent elements into the pure silicon crystal to replace the bits of the silicon atoms in the crystal lattice so as to form the P-type semiconductor. The holes are mainly provided by impurity atoms, free electrons are formed by thermal excitation, the more impurity atoms are doped, the higher the concentration of majority (holes) is, and the stronger the conductivity is.
In one embodiment, the P-type semiconductor layer is doped with boron ions. In the embodiment of the invention, boron ions are adopted to heavily dope the first semiconductor layer 30 to form a P-type semiconductor, and the heavily doped P-type semiconductor layer contains a plurality of positive electric centers, which can repel the diffusion of positively charged impurity particles in the flexible substrate 10, so that the positively charged impurity particles cannot enter the interface between the active layer 201 and the first gate insulating layer 202, thereby effectively improving the Negative Bias Temperature Instability (NBTI) effect of the thin film transistor layer 20.
The P-type semiconductor layer is doped with boron ions, which form a plurality of positive electric centers in the P-type semiconductor layer, but due to the high-temperature activation process, the boron ions are tightly bonded to surrounding silicon atoms and are not diffused by the gate electric field.
In one embodiment, the display panel further includes a barrier layer 40 disposed on the flexible substrate 10, and a first buffer layer 50 disposed on the barrier layer 40, wherein the first semiconductor layer 30 is disposed between the barrier layer 40 and the first buffer layer 50. The barrier layer 40 and the first buffer layer 50 both function to prevent water and oxygen from entering the external environment to cause the thin-film transistor layer 20 to fail.
In one embodiment, a planarization layer 208 is disposed on the interlayer insulating layer 206 and the source/drain metal layer 207, and a pixel defining layer 209 is disposed on the planarization layer 208. The planarization layer 208 functions to eliminate a height difference between the interlayer insulating layer 206 and the source/drain metal layer 207, and the pixel defining layer 209 functions to define a pixel region for subsequent preparation of an organic light emitting material to form a light emitting function layer (not shown). The method for preparing the organic luminescent material is ink-jet printing or evaporation.
Referring to fig. 2, a basic structure of another display panel according to an embodiment of the present invention is shown, where the display panel includes a flexible substrate 10, a thin film transistor layer 20 disposed on the flexible substrate 10, and a positively charged first semiconductor layer 30 disposed between the flexible substrate 10 and the thin film transistor layer 20.
The display panel further includes a power line 2073, and the first semiconductor layer 30 is electrically connected to the power line 2073 through a first via hole.
The flexible substrate 10 is an organic thin film made of carbon, hydrogen, or the like, such as polyimide. The polyimide is mainly synthesized from dicarboxylic anhydride and diamine, has excellent mechanical property and dielectric property, and can keep flexibility and bendability.
It should be noted that the thin-film transistor layer 20 specifically includes: an active layer 201, a first gate insulating layer 202, a first gate layer 203, a second gate insulating layer 204, a second gate layer 205, an interlayer insulating layer 206, and a source/drain metal layer 207. Wherein the active layer 201 comprises an n-type substrate 2011 and a p-channel 2012; the first gate insulating layer 202 is positioned above the flexible substrate 10 and covers the active layer 201; the first gate layer 203 is located over the first gate insulating layer 202; the second gate insulating layer 204 is located over the first gate insulating layer 202 and covers the first gate layer 203; the second gate layer 205 is located over the second gate insulating layer 204; the interlayer insulating layer 206 is located on the second gate insulating layer 204 and covers the second gate layer 205; the source/drain metal layer 207 is disposed on the interlayer insulating layer 206 and electrically connected to the p-channel 2012 of the active layer 201 through a via hole, the via hole penetrates through the interlayer insulating layer 206, the second gate insulating layer 204 and a portion of the first gate insulating layer 202, and the source/drain metal layer 207 includes a source 2071 and a drain 2072.
It can be understood that, the power line 2073 provides a positive potential for the display panel, and the embodiment of the invention electrically connects the first semiconductor layer 30 to the power line 2073 through the first via hole, so that the first semiconductor layer 30 is constantly positively charged, which can repel the diffusion of the positively charged impurity particles in the flexible substrate 10 and make them unable to enter the interface between the active layer 201 and the first gate insulating layer 202, thereby effectively improving the Negative Bias Temperature Instability (NBTI) effect of the thin film transistor layer 20.
In one embodiment, the power line 2073 may be fabricated in the same layer as the source/drain metal layer 207 of the thin-film transistor layer 20.
In one embodiment, the first semiconductor layer 30 is a P-type semiconductor layer. Wherein the P-type semiconductor layer is doped with boron ions. In the embodiment of the present invention, on the basis that the first semiconductor layer 30 is electrically connected to the power line 2073 through the first via hole, boron ions are further adopted to heavily dope the first semiconductor layer 30 to form a P-type semiconductor, and the heavily doped P-type semiconductor layer contains a plurality of positive electrical centers, which can repel the diffusion of positively charged impurity particles in the flexible substrate 10, so that the positively charged impurity particles cannot enter the interface between the active layer 201 and the first gate insulating layer 202, thereby further improving the Negative Bias Temperature Instability (NBTI) effect of the thin film transistor layer 20.
Referring to fig. 3, a basic structure of another display panel according to an embodiment of the present invention is shown, where the display panel includes a flexible substrate 10, a thin film transistor layer 20 disposed on the flexible substrate 10, and a positively charged first semiconductor layer 30 disposed between the flexible substrate 10 and the thin film transistor layer 20.
The display panel further includes a barrier layer 40 disposed on the flexible substrate 10, a first buffer layer 50 disposed on the barrier layer 40, and a second buffer layer 60 disposed on the first buffer layer 50, wherein the first semiconductor layer 30 is disposed between the first buffer layer 50 and the second buffer layer 60.
In one embodiment, the first buffer layer 50 is made of a silicon nitride material, and the second buffer layer 60 is made of a silicon oxide material.
It should be noted that moisture in the external environment is also one of the causes of the NBTI effect, and the NBTI effect can be reduced by trying to reduce the content of moisture in the display panel. In the embodiment of the present invention, the first buffer layer 50 and the second buffer layer 60 are disposed on the flexible substrate 10, so that the diffusion of water vapor can be effectively prevented.
Referring to fig. 4, a basic structure diagram of another display panel according to an embodiment of the present invention includes a flexible substrate 10, a barrier layer 40 disposed on the flexible substrate 10, a first buffer layer 50 disposed on the barrier layer 40, a second buffer layer 60 disposed on the first buffer layer 50, a first semiconductor layer 30 disposed between the first buffer layer 50 and the second buffer layer 60, and a thin film transistor layer 20 disposed on the second buffer layer 60.
Wherein the display panel further comprises a second semiconductor layer 70, and the second semiconductor layer 70 is disposed between the barrier layer 40 and the first buffer layer 50.
In one embodiment, the second semiconductor layer 70 is positively charged. It is understood that the second semiconductor layer 70 is positively charged, which can repel the diffusion of the positively charged impurity particles in the flexible substrate 10 from entering the interface between the active layer 201 and the first gate insulating layer 202, thereby further improving the Negative Bias Temperature Instability (NBTI) effect of the thin film transistor layer 20.
The embodiment of the invention also provides a display device which comprises a driving chip and the display panel. The display device provided by the embodiment of the invention can be as follows: products or components with display functions such as mobile phones, tablet computers, televisions, displays, notebook computers, digital cameras, navigators and the like.
In summary, according to the display panel and the display device provided in the embodiments of the present invention, the positively charged first semiconductor layer is disposed between the flexible substrate and the thin film transistor layer, and the positively charged first semiconductor layer can repel diffusion of positively charged impurity particles in the flexible substrate, so that the positively charged impurity particles cannot enter an interface between polysilicon in the thin film transistor layer and the gate insulating layer, thereby effectively improving a negative bias temperature instability effect of the thin film transistor layer, and solving a technical problem that in a display panel in the prior art, positive ions in the flexible substrate can diffuse into the thin film transistor layer, which causes failure of the thin film transistor layer, because the flexible substrate is used as the substrate.
The display panel and the display device provided by the embodiments of the present invention are described in detail above. It should be understood that the exemplary embodiments described herein should be considered merely as illustrative, for facilitating the understanding of the method of the present invention and its core ideas, and not as limiting the present invention.

Claims (10)

1. The display panel is characterized by comprising a flexible substrate and a thin film transistor layer arranged on the flexible substrate;
and a positively charged first semiconductor layer is arranged between the flexible substrate and the thin film transistor layer.
2. The display panel of claim 1, further comprising a barrier layer disposed over the flexible substrate, a first buffer layer disposed over the barrier layer, wherein the first semiconductor layer is disposed between the barrier layer and the first buffer layer.
3. The display panel of claim 1, further comprising a barrier layer disposed over the flexible substrate, a first buffer layer disposed over the barrier layer, a second buffer layer disposed over the first buffer layer, wherein the first semiconductor layer is disposed between the first buffer layer and the second buffer layer.
4. The display panel of claim 3, further comprising a second semiconductor layer disposed between the barrier layer and the first buffer layer.
5. The display panel according to claim 4, wherein the second semiconductor layer is positively charged.
6. The display panel according to claim 2 or 3, wherein the display panel further comprises a power supply line, and the first semiconductor layer is electrically connected to the power supply line through a first via hole.
7. The display panel of claim 1, wherein the thin-film transistor layer is a P-type metal-oxide-semiconductor transistor layer.
8. The display panel according to claim 7, wherein the first semiconductor layer is a P-type semiconductor layer.
9. The display panel according to claim 8, wherein the P-type semiconductor layer is doped with boron ions.
10. A display device characterized by comprising the display panel according to any one of claims 1 to 9.
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