CN105374684A - PMOS structure and formation method thereof - Google Patents
PMOS structure and formation method thereof Download PDFInfo
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- CN105374684A CN105374684A CN201410438476.3A CN201410438476A CN105374684A CN 105374684 A CN105374684 A CN 105374684A CN 201410438476 A CN201410438476 A CN 201410438476A CN 105374684 A CN105374684 A CN 105374684A
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Abstract
The invention provides a PMOS structure and a formation method thereof. The formation method of the PMOS structure includes: a semiconductor substrate is provided, and a grid electrode structure and side walls positioned on sidewalls of two sides of the grid electrode structure are formed on the surface of the semiconductor substrate; the grid electrode structure and the side walls are regarded as masks, and grooves are formed at two sides of the side walls in the semiconductor substrate; germanium silicon seeding layers are formed on the surfaces of the bottom surfaces and side surfaces of the grooves, and the germanium silicon seeding layers are doped with fluorinions; and silicon germanium body layers are formed on the silicon germanium seeding layers, and remaining portions of the grooves are filled with the silicon germanium body layers. The fluorinions and silicon have strong bonding force, the germanium silicon seeding layers are doped with the fluorinions so that the transferred electron effect can be reduced, and the diffusion of P-type ions is prevented; besides, through the doping of the fluorinions, the stability of the device can be improved, and the negative bias temperature instability and the hot carrier injection effect are improved.
Description
Technical field
The present invention relates to semiconductor applications, particularly relate to a kind of PMOS structure and forming method thereof.
Background technology
Along with the fast development of ic manufacturing technology, the technology node of semiconductor device is in continuous reduction, and the physical dimension of device is also followed Moore's Law and constantly reduced.When dimensions of semiconductor devices is reduced to a certain degree, the various problems brought close to physics limit by semiconductor device occur in succession.Conventional source-drain area structure cannot meet the requirement grown to even greater heights to the device speed of service, has thus occurred the embedded germanium silicon technology (EmbeddedSiGetechnology) in order to improve PMOS electric property.This technology is by embedding germanium silicon layer in the substrate in PMOS source drain region, utilize the stress that between germanium silicon layer and substrate silicon, lattice mismatch produces channel region, improve the mobility of charge carrier (hole), and then improve drive current, improve the electric property of PMOS.
In the prior art, the boron ion of PMOS source drain region embedded germanium silicon situ doping, easily diffuse into raceway groove when annealing, and embedded germanium silicon layer on silicon/germanium silicon interface due to the defect that lattice mismatch produces, boron ion can be made more serious to the diffusion of raceway groove.Such phenomenon can cause gate current to increase, thus causes PMOS electric property to drift about.
In addition, in order to pursue the stress loading to PMOS raceway groove large as far as possible, the embedded germanium silicon layer general distance raceway groove being formed at source-drain area is very near, germanium ion will be caused like this to spread in raceway groove, change the doped structure of raceway groove, not only change hole migration speed, also make the total electrical charge quantity in raceway groove change, greatly reduce the electric property of PMOS.
Summary of the invention
When the problem that the present invention solves is the embedded germanium silicon layer forming PMOS structure, in-situ doped boron ion diffuse enters the problem that PMOS gate current increases, electric property declines that raceway groove causes, and the germanium ion diffusion in embedded germanium silicon layer, cause hot carrier injection effect and Negative Bias Temperature Instability to worsen, cause the problem that device stability declines.
For solving the problem, the invention provides a kind of formation method of PMOS structure, comprising: provide Semiconductor substrate, described semiconductor substrate surface is formed with grid structure and is positioned at the side wall on the sidewall of described grid structure both sides; With described grid structure and side wall for mask, in Semiconductor substrate described in side wall both sides, form groove; Form germanium silicon kind crystal layer in described trench bottom surfaces and side surface, described germanium silicon kind crystal layer is doped with fluorine ion; Described SiGe kind crystal layer forms SiGe body layer, and described SiGe body layer fills the remainder of full described groove, and described germanium silicon body layer contains Doped ions.
Optionally, the method forming described germanium silicon kind crystal layer is selective epitaxial growth process, and the temperature of described selective epitaxial growth process is 500 DEG C ~ 800 DEG C, and air pressure is that 1 holder ~ 100 are held in the palm, and reacting gas comprises silicon source gas and germanium source gas, and silicon source gas is SiH
4or SiH
2cl
2, germanium source gas is GeH
4, the flow of described silicon source gas and germanium source gas is 1 mark condition milliliter per minute ~ 1000 mark condition milliliter per minute.
Optionally, in described germanium silicon kind crystal layer, the mass ratio of Ge element is 1% ~ 30%, and the thickness of described germanium silicon kind crystal layer is
Optionally, in described germanium silicon kind crystal layer, the method for doped with fluorine ion is in-situ doped technique.
Optionally, in described germanium silicon kind crystal layer, the in-situ doped technique of doped with fluorine ion is: add fluorine source gas BF when forming the selective epitaxial growth process of described germanium silicon kind crystal layer
3or F
2, described fluorine source gas flow is concentration is 1 mark condition milliliter per minute ~ 100 mark condition milliliter per minute.
Optionally, in described germanium silicon kind crystal layer, the doping content of fluorine ion is 1 × 10
18atom/cm
3~ 1 × 10
21atom/cm
3.
Optionally, the method forming the germanium silicon body layer of filling full described groove remainder is selective epitaxial growth process, and the temperature of described selective epitaxial growth process is 500 DEG C ~ 800 DEG C, and air pressure is that 1 holder ~ 100 are held in the palm, reacting gas comprises silicon source gas and germanium source gas, and silicon source gas is SiH
4or SiH
2cl
2, germanium source gas is GeH
4, the flow of described silicon source gas and germanium source gas is 1 mark condition milliliter per minute ~ 1000 mark condition milliliter per minute.
Optionally, in described germanium silicon body layer, the mass ratio of Ge element is 30% ~ 50%, and the Doped ions that described germanium silicon body layer contains is boron ion.
Optionally, be in-situ doped technique in the method for described germanium silicon body layer doped with boron ion, described in-situ doped technique is: add boron source gas when forming the selective epitaxial growth process of described germanium silicon body layer, and boron source gas flow is 1 mark condition milliliter per minute ~ 1000 mark condition milliliter per minute.
Optionally, described boron source gas is B
2h
6, BH
3or BCl
3.
Optionally, described grid structure comprises the gate dielectric layer be positioned on described Semiconductor substrate and the grid layer be positioned on described gate dielectric layer.
Optionally, described spacer material is silicon nitride, silicon oxynitride or silica.
Optionally, described groove is U-shaped or Sigma type, and depth bounds is
Present invention also offers a kind of PMOS structure, comprising: Semiconductor substrate, the grid structure being positioned at described semiconductor substrate surface and the side wall be positioned on the sidewall of described grid structure both sides; Be arranged in the groove of described side wall semiconductor substrates on two sides; Be positioned at the germanium silicon kind crystal layer of described trench bottom surfaces and side surface, described germanium silicon kind crystal layer is doped with fluorine ion; Be positioned at the SiGe body layer on SiGe kind crystal layer, described SiGe body layer fills the remainder of full described groove, and described germanium silicon body layer contains Doped ions.
Optionally, in described germanium silicon kind crystal layer, the mass ratio of Ge element is 1% ~ 30%, and the thickness of described germanium silicon kind crystal layer is
Optionally, in described germanium silicon kind crystal layer, the doping content of fluorine ion is 1 × 10
18atom/cm
3~ 1 × 10
21atom/cm
3.
Optionally, in described germanium silicon body layer, the mass ratio of Ge element is 30% ~ 50%, and the Doped ions that described germanium silicon body layer contains is boron ion.
Optionally, described grid structure comprises the gate dielectric layer be positioned on described Semiconductor substrate and the grid layer be positioned on described gate dielectric layer.
Optionally, described spacer material is silicon nitride, silicon oxynitride or silica.
Optionally, described groove is U-shaped or Sigma type, and depth bounds is
Compared with prior art, technical scheme of the present invention has the following advantages:
The formation method of PMOS structure of the present invention, by first forming the germanium silicon kind crystal layer doped with fluorine ion in PMOS source drain region, form the method for germanium silicon body layer again, utilize fluorine ion and the powerful bonding force of silicon atom, in germanium silicon kind crystal layer, form potential barrier barrier, reduce transferred electron effect, reduce the diffusion probability of boron ion or germanium ion in germanium silicon body layer, the stability of device can be improved, improve Negative Bias Temperature Instability and hot carrier injection effect.In addition, the not doped with fluorine ion in germanium silicon body layer at germanium silicon kind crystal layer, ensure that while formation potential barrier barrier reduces transferred electron effect, device source leakage current will being caused to reduce because adulterating a large amount of fluorine ion in source-drain area, affecting device electric property.
Further, the thickness of described germanium silicon kind crystal layer is
the ratio of Ge element quality is 1% ~ 30%, and the doping content of fluorine ion is 1 × 10
18atom/cm
3~ 1 × 10
21atom/cm
3, while guarantee applies enough large stress to raceway groove, and effectively can reduce the diffusion probability of boron ion or germanium ion in germanium silicon body layer.
PMOS structure of the present invention, contains the groove, the germanium silicon kind crystal layer doped with fluorine ion and the germanium silicon body layer doped with boron ion that are arranged in side wall semiconductor substrates on two sides.The described germanium silicon kind crystal layer doped with fluorine ion is positioned at described trench bottom surfaces and side surface, and the germanium silicon body layer doped with boron ion is positioned on described germanium silicon kind crystal layer also fills full groove remainder, and described germanium silicon body layer end face flushes with semiconductor substrate surface.Doped with in the germanium silicon kind crystal layer of fluorine ion, make use of fluorine ion and the powerful bonding force of silicon atom forms potential barrier barrier, reduce transferred electron effect, reduce the diffusion probability of boron ion or germanium ion, the stability of device can be improved, improve Negative Bias Temperature Instability and hot carrier injection effect.
Accompanying drawing explanation
Fig. 1 to Fig. 5 is the cross-sectional view of the forming process of one embodiment of the invention PMOS structure;
Fig. 6 to Fig. 9 is the cross-sectional view of the forming process of another embodiment of the present invention PMOS structure.
Embodiment
From background technology, there is the problem of electric property drift and electric property decline in the PMOS structure that prior art processes is formed.For this reason, described semiconductor device and formation process thereof are studied, when finding that carrying out selective epitaxial growth in PMOS source drain region forms embedded germanium silicon layer, in-situ doped boron ion can spread in follow-up annealing process, increases grid current and causes PMOS electric property to drift about.Germanium ion in germanium silicon layer also can diffuse into raceway groove, not only change hole migration speed, also make the total electrical charge quantity in raceway groove change, result in hot carrier injection effect and Negative Bias Temperature Instability deterioration, greatly reduce the electric property of PMOS.
For solving the problem, a kind of PMOS structure and forming method thereof is provided in the embodiment of the present invention, wherein the formation method of PMOS structure is the germanium silicon kind crystal layer by being formed in PMOS source drain region doped with fluorine ion, fluorine ion and the powerful bonding force of silicon atom is utilized to form potential barrier barrier, reduce transferred electron effect, reduce the diffusion probability of boron ion or germanium ion in germanium silicon body layer, improve the stability of device, improve Negative Bias Temperature Instability and hot carrier injection effect, improve semiconductor device electric property.
For enabling above-mentioned purpose, the feature and advantage of this method more become apparent, be described in detail below in conjunction with the embodiment of accompanying drawing to this method.When describing the embodiment of the present invention in detail, for ease of illustrating, schematic diagram can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, and it should not limit the scope of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
Fig. 1 ~ Fig. 5 is the cross-sectional view of the forming process of one embodiment of the invention PMOS structure.
With reference to figure 1, provide Semiconductor substrate 100, the side wall 102 that described Semiconductor substrate 100 surface is formed with grid structure 101 and is positioned on the sidewall of described grid structure 101 both sides.
Described Semiconductor substrate 100 is silicon substrate or silicon-on-insulator (SOI) substrate.
Described grid structure 101 comprises the gate dielectric layer 101a be positioned on Semiconductor substrate 100 surface and the grid layer 101b be positioned on described gate dielectric layer 101a surface.
Described gate dielectric layer 101a material is silica, silicon oxide carbide, hafnium oxide, nitrogen hafnium oxide, zirconia or nitrogen zirconia.Silica or silicon oxide carbide adopt thermal oxidation method, chemical vapour deposition technique or atomic layer deposition method to be formed; Hafnium oxide, nitrogen hafnium oxide, zirconia or nitrogen zirconia adopt chemical vapour deposition technique, physical vaporous deposition or atomic layer deposition method to be formed.
The thickness range of described gate dielectric layer 101a is
as an embodiment, described gate dielectric layer 101a thickness is
Described gate layer material 101b is polysilicon, the grid layer 101b of polysilicon adopts low-pressure chemical vapor deposition (LPCVD) method to be formed, as an embodiment, the reaction temperature of described Low Pressure Chemical Vapor Deposition is 600 DEG C ~ 800 DEG C, pressure is 50Torr ~ 300Torr, and silane flow rate 50 marks condition milliliter per minute ~ 300 mark condition milliliter per minute.Described grid layer 101b thickness is
Described side wall 102 material is silicon nitride, silicon oxynitride or silica, and described side wall 102 thickness is
With reference to figure 2, with described grid structure 101 and side wall 102 for mask, in side wall 102 semiconductor substrates on two sides 100, form groove 103.
The profile graphics of described groove 103 is U-shaped, and the degree of depth is
As an embodiment, form the method that described groove 103 adopts dry etching, the etching gas of described dry etching comprises HBr, Cl
2, SF
6, NF
3, O
2, CH
2f
2and CHF
3in one or more, the flow of etching gas is 50 mark condition milliliter per minute ~ 500 mark condition milliliter per minutes, and bias voltage is 50V ~ 450V, and power is 200W ~ 600W, and temperature is 30 DEG C ~ 60 DEG C, and the time is 40 seconds ~ 120 seconds.
With reference to figure 3, form germanium silicon kind crystal layer 104 in described groove 103 bottom surface and side surface, described germanium silicon kind crystal layer 104 is doped with fluorine ion.
The method forming described germanium silicon kind crystal layer 104 is selective epitaxial growth process, and as an embodiment, the temperature of described selective epitaxial growth process is 500 DEG C ~ 800 DEG C, and air pressure is that 1 holder ~ 100 are held in the palm, and reacting gas comprises silicon source gas SiH
4or SiH
2cl
2, and germanium source gas GeH
4, the flow of described silicon source gas and germanium source gas is 1 mark condition milliliter per minute ~ 1000 mark condition milliliter per minute.
In germanium silicon kind crystal layer 104, doped with fluorine ion method is in-situ doped technique.As an embodiment, described in-situ doped technique for: described in selective epitaxial growth during germanium silicon kind crystal layer 104, then add fluorine source gas BF
3or F
2, described fluorine source gas flow is 1 mark condition milliliter per minute ~ 100 mark condition milliliter per minute.
Doped with fluorine ion in described germanium silicon kind crystal layer 104, object is the diffusion phenomena in order to hinder boron ion and germanium ion.Fluorine atom is as VII major element, electronegative fluorine ion is formed after acquisition electronics, because fluorine ion radius is very little, and fluorine ion only has two-layer electronics, therefore be combined the bonding force of the Si-F key formed with silicon atom larger for fluorine ion, diffusion ion is when being doped with the germanium silicon kind crystal layer 104 of fluorine ion described in passing, need to overcome larger potential barrier to destroy the stable bonding of Si-F, therefore the germanium silicon kind crystal layer 104 being doped with fluorine ion is just equivalent to one potential barrier barrier, play the effect hindering boron ion or germanium ion diffusion, weaken the gate current increase phenomenon because boron ion diffuse causes, improve the drift of PMOS electric property.The doping of fluorine ion simultaneously can reduce transferred electron effect, prevents the diffusion of germanium ion, improves the stability of device, improves Negative Bias Temperature Instability and hot carrier injection effect.
In addition, the not doped with fluorine ion in germanium silicon body layer at germanium silicon kind crystal layer, ensure that while formation potential barrier barrier, device source leakage current will being caused to reduce because adulterating a large amount of fluorine ion in source-drain area, affecting device electric property.
Described germanium silicon kind crystal layer 104 is as transition zone, object is the epitaxial growth quality in order to improve follow-up germanium silicon body layer, avoid high Ge-doped germanium silicon body layer and directly produce larger lattice mismatch when substrate silicon Epitaxial growth, this lattice mismatch can cause germanium silicon body layer growth inequality even to grow failure, also easily lattice defect unnecessary is in a large number formed, therefore the Ge content of described germanium silicon kind crystal layer is lower, as an embodiment, in described germanium silicon kind crystal layer 104, the mass ratio of Ge element is 1% ~ 30%.
Described germanium silicon kind crystal layer 104 is just as transition zone, the mass ratio of Ge element is lower, therefore need to select suitable germanium silicon kind crystal layer thickness: thickness is too thin does not have the effect guiding high Ge-doped germanium silicon body layer growth as kind of crystal layer, thickness is too thick can be reduced germanium silicon body layer volume thus cause the stress loading of raceway groove not enough, as an embodiment, the thickness of described germanium silicon kind crystal layer 104 is
Further research finds, doped with fluorine ion in described germanium silicon kind crystal layer 104 also needs suitable doping content: the too low diffusion that cannot hinder boron ion or germanium ion of concentration, excessive concentration can cause again fluorine-ion-doped excessive and cause negative effect to PMOS electric property, as an embodiment, in described germanium silicon kind crystal layer 104, the doping content of fluorine ion is 1 × 10
18atom/cm
3~ 1 × 10
21atom/cm
3.
With reference to figure 4, described SiGe kind crystal layer 104 forms SiGe body layer 106, described SiGe body layer 106 fills the remainder of full described groove 103 (shown in Figure 3), and described germanium silicon body layer 106 is containing Doped ions.
The method forming described germanium silicon body layer 106 is selective epitaxial growth process.As an embodiment, the temperature of described selective epitaxial growth process is 500 DEG C ~ 800 DEG C, and air pressure is that 1 holder ~ 100 are held in the palm, and reacting gas comprises silicon source gas SiH
4or SiH
2cl
2, and germanium source gas GeH
4, the flow of described silicon source gas and germanium source gas is 1 mark condition milliliter per minute ~ 1000 mark condition milliliter per minute.
The Doped ions that described germanium silicon body layer 106 contains is boron ion.
In germanium silicon body layer 106, the method for doped with boron ion is in-situ doped technique.As an embodiment, the in-situ doped technique of described doped with boron ion is: when forming the selective epitaxial growth of described germanium silicon body layer 106, then add boron source gas B
2h
6, BH
3or BCl
3, described boron source gas flow is 1 mark condition milliliter per minute ~ 1000 mark condition milliliter per minute.
In described germanium silicon body layer 106, the mass ratio of Ge element is 30% ~ 50%, and the doping content of boron ion is 1 × 10
19atom/cm
3~ 5 × 10
20atom/cm
3.
Described germanium silicon body layer 106 fills full groove remainder completely, and germanium silicon body layer 106 end face flushes with Semiconductor substrate 100 surface.
Based on the formation method shown in Fig. 1 to Fig. 4, additionally provide a kind of PMOS structure in the embodiment of the present invention, with reference to figure 5, comprising:
Semiconductor substrate 100, the grid structure 101 being positioned at described Semiconductor substrate 100 surface and the side wall 102 be positioned on the sidewall of described grid structure 101 both sides;
Be arranged in the groove 130 of described side wall 102 semiconductor substrates on two sides 100;
Be positioned at the germanium silicon kind crystal layer 104 of described groove 130 bottom surface and side surface, described germanium silicon kind crystal layer 104 is doped with fluorine ion;
Be positioned at the SiGe body layer 106 on SiGe kind crystal layer 104, described SiGe body layer 106 fills the remainder of full described groove 130, and described germanium silicon body layer 106 is containing Doped ions.
Described Semiconductor substrate 100 is silicon substrate or silicon-on-insulator (SOI) substrate.
Described grid structure 101 comprises the gate dielectric layer 101a be positioned on described the Semiconductor substrate 100 and grid layer 101b be positioned on described gate dielectric layer 101a.
Described gate dielectric layer 101a material is silica, silicon oxide carbide, hafnium oxide, nitrogen hafnium oxide, zirconia or nitrogen zirconia.
Described grid layer 101b material is polysilicon.
Described side wall 102 material is silicon nitride, silicon oxynitride or silica.
Described groove 130 profile graphics is U-shaped, and the degree of depth is
The thickness of described germanium silicon kind crystal layer 104 is
the ratio of Ge element quality is 1% ~ 30%, and the doping content of fluorine ion is 1 × 10
18atom/cm
3~ 1 × 10
21atom/cm
3.
In described germanium silicon body layer 106, the mass ratio of Ge element is 30% ~ 50%, and the doping content of boron ion is 1 × 10
19atom/cm
3~ 5 × 10
20atom/cm
3.
Described germanium silicon body layer 106 fills full described groove 130 remainder completely, and germanium silicon body layer 106 end face flushes with Semiconductor substrate 100 surface.
Fig. 6 ~ Fig. 9 is the cross-sectional view of the forming process of another embodiment of the present invention PMOS structure.
With reference to figure 6, provide Semiconductor substrate 100, the side wall 102 that described Semiconductor substrate 100 surface is formed with grid structure 101 and is positioned on the sidewall of described grid structure 101 both sides; With described grid structure 101 and side wall 102 for mask, in described side wall 102 semiconductor substrates on two sides 100, form groove 107.
The method step formed before groove 107 is identical with the method step that a upper embodiment is formed before groove 103.
The profile graphics of described groove 107 is Sigma type, and the degree of depth is
the embedded germanium silicon layer of Sigma type has the drift angle near raceway groove, and the U-shaped embedded germanium silicon layer of stress ratio produced raceway groove is higher, can better promote the electric property of PMOS.
As an embodiment, form the method for described groove 107, comprise, dry etching forms a U-shaped groove, U-shaped groove described in wet etching, forms described Sigma type groove 107.The etching gas of the dry etching of the U-shaped groove of described formation comprises HBr, Cl
2, SF
6, NF
3, O
2, CH
2f
2and CHF
3in one or more, the flow of mist is 50 mark condition milliliter per minute ~ 500 mark condition milliliter per minutes, and bias voltage is 50V ~ 450V, and power is 200W ~ 600W, and temperature is 30 DEG C ~ 60 DEG C, and the time is 20 seconds ~ 80 seconds.The etching solution of the wet etching of described formation Sigma type groove 107 is tetramethyl ammonium hydroxide solution (TMAH), and concentration range is 1% ~ 10%, and temperature is 10 DEG C ~ 50 DEG C, and the time is 60 seconds ~ 180 seconds.
With reference to figure 7, form germanium silicon kind crystal layer 108 in described groove 107 bottom surface and side surface, described germanium silicon kind crystal layer 108 is doped with fluorine ion.
The method forming described germanium silicon kind crystal layer 108 is selective epitaxial growth process, and the temperature of described selective epitaxial growth process is 500 DEG C ~ 800 DEG C, and air pressure is that 1 holder ~ 100 are held in the palm, and reacting gas comprises silicon source gas SiH
4or SiH
2cl
2, and germanium source gas GeH
4, the flow of described silicon source gas and germanium source gas is 1 mark condition milliliter per minute ~ 1000 mark condition milliliter per minute.
In germanium silicon kind crystal layer 108, doped with fluorine ion method is in-situ doped technique.As an embodiment, described in-situ doped technique for: described in selective epitaxial growth during germanium silicon kind crystal layer 108, then add fluorine source gas BF
3or F
2, described fluorine source gas flow is 1 mark condition milliliter per minute ~ 100 mark condition milliliter per minute.
The thickness of described germanium silicon kind crystal layer 108 is
the ratio of Ge element quality is 1% ~ 30%, and the doping content of fluorine ion is 1 × 10
18atom/cm
3~ 1 × 10
21atom/cm
3.
With reference to figure 8, described SiGe kind crystal layer 108 forms SiGe body layer 110, described SiGe body layer 110 fills the remainder of full described groove 107 (shown in Figure 7), and described germanium silicon body layer 110 is containing Doped ions.
The method forming described germanium silicon body layer 110 is selective epitaxial growth process.As an embodiment, the temperature of described selective epitaxial growth process is 500 DEG C ~ 800 DEG C, and air pressure is that 1 holder ~ 100 are held in the palm, and reacting gas comprises silicon source gas SiH
4or SiH
2cl
2, and germanium source gas GeH
4, the flow of described silicon source gas and germanium source gas is 1 mark condition milliliter per minute ~ 1000 mark condition milliliter per minute.
The Doped ions that described germanium silicon body layer 110 contains is boron ion.
In germanium silicon body layer 110, the method for doped with boron ion is in-situ doped technique.As an embodiment, described doped with boron ion original position doping process is: when forming the selective epitaxial growth of described germanium silicon body layer 110, then add boron source gas B
2h
6, BH
3or BCl
3, described boron source gas flow is 1 mark condition milliliter per minute ~ 1000 mark condition milliliter per minute.
In described germanium silicon body layer 110, the mass ratio of Ge element is 30% ~ 50%, and the doping content of boron ion is 1 × 10
19atom/cm
3~ 5 × 10
20atom/cm
3.
Described germanium silicon body layer 110 fills full groove remainder completely, and germanium silicon body layer 110 end face flushes with Semiconductor substrate 100 surface.
Based on the formation method shown in Fig. 6 to Fig. 8, additionally provide a kind of PMOS structure in the embodiment of the present invention, with reference to figure 9, comprising:
Semiconductor substrate 100, the grid structure 101 being positioned at described Semiconductor substrate 100 surface and the side wall 102 be positioned on the sidewall of described grid structure 101 both sides;
Be arranged in the groove 140 of described side wall 102 semiconductor substrates on two sides 100;
Be positioned at the germanium silicon kind crystal layer 108 of described groove 140 bottom surface and side surface, described germanium silicon kind crystal layer 108 is doped with fluorine ion;
Be positioned at the SiGe body layer 110 on SiGe kind crystal layer 108, described SiGe body layer 110 fills the remainder of full described groove 140, and described germanium silicon body layer 110 is containing Doped ions.
Described Semiconductor substrate 100 is silicon substrate or silicon-on-insulator (SOI) substrate.
Described grid structure 101 comprises the gate dielectric layer 101a be positioned on described the Semiconductor substrate 100 and grid layer 101b be positioned on described gate dielectric layer 101a.
Described gate dielectric layer 101a material is silica, silicon oxide carbide, hafnium oxide, nitrogen hafnium oxide, zirconia or nitrogen zirconia.
Described grid layer 101b material is polysilicon.
Described side wall 102 material is silicon nitride, silicon oxynitride or silica.
Described groove 140 profile graphics is Sigma type, and the degree of depth is
The thickness of described germanium silicon kind crystal layer 108 is
the ratio of Ge element quality is 1% ~ 30%, and the doping content of fluorine ion is 1 × 10
18atom/cm
3~ 1 × 10
21atom/cm
3.
In described germanium silicon body layer 110, the mass ratio of Ge element is 30% ~ 50%, and the doping content of boron ion is 1 × 10
19atom/cm
3~ 5 × 10
20atom/cm
3.
Described germanium silicon body layer 110 fills full described groove 140 remainder completely, and germanium silicon body layer 110 end face flushes with Semiconductor substrate 100 surface.
To sum up, the formation method of the PMOS structure that the embodiment of the present invention provides, by first forming the germanium silicon kind crystal layer doped with fluorine ion in PMOS source drain region, form the method for germanium silicon body layer again, utilize fluorine ion and the powerful bonding force of silicon atom, in germanium silicon kind crystal layer, form potential barrier barrier, reduce transferred electron effect, reduce the diffusion probability of boron ion or germanium ion in germanium silicon body layer, the stability of device can be improved, improve Negative Bias Temperature Instability and hot carrier injection effect.In addition, the not doped with fluorine ion in germanium silicon body layer at germanium silicon kind crystal layer, ensure that while formation potential barrier barrier, device source leakage current will being caused to reduce because adulterating a large amount of fluorine ion in source-drain area, affecting device electric property.
The PMOS structure that the embodiment of the present invention provides, comprise the germanium silicon kind crystal layer doped with fluorine ion, make use of fluorine ion and the powerful bonding force of silicon atom forms potential barrier barrier, reduce transferred electron effect, reduce the diffusion probability of boron ion or germanium ion, the stability of device can be improved, improve Negative Bias Temperature Instability and hot carrier injection effect.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1. a formation method for PMOS structure, is characterized in that, comprising:
There is provided Semiconductor substrate, described semiconductor substrate surface is formed with grid structure and is positioned at the side wall on the sidewall of described grid structure both sides;
With described grid structure and side wall for mask, in Semiconductor substrate described in side wall both sides, form groove;
Form germanium silicon kind crystal layer in described trench bottom surfaces and side surface, described germanium silicon kind crystal layer is doped with fluorine ion;
Described SiGe kind crystal layer forms SiGe body layer, and described SiGe body layer fills the remainder of full described groove, and described germanium silicon body layer contains Doped ions.
2. the formation method of PMOS structure as claimed in claim 1, it is characterized in that, the method forming described germanium silicon kind crystal layer is selective epitaxial growth process, the temperature of described selective epitaxial growth process is 500 DEG C ~ 800 DEG C, air pressure is that 1 holder ~ 100 are held in the palm, reacting gas comprises silicon source gas and germanium source gas, and silicon source gas is SiH
4or SiH
2cl
2, germanium source gas is GeH
4, the flow of described silicon source gas and germanium source gas is 1 mark condition milliliter per minute ~ 1000 mark condition milliliter per minute.
3. the formation method of PMOS structure as claimed in claim 2, it is characterized in that, in described germanium silicon kind crystal layer, the mass ratio of Ge element is 1% ~ 30%, and the thickness of described germanium silicon kind crystal layer is
4. the formation method of PMOS structure as claimed in claim 2, it is characterized in that, in described germanium silicon kind crystal layer, the method for doped with fluorine ion is in-situ doped technique.
5. the formation method of PMOS structure as claimed in claim 4, it is characterized in that, in described germanium silicon kind crystal layer, the in-situ doped technique of doped with fluorine ion is: add fluorine source gas BF when forming the selective epitaxial growth process of described germanium silicon kind crystal layer
3or F
2, described fluorine source gas flow is concentration is 1 mark condition milliliter per minute ~ 100 mark condition milliliter per minute.
6. the formation method of PMOS structure as claimed in claim 4, it is characterized in that, in described germanium silicon kind crystal layer, the doping content of fluorine ion is 1 × 10
18atom/cm
3~ 1 × 10
21atom/cm
3.
7. the formation method of PMOS structure as claimed in claim 1, it is characterized in that, the method forming the germanium silicon body layer of filling full described groove remainder is selective epitaxial growth process, the temperature of described selective epitaxial growth process is 500 DEG C ~ 800 DEG C, air pressure is that 1 holder ~ 100 are held in the palm, reacting gas comprises silicon source gas and germanium source gas, and silicon source gas is SiH
4or SiH
2cl
2, germanium source gas is GeH
4, the flow of described silicon source gas and germanium source gas is 1 mark condition milliliter per minute ~ 1000 mark condition milliliter per minute.
8. the formation method of PMOS structure as claimed in claim 7, it is characterized in that, in described germanium silicon body layer, the mass ratio of Ge element is 30% ~ 50%, and the Doped ions that described germanium silicon body layer contains is boron ion.
9. the formation method of PMOS structure as claimed in claim 8, it is characterized in that, be in-situ doped technique in the method for described germanium silicon body layer doped with boron ion, described in-situ doped technique is: add boron source gas when forming the selective epitaxial growth process of described germanium silicon body layer, and boron source gas flow is 1 mark condition milliliter per minute ~ 1000 mark condition milliliter per minute.
10. the formation method of PMOS structure as claimed in claim 9, it is characterized in that, described boron source gas is B
2h
6, BH
3or BCl
3.
The formation method of 11. PMOS structures as claimed in claim 1, is characterized in that, described grid structure comprises the gate dielectric layer be positioned on described Semiconductor substrate and the grid layer be positioned on described gate dielectric layer.
The formation method of 12. PMOS structures as claimed in claim 1, it is characterized in that, described spacer material is silicon nitride, silicon oxynitride or silica.
The formation method of 13. PMOS structures as claimed in claim 1, it is characterized in that, described groove is U-shaped or Sigma type, and depth bounds is
14. 1 kinds of PMOS structures, is characterized in that, comprising:
Semiconductor substrate, the grid structure being positioned at described semiconductor substrate surface and the side wall be positioned on the sidewall of described grid structure both sides;
Be arranged in the groove of described side wall semiconductor substrates on two sides;
Be positioned at the germanium silicon kind crystal layer of described trench bottom surfaces and side surface, described germanium silicon kind crystal layer is doped with fluorine ion;
Be positioned at the SiGe body layer on SiGe kind crystal layer, described SiGe body layer fills the remainder of full described groove, and described germanium silicon body layer contains Doped ions.
15. PMOS structures as claimed in claim 14, is characterized in that, in described germanium silicon kind crystal layer, the mass ratio of Ge element is 1% ~ 30%, and the thickness of described germanium silicon kind crystal layer is
16. PMOS structures as claimed in claim 14, is characterized in that, in described germanium silicon kind crystal layer, the doping content of fluorine ion is 1 × 10
18atom/cm
3~ 1 × 10
21atom/cm
3.
17. PMOS structures as claimed in claim 14, is characterized in that, in described germanium silicon body layer, the mass ratio of Ge element is 30% ~ 50%, and the Doped ions that described germanium silicon body layer contains is boron ion.
18. PMOS structures as claimed in claim 14, is characterized in that, described grid structure comprises the gate dielectric layer be positioned on described Semiconductor substrate and the grid layer be positioned on described gate dielectric layer.
19. PMOS structures as claimed in claim 14, it is characterized in that, described spacer material is silicon nitride, silicon oxynitride or silica.
20. PMOS structures as claimed in claim 14, it is characterized in that, described groove is U-shaped or Sigma type, and depth bounds is
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| CN112885849A (en) * | 2021-01-29 | 2021-06-01 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
| CN113675217A (en) * | 2020-05-14 | 2021-11-19 | 上海功成半导体科技有限公司 | FD-SOI substrate structure and device structure |
| US11411071B1 (en) | 2020-09-28 | 2022-08-09 | Changxin Memory Technologies, Inc. | Capacitor array structure and method for manufacturing a capacitor array structure, and semiconductor memory device |
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| US20120181625A1 (en) * | 2011-01-19 | 2012-07-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing strained source/drain structures |
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| US20120181625A1 (en) * | 2011-01-19 | 2012-07-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing strained source/drain structures |
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| US11411071B1 (en) | 2020-09-28 | 2022-08-09 | Changxin Memory Technologies, Inc. | Capacitor array structure and method for manufacturing a capacitor array structure, and semiconductor memory device |
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