CN113675217A - FD-SOI substrate structure and device structure - Google Patents

FD-SOI substrate structure and device structure Download PDF

Info

Publication number
CN113675217A
CN113675217A CN202010404711.0A CN202010404711A CN113675217A CN 113675217 A CN113675217 A CN 113675217A CN 202010404711 A CN202010404711 A CN 202010404711A CN 113675217 A CN113675217 A CN 113675217A
Authority
CN
China
Prior art keywords
layer
silicon
germanium
angstroms
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010404711.0A
Other languages
Chinese (zh)
Inventor
徐大朋
薛忠营
罗杰馨
柴展
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Gongcheng Semiconductor Technology Co Ltd
Original Assignee
Shanghai Gongcheng Semiconductor Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Gongcheng Semiconductor Technology Co Ltd filed Critical Shanghai Gongcheng Semiconductor Technology Co Ltd
Priority to CN202010404711.0A priority Critical patent/CN113675217A/en
Publication of CN113675217A publication Critical patent/CN113675217A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)

Abstract

The invention provides an FD-SOI substrate structure and a device structure. The substrate structure adopts a stack structure of the top germanium-silicon layer and the silicon material layer as a channel of the device, the channel does not need to be doped and is thinner, the leakage current between the source and the drain can be greatly reduced, and on the other hand, the top germanium-silicon layer can greatly improve the hole mobility, thereby improving the performance of the device. The silicon material layer covers the top germanium-silicon layer, so that the surface of the germanium-silicon channel can be effectively prevented from forming water-soluble GeO2Or volatile GeO, thereby improving the stability of the device.

Description

FD-SOI substrate structure and device structure
Technical Field
The invention belongs to the field of semiconductor design and manufacture, and particularly relates to an FD-SOI substrate structure and a device structure.
Background
After the bulk silicon CMOS technology has gone to 22nm, the feature size has been difficult to continue to shrink, and innovative technologies are urgently needed to sustain further development. Among the candidates, the FDSOI (Fully Depleted SOI) technology is very competitive. For the FDSOI transistor, the silicon film naturally limits the depth of a source-Drain junction and also limits a source-Drain junction depletion region, so that short channel effects such as DIBL (Drain Induced Barrier Lowering) and the like can be improved, the sub-threshold characteristic of the device is improved, and the static power consumption of the circuit is reduced. In addition, the FDSOI transistor does not need channel doping, and can avoid RDF (Random Dopants Fluctuation) and other effects, thereby maintaining a stable threshold voltage and avoiding mobility degradation caused by doping.
Different from a 3D transistor structure adopted by a FinFET process, the FD-SOI is a planar process, so that the process difficulty can be effectively reduced; compared with the traditional bulk silicon technology, FD-SOI can provide better electrostatic characteristics of the transistor, and the buried oxide layer can reduce the parasitic capacitance between a source (source) and a drain (drain); in addition, the technology can effectively limit the electron flow between the source electrode and the drain electrode, and greatly reduce the leakage current which influences the performance of the component. In addition to the pass gate, FD-SOI also allows for control of transistor behavior by poling the device substrate underneath, similar to bulk silicon technology, also for achievable body bias.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides an FD-SOI substrate structure and a device structure, which are used to solve the problem of low carrier mobility of the FD-SOI device structure in the prior art.
To achieve the above and other related objects, the present invention provides a method for fabricating an FD-SOI substrate structure, the method comprising: 1) providing an FD-SOI substrate, wherein the FD-SOI substrate comprises a silicon substrate, a buried oxide layer and a top silicon layer; 2) epitaxially growing a silicon germanium layer on the top silicon layer; 3) oxidizing the SiGe layer, pushing germanium in the SiGe layer into the top SiGe layer to form a top SiGe layer; 4) removing the silicon dioxide layer generated by the oxidation reaction to expose the top germanium-silicon layer; 5) and epitaxially growing a silicon material layer on the top germanium-silicon layer.
Optionally, the thickness of the top silicon layer in step 1) ranges from 50 to 200 angstroms, and the buried oxide layer is a silicon dioxide layer and ranges from 100 to 300 angstroms.
Optionally, the epitaxially growing a germanium-silicon layer of step 2) comprises: removing the oxide on the surface of the top silicon layer; and growing a germanium-silicon layer in situ, wherein the concentration of germanium in the germanium-silicon layer is between 20 and 40 percent, and the thickness of the germanium-silicon layer is between 50 and 400 angstroms.
Optionally, the oxidation conditions of step 3) are reaction in an oxygen atmosphere at 800-1100 ℃, and the thickness of the formed top silicon germanium layer ranges from 60 to 100 angstroms.
Optionally, the method for removing the silicon dioxide layer in the step 4) includes etching the silicon dioxide layer with an HF acid solution or gas.
Optionally, the step 5) of epitaxially growing the silicon material layer includes: removing the oxide on the surface of the top germanium-silicon layer; and growing a silicon material layer in situ, wherein the thickness of the silicon material layer is between 5 and 20 angstroms.
The invention also provides a preparation method of the FD-SOI device structure, which comprises the following steps: 1) preparing the FD-SOI substrate structure by adopting the preparation method of the FD-SOI substrate structure; 2) depositing a gate oxide layer, a high-k dielectric layer, a titanium nitride layer and a gate electrode layer on the silicon material layer in sequence; 3) etching the gate layer, the titanium nitride layer, the high-k dielectric layer and the gate oxide layer to form a gate structure, and forming side wall structures on two sides of the gate structure; 4) and epitaxially growing germanium-silicon convex layers on two sides of the grid structure.
Optionally, the method for depositing the gate oxide layer in the step 2) comprises an in-situ water vapor generation method, wherein the thickness of the gate oxide layer is between 6 and 15 angstroms; the high-k dielectric layer comprises HfO2And HfLaO2The thickness of the titanium nitride layer is between 15 and 30 angstroms, and the thickness of the titanium nitride layer is between 15 and 30 angstroms.
Optionally, step 3) comprises: forming a hard mask layer and a photoresist layer on the gate layer, defining a gate region, and forming a gate structure by plasma etching, wherein the gate layer is made of amorphous silicon and has a thickness ranging from 500 to 600 angstroms, the hard mask layer is made of a combination of silicon oxide and silicon nitride, and the total thickness ranges from 350 to 500 angstroms.
Optionally, the step 4) of epitaxially growing the germanium-silicon convex layer includes: removing oxides on the surfaces of the silicon layers on the two sides of the grid structure; growing a germanium-silicon convex layer in situ, wherein the germanium concentration range of the germanium-silicon convex layer is between 20 and 50 percent, and the boron concentration of the germanium-silicon convex layer is 1 multiplied by 1019～1021/cm3The thickness range of the germanium-silicon convex layer is 200-400 angstroms.
The invention also provides an FD-SOI substrate structure, which comprises a silicon substrate, a buried oxide layer, a top germanium-silicon layer and a silicon material layer which are sequentially stacked.
Optionally, the thickness of the top germanium-silicon layer ranges from 60 to 100 angstroms, and the thickness of the silicon material layer ranges from 5 to 20 angstroms.
Optionally, the buried oxide layer is a silicon dioxide layer having a thickness in a range of 100 to 300 angstroms.
The present invention also provides an FD-SOI device structure, comprising: the FD-SOI substrate structure as described above; the grid structure is positioned on the silicon material layer and comprises a grid oxide layer, a high-k dielectric layer, a titanium nitride layer and a grid layer which are sequentially stacked, and side wall structures are arranged on two sides of the grid structure; and the germanium-silicon convex layers are formed on two sides of the grid structure.
Optionally, the thickness of the gate oxide layer is between 6 and 15 angstroms; the high-k dielectric layer comprises HfO2And HfLaO2The thickness of the titanium nitride layer is between 15 and 30 angstroms, the material of the gate layer comprises amorphous silicon, and the thickness of the gate layer is between 500 and 600 angstroms.
Optionally, the germanium concentration range of the germanium-silicon convex layer is between 20% and 50%, and the boron concentration range is 1 × 1019～1021/cm3The thickness range of the germanium-silicon convex layer is 200-400 angstroms.
As described above, the FD-SOI substrate structure and the device structure of the present invention have the following advantageous effects:
the FD-SOI substrate structure adopts a stack structure of the top germanium-silicon layer and the silicon material layer, the top germanium-silicon layer can be used as a channel of a subsequent device, such as an MOS device, and the channel does not need to be doped, on one hand, the thickness of the top germanium-silicon layer is thinner, so that the limitation of electron flow between a source electrode and a drain electrode is limited, and the leakage current between the source electrode and the drain electrode can be greatly reduced, on the other hand, the germanium atoms in a germanium-silicon system are larger than the silicon atoms, and the generated compressive stress can split a valence band energy band, so that the effective quality of a cavity is reduced, the hole mobility is greatly improved, and the performance of the device is further improved.
The silicon material layer covers the top germanium-silicon layer, so that the surface of the germanium-silicon channel can be effectively prevented from forming water-soluble GeO2Or volatile GeO, thereby greatly improving the stability of the device.
Drawings
Fig. 1 to 5 are schematic structural views showing steps of a method for manufacturing an FD-SOI substrate structure according to an embodiment of the present invention.
Fig. 6 to 8 are schematic structural views showing steps of a method for manufacturing an FD-SOI device structure in an embodiment of the present invention.
Description of the element reference numerals
101 silicon substrate
102 buried oxide layer
103 top silicon layer
104 germanium-silicon layer
105 top germanium silicon layer
106 silicon dioxide layer
107 silicon material layer
108 gate oxide layer
109 high-k dielectric layer
110 titanium nitride layer
111 gate layer
112 mask layer
113 side wall structure
114. 115 SiGe bump
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 1 to 5, the present embodiment provides a method for manufacturing an FD-SOI substrate structure, the method comprising:
as shown in fig. 1, step 1) is first performed to provide an FD-SOI substrate comprising a silicon base 101, a buried oxide layer 102, and a top silicon layer 103.
The top silicon layer 103 has a thickness in the range of 50-200 angstroms, and the buried oxide layer 102 is a silicon dioxide layer 106 having a thickness in the range of 100-300 angstroms. For example, the top silicon layer 103 may have a thickness of 100 angstroms and the buried oxide layer 102 may have a thickness of 200 angstroms.
As shown in fig. 2, step 2) is then performed to epitaxially grow a silicon germanium layer 104 on the top silicon layer 103.
For example, step 2) of epitaxially growing sige layer 104 comprises:
and 2-1) removing the oxide on the surface of the top silicon layer 103 to obtain a surface which exposes the top silicon layer 103, and simultaneously enabling the surface to have lower defects so as to be beneficial to the growth of a subsequent germanium-silicon layer 104 and the improvement of the efficiency of pushing germanium in the subsequent germanium-silicon layer 104 into the top silicon layer 103.
For example, the oxide can be removed by etching with an etching solution such as SiCoNi, HCl, etc., and for example, H, etc2And reducing and cleaning the oxide by using reducing gas to remove the oxide. Of course, other etching solutions or reducing gases may be used to remove the oxide, and are not limited to the examples listed herein.
Step 2-1), growing the germanium-silicon layer 104 in situ, wherein the concentration of germanium in the germanium-silicon layer 104 is between 20% and 40%, and the thickness range of the germanium-silicon layer 104 is between 50 angstrom and 400 angstrom. For example, the germanium concentration in the sige layer 104 may be 30%, and the thickness of the sige layer 104 may be 300 angstroms.
As shown in fig. 3, step 3) is then performed to oxidize the sige layer 104, pushing the ge in the sige layer 104 into the top si layer 103 through oxygen occupancy to form a top sige layer 105.
By way of example, the above-described oxidation conditions are reaction in an oxygen atmosphere at 800 ℃ to 1100 ℃, and the top silicon germanium layer 105 is formed to a thickness in the range of 60 angstroms to 100 angstroms. For example, the above-described oxidation conditions were reaction in an oxygen atmosphere at 1000 ℃ to form the top silicon germanium layer 105 having a thickness of 80 angstroms. One portion of the top sige layer 105 may be formed by pushing ge into the top si layer 103, and another portion may be a portion of the sige layer 104 that remains unoxidized.
The top germanium-silicon layer 105 can be used as a channel of a subsequent device, such as an MOS device, the channel does not need to be doped, on one hand, the top germanium-silicon layer 105 is thin, so that the flow of electrons between a source electrode and a drain electrode is limited, and the leakage current between the source electrode and the drain electrode can be greatly reduced, on the other hand, in a germanium-silicon system (SiGe/Si), germanium (Ge) atoms are larger than silicon (Si) atoms, the generated compressive stress can split a valence band energy band, the effective quality of a hole is reduced, and therefore the hole mobility is greatly improved, and the performance of the device is further improved.
As shown in fig. 4, step 4) is performed to remove the silicon dioxide layer 106 formed by the oxidation reaction, so as to expose the top sige layer 105.
For example, the method of removing the silicon oxide layer 106 includes etching the silicon oxide layer 106 with an HF acid solution or gas. Of course, other liquids or gases capable of reducing silicon dioxide may be used to remove the silicon dioxide layer 106, and are not limited to the above-listed examples.
As shown in fig. 5, finally, step 5) is performed to epitaxially grow a layer 107 of silicon material on the top ge-si layer 105.
For example, epitaxially growing a silicon layer includes:
and 5-1), removing the oxide on the surface of the top germanium-silicon layer 105.
Step 5-2), growing a silicon material layer 107 in situ, wherein the thickness of the silicon material layer 107 is between 5 and 20 angstroms.
The silicon material is epitaxially grown on the top SiGe layer 105Layer 107 effective to prevent formation of water-soluble GeO on the surface of the SiGe channel2Or volatile GeO, thereby greatly improving the stability of the device.
As shown in fig. 1 to 8, this embodiment further provides a method for manufacturing an FD-SOI device structure, which includes the steps of:
as shown in fig. 1 to 5, step 1) is first performed to prepare an FD-SOI substrate structure using the preparation method of an FD-SOI substrate structure as described above.
The FD-SOI substrate structure may be fabricated as described above and will not be described herein.
As shown in fig. 6, step 2) is then performed to sequentially deposit a gate oxide layer 108, a high-k dielectric layer 109, a titanium nitride layer 110 and a gate layer 111 on the silicon material layer.
For example, the method for depositing the gate oxide layer 108 in the step 2) comprises an in-situ water vapor generation method, wherein the thickness of the gate oxide layer 108 is between 6 and 15 angstroms; the high-k dielectric layer 109 comprises HfO2And HfLaO2The thickness of the titanium nitride layer 110 is between 15 and 30 angstroms, and the material of the gate layer 111 comprises amorphous silicon and has a thickness between 500 and 600 angstroms. The titanium nitride layer 110 can effectively improve the mechanical and electrical properties between the gate layer 111 and the high-k dielectric.
As shown in fig. 7, step 3) is performed to etch the gate layer 111, the titanium nitride layer 110, the high-k dielectric layer 109 and the gate oxide layer 108, so as to form a gate structure, and sidewall structures 113 are formed on two sides of the gate structure.
Specifically, the method comprises the following steps: and forming a hard mask layer 112 and a photoresist layer on the gate layer 111, defining a gate region, and forming a gate structure by using plasma etching, wherein the hard mask layer is made of a combination of silicon oxide and silicon nitride, and the total thickness ranges from 350 to 500 angstroms.
As shown in fig. 8, step 4) is finally performed to epitaxially grow germanium-silicon convex layers 114 and 115 on two sides of the gate structure, where the germanium-silicon convex layers 114 and 115 are electrically isolated from the gate structure by the sidewall structure 113.
The FD-SOI device structure comprises PMOS transistors, the sige convex layers 114 and 115 are respectively used as the source and drain of the PMOS transistors, and the top sige layer 105 under the gate structure is used as the channel of the PMOS.
Specifically, the step 4) of epitaxially growing the germanium-silicon convex layers 114 and 115 includes: removing oxides on the surfaces of the silicon layers on the two sides of the grid structure; growing germanium-silicon convex layers 114 and 115 in situ, wherein the germanium concentration range of the germanium-silicon convex layers 114 and 115 is between 20 and 50 percent, and the boron concentration is 1 multiplied by 1019～1021/cm3The thickness of the germanium-silicon bump layers 114 and 115 ranges from 200 to 400 angstroms.
As shown in fig. 5, the present embodiment further provides an FD-SOI substrate structure, which includes a silicon substrate 101, a buried oxide layer 102, a top ge-si layer 105, and a si material layer 107, which are stacked in sequence.
For example, the thickness of the top sige layer 105 ranges from 60 to 100 angstroms and the thickness of the silicon material layer 107 ranges from 5 to 20 angstroms.
According to the invention, the silicon material layer 107 is extended on the top germanium-silicon layer 105, so that the formation of water-soluble GeO on the surface of a germanium-silicon channel can be effectively prevented2Or volatile GeO, thereby greatly improving the stability of the device.
As shown in fig. 8, the present embodiment also provides an FD-SOI device structure, which includes: the FD-SOI substrate structure as described above; the gate structure is positioned on the silicon material layer 107 and comprises a gate oxide layer 108, a high-k dielectric layer 109, a titanium nitride layer 110 and a gate layer 111 which are sequentially stacked, and side wall structures 113 are arranged on two sides of the gate structure; germanium-silicon convex layers 114 and 115 are formed on two sides of the grid structure.
For example, the thickness of the gate oxide layer 108 is between 6 and 15 angstroms; the high-k dielectric layer 109 comprises HfO2And HfLaO2The thickness of the titanium nitride layer 110 is between 15 and 30 angstroms, and the material of the gate layer 111 comprises amorphous silicon and has a thickness between 500 and 600 angstroms.
For example, the germanium concentration of the germanium-silicon bump layers 114, 115 ranges from 20% to 50% and the boron concentration ranges from 1 × 1019～1021/cm3The thickness of the germanium-silicon bump layers 114 and 115 ranges from 200 to 400 angstroms.
The FD-SOI device structure comprises PMOS transistors, the sige convex layers 114 and 115 are respectively used as the source and drain of the PMOS transistors, and the top sige layer 105 under the gate structure is used as the channel of the PMOS. The titanium nitride layer 110 can effectively improve the mechanical and electrical properties between the gate layer 111 and the high-k dielectric.
As described above, the FD-SOI substrate structure and the device structure of the present invention have the following advantageous effects:
the FD-SOI substrate structure adopts a stack structure of the top germanium-silicon layer and the silicon material layer, the top germanium-silicon layer can be used as a channel of a subsequent device, such as an MOS device, and the channel does not need to be doped, on one hand, the thickness of the top germanium-silicon layer is thinner, so that the limitation of electron flow between a source electrode and a drain electrode is limited, and the leakage current between the source electrode and the drain electrode can be greatly reduced, on the other hand, the germanium atoms in a germanium-silicon system are larger than the silicon atoms, and the generated compressive stress can split a valence band energy band, so that the effective quality of a cavity is reduced, the hole mobility is greatly improved, and the performance of the device is further improved.
The silicon material layer covers the top germanium-silicon layer, so that the surface of the germanium-silicon channel can be effectively prevented from forming water-soluble GeO2Or volatile GeO, thereby greatly improving the stability of the device.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. The FD-SOI substrate structure is characterized by comprising a silicon substrate, a buried oxide layer, a top germanium-silicon layer and a silicon material layer which are sequentially stacked.
2. The FD-SOI substrate structure of claim 1 wherein: the thickness of the top SiGe layer ranges from 60 to 100 angstroms.
3. The FD-SOI substrate structure of claim 1 wherein: the thickness of the silicon material layer is between 5 and 20 angstroms.
4. The FD-SOI substrate structure of claim 1 wherein: the buried oxide layer is a silicon dioxide layer, and the thickness range of the buried oxide layer is between 100 and 300 angstroms.
5. An FD-SOI device structure, comprising:
the FD-SOI substrate structure of claim 1 to 4;
the grid structure is positioned on the silicon material layer and comprises a grid oxide layer, a high-k dielectric layer, a titanium nitride layer and a grid layer which are sequentially stacked, and side wall structures are arranged on two sides of the grid structure;
and the germanium-silicon convex layers are formed on two sides of the grid structure.
6. The FD-SOI device structure of claim 5, wherein: the thickness of the gate oxide layer is between 6 and 15 angstroms.
7. The FD-SOI device structure of claim 5, wherein: the high-k dielectric layer comprises HfO2And HfLaO2Of between 15 and 30 angstroms thick.
8. The FD-SOI device structure of claim 5, wherein: the thickness of the titanium nitride layer ranges from 15 to 30 angstroms.
9. The FD-SOI device structure of claim 5, wherein: the gate layer is made of amorphous silicon and has a thickness ranging from 500 to 600 angstroms.
10. The FD-SOI device structure of claim 5, wherein: the germanium concentration range of the germanium-silicon convex layer is between 20% and 50%, and the boron concentration is 1 multiplied by 1019～1021/cm3The thickness range of the germanium-silicon convex layer is 200-400 angstroms.
CN202010404711.0A 2020-05-14 2020-05-14 FD-SOI substrate structure and device structure Pending CN113675217A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010404711.0A CN113675217A (en) 2020-05-14 2020-05-14 FD-SOI substrate structure and device structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010404711.0A CN113675217A (en) 2020-05-14 2020-05-14 FD-SOI substrate structure and device structure

Publications (1)

Publication Number Publication Date
CN113675217A true CN113675217A (en) 2021-11-19

Family

ID=78537048

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010404711.0A Pending CN113675217A (en) 2020-05-14 2020-05-14 FD-SOI substrate structure and device structure

Country Status (1)

Country Link
CN (1) CN113675217A (en)

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004039831A (en) * 2002-07-03 2004-02-05 Renesas Technology Corp Manufacturing method of semiconductor device
US20040175872A1 (en) * 2003-03-07 2004-09-09 Taiwan Semiconductor Manufacturing Company Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement
CN101764102A (en) * 2009-12-24 2010-06-30 中国科学院上海微系统与信息技术研究所 Method for manufacturing silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) device with vertical gate structure
CN102237268A (en) * 2010-04-21 2011-11-09 中国科学院微电子研究所 Preparation and etching method of plug-in TiN metal gate stack structure
CN102646643A (en) * 2012-05-03 2012-08-22 上海华力微电子有限公司 Preparation method of accumulative type Si-NWFET (silicon-nanowire field effect transistor based on SOI (Silicon On Insulator)
US20140353717A1 (en) * 2013-05-31 2014-12-04 International Business Machines Corporation Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region
CN105374684A (en) * 2014-08-30 2016-03-02 中芯国际集成电路制造(上海)有限公司 PMOS structure and formation method thereof
CN211828771U (en) * 2020-05-14 2020-10-30 上海新微技术研发中心有限公司 FD-SOI substrate structure and device structure
CN211828770U (en) * 2020-05-14 2020-10-30 上海新微技术研发中心有限公司 FD-SOI substrate structure and device structure
CN113675218A (en) * 2020-05-14 2021-11-19 上海功成半导体科技有限公司 FD-SOI substrate structure and device structure
CN113675135A (en) * 2020-05-14 2021-11-19 上海功成半导体科技有限公司 FD-SOI substrate structure and device structure preparation method
CN113745147A (en) * 2020-05-14 2021-12-03 上海功成半导体科技有限公司 FD-SOI substrate structure and device structure preparation method

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004039831A (en) * 2002-07-03 2004-02-05 Renesas Technology Corp Manufacturing method of semiconductor device
US20040175872A1 (en) * 2003-03-07 2004-09-09 Taiwan Semiconductor Manufacturing Company Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement
CN101764102A (en) * 2009-12-24 2010-06-30 中国科学院上海微系统与信息技术研究所 Method for manufacturing silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) device with vertical gate structure
CN102237268A (en) * 2010-04-21 2011-11-09 中国科学院微电子研究所 Preparation and etching method of plug-in TiN metal gate stack structure
CN102646643A (en) * 2012-05-03 2012-08-22 上海华力微电子有限公司 Preparation method of accumulative type Si-NWFET (silicon-nanowire field effect transistor based on SOI (Silicon On Insulator)
US20140353717A1 (en) * 2013-05-31 2014-12-04 International Business Machines Corporation Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region
CN105374684A (en) * 2014-08-30 2016-03-02 中芯国际集成电路制造(上海)有限公司 PMOS structure and formation method thereof
CN211828771U (en) * 2020-05-14 2020-10-30 上海新微技术研发中心有限公司 FD-SOI substrate structure and device structure
CN211828770U (en) * 2020-05-14 2020-10-30 上海新微技术研发中心有限公司 FD-SOI substrate structure and device structure
CN113675218A (en) * 2020-05-14 2021-11-19 上海功成半导体科技有限公司 FD-SOI substrate structure and device structure
CN113675135A (en) * 2020-05-14 2021-11-19 上海功成半导体科技有限公司 FD-SOI substrate structure and device structure preparation method
CN113745147A (en) * 2020-05-14 2021-12-03 上海功成半导体科技有限公司 FD-SOI substrate structure and device structure preparation method

Similar Documents

Publication Publication Date Title
US10559654B2 (en) Nanosheet isolation for bulk CMOS non-planar devices
US10014322B2 (en) Local SOI fins with multiple heights
CN102428564B (en) Nanowire mesh FET with multiple threshold voltages
US7154118B2 (en) Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
JP4034387B2 (en) Integrated CMOS circuit device and manufacturing method thereof
US8466451B2 (en) Single gate inverter nanowire mesh
US20050285212A1 (en) Transistors with increased mobility in the channel zone and method of fabrication
JP5728444B2 (en) Semiconductor device and manufacturing method thereof
TW201419539A (en) Source and drain doping using doped raised source and drain regions
WO2011066728A1 (en) Comound material accumulation type of whole enclosing gate cmos field effect transistor
CN211828771U (en) FD-SOI substrate structure and device structure
US11973126B2 (en) Isolation structures for transistors
CN109473398B (en) Semiconductor device and method for manufacturing the same
CN211828770U (en) FD-SOI substrate structure and device structure
CN113675135A (en) FD-SOI substrate structure and device structure preparation method
CN113745147A (en) FD-SOI substrate structure and device structure preparation method
CN113675218A (en) FD-SOI substrate structure and device structure
US20220293601A1 (en) FINFET Device Having Flat-Top Epitaxial Features and Method of Making the Same
KR101367989B1 (en) A fabrication method of ultra-thin finfet and the ultra-thin finfet fabricated by this method.
CN113675217A (en) FD-SOI substrate structure and device structure
WO2022086764A1 (en) Formation of gate all around device
CN106981422B (en) Vertical TFET and manufacturing method thereof
CN102738174B (en) A kind of three strain whole plane SOI BiCMOS integrated device and preparation methods
CN102738172B (en) A kind of two polyplanar SOI BiCMOS integrated device and preparation method
CN114639731A (en) Method for manufacturing semiconductor element

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB03 Change of inventor or designer information
CB03 Change of inventor or designer information

Inventor after: Xu Dapeng

Inventor after: Luo Jiexin

Inventor after: Chai Zhan

Inventor before: Xu Dapeng

Inventor before: Xue Zhongying

Inventor before: Luo Jiexin

Inventor before: Chai Zhan