CN112883675A - Semiconductor device modeling method and device - Google Patents
Semiconductor device modeling method and device Download PDFInfo
- Publication number
- CN112883675A CN112883675A CN202110259512.XA CN202110259512A CN112883675A CN 112883675 A CN112883675 A CN 112883675A CN 202110259512 A CN202110259512 A CN 202110259512A CN 112883675 A CN112883675 A CN 112883675A
- Authority
- CN
- China
- Prior art keywords
- model
- voltage
- sub
- drain terminal
- parameters
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
Abstract
The invention discloses a modeling method and a device of a semiconductor device, wherein the method comprises the following steps: adding a voltage-controlled resistor at the drain terminal of the device model based on a BSIMSOI model to obtain a sub-circuit model; then, based on the sub-circuit model, model parameters of the sub-circuit model are extracted. The invention is improved on the basis of the BSIMSOI model, and the deviation problem generated by ohmic contact and freezeout effect in the device model can be effectively solved after the voltage-controlled resistor is added.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device modeling method and device.
Background
The model is a bridge between device technology and circuit design. Current process manufacturers can only provide industrial model libraries at-40 ℃ to 80 ℃, and can only provide military-compliant device models at-55 ℃ to 125 ℃ at most. However, at very low temperatures, the effect of the freezeout effect on device performance needs to be considered, and at present, model studies at very low temperatures are relatively few. Currently, a mainstream MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) device model in the industry is a BSIM model, and a corresponding SOI (Silicon-On-Insulator, Silicon On an insulating substrate) MOSFET device model is a bsimson model.
However, the BSIMSOI model includes most of the physical effects, but does not consider the influence of the freezeout effect on the device performance, and the ohmic contact becomes schottky at an extremely low temperature and increases in resistance, and decreases in resistance as the applied voltage increases. Therefore, when the BSIMSOI model is directly adopted for modeling and parameter extraction at present, the device model deviation can occur at extremely low temperature.
Disclosure of Invention
In view of the above problems, the present invention provides a method and an apparatus for modeling a semiconductor device, which can effectively solve the deviation problem caused by ohmic contact and freezeout effect in a device model.
In a first aspect, the present application provides the following technical solutions through an embodiment:
a method of modeling a semiconductor device, comprising:
adding a voltage-controlled resistor at the drain terminal of the device model based on a BSIMSOI model to obtain a sub-circuit model; and extracting model parameters of the sub-circuit model based on the sub-circuit model.
Optionally, the step of adding a voltage-controlled resistor at the drain terminal of the device model based on the BSIMSOI model to obtain a sub-circuit model includes:
defining drain external voltage, drain internal voltage and parameters of a device model based on the BSIMSOI model; defining the voltage-controlled resistor based on the external voltage of the drain terminal and the internal voltage of the drain terminal to obtain a sub-circuit model; the voltage-controlled resistor is positioned between the external voltage of the drain terminal and the internal voltage of the drain terminal.
Optionally, the parameters include: model coefficients corresponding to the voltage-controlled resistors; the extracting model parameters of the sub-circuit model based on the sub-circuit model comprises:
and extracting model parameters of the sub-circuit model based on the sub-circuit model, the model coefficients and the external voltage of the drain terminal.
Optionally, the parameters further include: a preset voltage corresponding to the voltage-controlled resistor; the extracting model parameters of the sub-circuit model based on the sub-circuit model comprises:
and extracting model parameters of the sub-circuit model based on the sub-circuit model, the model coefficient, the external voltage of the drain terminal and the preset voltage.
Optionally, the extracting the model parameter of the sub-circuit model based on the sub-circuit model, the model coefficient, the drain external voltage, and the preset voltage includes:
obtaining a correlation coefficient based on the external voltage of the drain terminal and the preset voltage; the correlation coefficient is the minimum value between the external voltage of the drain terminal and the preset voltage; obtaining a resistance model of the voltage-controlled resistor based on the model coefficient and the correlation coefficient; and extracting model parameters of the sub-circuit model based on the sub-circuit model and the resistance model.
In a second aspect, based on the same inventive concept, the present application provides the following technical solutions through an embodiment:
a semiconductor device modeling apparatus, comprising:
the model building module is used for increasing a voltage-controlled resistor at the drain terminal of the device model based on the BSIMSOI model to obtain a sub-circuit model; and the parameter extraction module is used for extracting model parameters of the sub-circuit model based on the sub-circuit model.
Optionally, the model building module is specifically configured to:
defining drain external voltage, drain internal voltage and parameters of a device model based on the BSIMSOI model; defining the voltage-controlled resistor based on the external voltage of the drain terminal and the internal voltage of the drain terminal to obtain a sub-circuit model; the voltage-controlled resistor is positioned between the external voltage of the drain terminal and the internal voltage of the drain terminal.
Optionally, the parameters include: model coefficients corresponding to the voltage-controlled resistors; the parameter extraction module is specifically configured to:
and extracting model parameters of the sub-circuit model based on the sub-circuit model, the model coefficients and the external voltage of the drain terminal.
Optionally, the parameters further include: a preset voltage corresponding to the voltage-controlled resistor; the parameter extraction module is further specifically configured to:
and extracting model parameters of the sub-circuit model based on the sub-circuit model, the model coefficient, the external voltage of the drain terminal and the preset voltage.
In a third aspect, based on the same inventive concept, the present application provides the following technical solutions through an embodiment:
a computer-readable storage medium, having stored thereon a computer program which, when being executed by a processor, carries out the steps of the method of any of the first aspects.
According to the semiconductor device modeling method and device provided by the embodiment of the invention, a voltage-controlled resistor is added at the drain terminal of a device model based on a BSIMSOI model to obtain a sub-circuit model; then, based on the sub-circuit model, model parameters of the sub-circuit model are extracted. In the embodiment, the deviation problem caused by ohmic contact and freezeout effect in the device model can be effectively solved by improving the BSIMSOI model on the basis of adding a voltage-controlled resistor.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts. In the drawings:
fig. 1 is a flow chart illustrating a method for modeling a semiconductor device according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram showing the structure of a macro-model of a sub-circuit formed by a voltage-controlled resistor sub-circuit and a MOS transistor in a first embodiment of the present invention;
FIG. 3 is a diagram showing the fitting result of the device model without adding the voltage-controlled resistance according to the first embodiment of the present invention;
FIG. 4 is a diagram showing the fitting result of the device model for increasing the voltage-controlled resistance according to the first embodiment of the present invention;
fig. 5 is a schematic structural diagram of a modeling apparatus for a semiconductor device according to a second embodiment of the invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
First embodiment
Referring to fig. 1, fig. 1 illustrates a method for modeling a semiconductor device according to a first embodiment of the present invention, which includes the following steps:
step S10: and adding a voltage-controlled resistor at the drain terminal of the device model based on the BSIMSOI model to obtain a sub-circuit model.
In step S10, a BSIMSOI model may be obtained first, then a device model definition is performed, such as a MOS device, and a voltage-controlled resistance is added to the drain of the device model, where the voltage-controlled resistance varies with the external voltage at the drain. Specifically, the drain external voltage, the drain internal voltage and the parameters of the device model can be defined based on a BSIMSOI model; defining a voltage-controlled resistor based on the external voltage of the drain terminal and the internal voltage of the drain terminal to obtain a sub-circuit model; the voltage-controlled resistor is located between the external voltage of the drain terminal and the internal voltage of the drain terminal, as shown in fig. 2, fig. 2 shows a schematic structural diagram of a macro model of a sub-circuit formed by a sub-circuit of the voltage-controlled resistor and a device model (MOS transistor). Specifically, the method further comprises defining a source end, a gate end, a back gate, a bottom end and the like of the device model; the parameters include model coefficients to fit the voltage controlled resistance, as well as other parameters such as temperature, channel length, mobility, etc.
Step S20: and extracting model parameters of the sub-circuit model based on the sub-circuit model.
In step S20, since the voltage-controlled resistance is increased, the model parameters of the sub-circuit model are extracted based on the sub-circuit model, the model coefficients, and the drain external voltage when the parameters are extracted. More specifically, model parameters of the sub-circuit model are extracted based on the sub-circuit model, model coefficients, a drain external voltage, and a preset voltage. When the method is implemented, the steps are as follows:
firstly, a correlation coefficient can be obtained based on an external voltage of a drain terminal and a preset voltage; the correlation coefficient is the minimum value between the external voltage of the drain terminal and a preset voltage; it can be expressed as K ═ min (V (d, s), vcon), where V (d, s) represents the external drain voltage and vcon is a preset voltage. Then, based on the model coefficient and the correlation coefficient, a resistance model of the voltage-controlled resistor is obtained, and the resistance model can represent the change of the resistance value of the voltage-controlled resistor along with the voltage, which can be specifically expressed as ppd0+ ppd1 × K + ppd2 × K2+ppd3*K3+ppd4*K4And ppd 0-ppd 4 are model coefficients. And finally, extracting model parameters of the sub-circuit model based on the sub-circuit model and the resistance model. When extracting model parameters, the parameters including DC parameters are extracted at-196 deg.C according to the standard method in the industry. In addition, the extracted parameters also include coefficients corresponding to voltage-controlled resistors in the resistance model, process parameters, channel length, channel width, mobility, temperature, and the like.
In the embodiment, the voltage-controlled resistance is added, and the voltage-controlled resistance is characterized by the correlation coefficient along with the voltage. When the external voltage of the drain terminal is greater than vcon, the resistance value of the voltage-controlled resistor is a fixed value, namely the resistance value of the voltage-controlled resistor changes in the range of 0-vcon; when the external voltage of the drain terminal is greater than vcon, the resistance value of the voltage-controlled resistor is kept unchanged. Therefore, by adopting the preset voltage when the external voltage of the drain terminal is larger, the segmented representation of the voltage-controlled resistor is realized, and the accuracy of fitting is improved.
An example of code is as follows:
subbckt nmos _ sub d s e p w ═ 1u 'l ═ 1 u'/where d g s e p respectively represent the drain (corresponding drain external voltage), gate, source, backgate and bottom defining the nmos _ sub-circuit, and w, l respectively represent the width and length defining the device model.
.param
+ ppd0 ═ 3.1E3 ppd1 ═ 5.4E3 ppd2 ═ 3.8E3+ ppd3 ═ 0 ppd4 ═ 0 vcon ═ 0.9/, where ppd0 to ppd4 and vcon respectively denote the parameters.
K ═ min (V (d, s), vcon)/V (d, s) represents the drain external voltage, vcon is a preset voltage set, and K is the minimum value between V (d, s) and vcon. Since ohmic contact is schottky at an extremely low temperature, resistance increases, and when applied voltage increases, resistance becomes smaller. Therefore, in the embodiment, the voltage-controlled resistor R1 can be dynamically adjusted by K, so that inter-partition control of a saturation region and a linear region during model simulation is realized, schottky effective fitting is realized, fitting accuracy is improved, and accurate parameters can be extracted.
M1 d1 g s e p nmos w w l l/denotes a mos transistor M1 defined using the BSIMSOI model, where d1 denotes the drain of M1 and the corresponding internal voltage.
R1 d d1'(ppd0+ppd1*K+ppd2*K2+ppd3*K3+ppd4*K4) '/denotes a resistance expression defining the voltage-controlled resistance between nodes d and d1 and the voltage-controlled resistance, and the influence of the ohmic resistance changing with the voltage can be fitted by taking parameters ppd 1-ppd 4 as coefficients of a polynomial.
.ends nmos_sub
It should also be noted that vcon in the above code is process dependent and can be adjusted according to the fitting situation. The value of K is the minimum value of the external voltage of the current drain terminal and the parameter vcon. As in the code of this example, when the drain external voltage is less than 0.9V, K ═ V (d, s); when the external voltage of the drain terminal is more than 0.9V, K is 0.9.
Fitting verification is performed based on the above code example, and results as shown in fig. 3 and 4 can be obtained. Fig. 3 is a fitting result when no voltage-controlled resistor is added based on the BSIMSOI model, and it can be seen that, under the same gate terminal voltage, when the drain terminal external voltage is small, the drain terminal current is significantly large, and the fitting result is poor. Fig. 4 is a fitting result of adding a voltage-controlled resistor based on the BSIMSOI model, and it can be seen that the fitting result is good when the external voltage of the drain terminal increases from small under the same gate terminal voltage. Therefore, in the embodiment, by improving on the basis of the BSIMSOI model, the deviation problem caused by ohmic contact and the freezeout effect in the device model can be effectively solved after the voltage-controlled resistor is added. In addition, in the embodiment, the voltage-controlled resistor is added based on the BSIMSOI model, and the original model source code is still used without developing the device model source code.
Second embodiment
Referring to fig. 5, a semiconductor device modeling apparatus 300 is provided in the present embodiment based on the same inventive concept. The semiconductor device modeling apparatus 300 includes:
the model building module 301 is used for adding a voltage-controlled resistor at the drain terminal of the device model based on the BSIMSOI model to obtain a sub-circuit model; a parameter extraction module 302, configured to extract model parameters of the sub-circuit model based on the sub-circuit model.
As an optional implementation manner, the model building module 301 is specifically configured to:
defining drain external voltage, drain internal voltage and parameters of a device model based on the BSIMSOI model; defining the voltage-controlled resistor based on the external voltage of the drain terminal and the internal voltage of the drain terminal to obtain a sub-circuit model; the voltage-controlled resistor is positioned between the external voltage of the drain terminal and the internal voltage of the drain terminal.
As an optional implementation, the parameters include: model coefficients corresponding to the voltage-controlled resistors; the parameter extraction module 302 is specifically configured to:
and extracting model parameters of the sub-circuit model based on the sub-circuit model, the model coefficients and the external voltage of the drain terminal.
As an optional implementation, the parameter further includes: a preset voltage corresponding to the voltage-controlled resistor; the parameter extraction module 302 is further specifically configured to:
and extracting model parameters of the sub-circuit model based on the sub-circuit model, the model coefficient, the external voltage of the drain terminal and the preset voltage.
As an optional implementation manner, the parameter extraction module 302 is further specifically configured to:
obtaining a correlation coefficient based on the external voltage of the drain terminal and the preset voltage; the correlation coefficient is the minimum value between the external voltage of the drain terminal and the preset voltage; obtaining a resistance model of the voltage-controlled resistor based on the model coefficient and the correlation coefficient; and extracting model parameters of the sub-circuit model based on the sub-circuit model and the resistance model.
It should be noted that, the semiconductor device modeling apparatus 300 according to the embodiment of the present invention is implemented and produces the same technical effects as the foregoing method embodiments, and for the sake of brief description, reference may be made to the corresponding contents in the foregoing method embodiments for the parts of the apparatus embodiments that are not mentioned.
Third embodiment
Based on the same inventive concept, the present embodiment provides a computer-readable storage medium, on which a computer program is stored, which when executed by a processor implements the steps of the method of any one of the first embodiments described above.
It should be noted that, the embodiment of the present invention provides a computer-readable storage medium, wherein the method implemented by the program when executed by the processor and the technical effect produced by the method are the same as the foregoing method embodiment, and for the sake of brief description, for what is not mentioned in the embodiment, reference may be made to the corresponding content in the foregoing method embodiment.
The term "and/or" appearing herein is merely one type of associative relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship; the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A method of modeling a semiconductor device, comprising:
adding a voltage-controlled resistor at the drain terminal of the device model based on a BSIMSOI model to obtain a sub-circuit model;
and extracting model parameters of the sub-circuit model based on the sub-circuit model.
2. The method of claim 1, wherein adding a voltage-controlled resistance at a drain terminal of the device model based on the BSIMSOI model to obtain the sub-circuit model comprises:
defining drain external voltage, drain internal voltage and parameters of a device model based on the BSIMSOI model;
defining the voltage-controlled resistor based on the external voltage of the drain terminal and the internal voltage of the drain terminal to obtain a sub-circuit model; the voltage-controlled resistor is positioned between the external voltage of the drain terminal and the internal voltage of the drain terminal.
3. The method of claim 2, wherein the parameters comprise: model coefficients corresponding to the voltage-controlled resistors; the extracting model parameters of the sub-circuit model based on the sub-circuit model comprises:
and extracting model parameters of the sub-circuit model based on the sub-circuit model, the model coefficients and the external voltage of the drain terminal.
4. The method of claim 3, wherein the parameters further comprise: a preset voltage corresponding to the voltage-controlled resistor; the extracting model parameters of the sub-circuit model based on the sub-circuit model comprises:
and extracting model parameters of the sub-circuit model based on the sub-circuit model, the model coefficient, the external voltage of the drain terminal and the preset voltage.
5. The method of claim 4, wherein extracting model parameters of the sub-circuit model based on the sub-circuit model, the model coefficients, the drain external voltage, and the preset voltage comprises:
obtaining a correlation coefficient based on the external voltage of the drain terminal and the preset voltage; the correlation coefficient is the minimum value between the external voltage of the drain terminal and the preset voltage;
obtaining a resistance model of the voltage-controlled resistor based on the model coefficient and the correlation coefficient;
and extracting model parameters of the sub-circuit model based on the sub-circuit model and the resistance model.
6. A semiconductor device modeling apparatus, comprising:
the model building module is used for increasing a voltage-controlled resistor at the drain terminal of the device model based on the BSIMSOI model to obtain a sub-circuit model;
and the parameter extraction module is used for extracting model parameters of the sub-circuit model based on the sub-circuit model.
7. The apparatus of claim 6, wherein the model building module is specifically configured to:
defining drain external voltage, drain internal voltage and parameters of a device model based on the BSIMSOI model; defining the voltage-controlled resistor based on the external voltage of the drain terminal and the internal voltage of the drain terminal to obtain a sub-circuit model; the voltage-controlled resistor is positioned between the external voltage of the drain terminal and the internal voltage of the drain terminal.
8. The apparatus of claim 7, wherein the parameters comprise: model coefficients corresponding to the voltage-controlled resistors; the parameter extraction module is specifically configured to:
and extracting model parameters of the sub-circuit model based on the sub-circuit model, the model coefficients and the external voltage of the drain terminal.
9. The apparatus of claim 8, wherein the parameters further comprise: a preset voltage corresponding to the voltage-controlled resistor; the parameter extraction module is further specifically configured to:
and extracting model parameters of the sub-circuit model based on the sub-circuit model, the model coefficient, the external voltage of the drain terminal and the preset voltage.
10. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110259512.XA CN112883675A (en) | 2021-03-10 | 2021-03-10 | Semiconductor device modeling method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110259512.XA CN112883675A (en) | 2021-03-10 | 2021-03-10 | Semiconductor device modeling method and device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112883675A true CN112883675A (en) | 2021-06-01 |
Family
ID=76054078
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110259512.XA Pending CN112883675A (en) | 2021-03-10 | 2021-03-10 | Semiconductor device modeling method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112883675A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101976283A (en) * | 2010-10-21 | 2011-02-16 | 中国科学院上海微系统与信息技术研究所 | Method for determining BSIMSOI4 (Berkeley Short-channel IGFET Model Silicon on Insulator 4) direct current model parameter |
| US20120187975A1 (en) * | 2011-01-24 | 2012-07-26 | Renesas Electronics Corporation | Semiconductor device evaluation apparatus and semiconductor device evaluation method |
| US20130030774A1 (en) * | 2011-07-29 | 2013-01-31 | Globalfoundries Inc. | Modeling Gate Transconductance in a Sub-Circuit Transistor Model |
| WO2014012300A1 (en) * | 2012-07-17 | 2014-01-23 | 中国科学院微电子研究所 | Soi mos device modeling method |
| CN104951599A (en) * | 2015-06-04 | 2015-09-30 | 中国科学院微电子研究所 | SOIMOSFET device modeling method |
| CN112052636A (en) * | 2020-08-31 | 2020-12-08 | 中国科学院微电子研究所 | BSIMSOI-based FDSOI MOSFET device modeling method and device |
-
2021
- 2021-03-10 CN CN202110259512.XA patent/CN112883675A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101976283A (en) * | 2010-10-21 | 2011-02-16 | 中国科学院上海微系统与信息技术研究所 | Method for determining BSIMSOI4 (Berkeley Short-channel IGFET Model Silicon on Insulator 4) direct current model parameter |
| US20120187975A1 (en) * | 2011-01-24 | 2012-07-26 | Renesas Electronics Corporation | Semiconductor device evaluation apparatus and semiconductor device evaluation method |
| US20130030774A1 (en) * | 2011-07-29 | 2013-01-31 | Globalfoundries Inc. | Modeling Gate Transconductance in a Sub-Circuit Transistor Model |
| WO2014012300A1 (en) * | 2012-07-17 | 2014-01-23 | 中国科学院微电子研究所 | Soi mos device modeling method |
| CN104951599A (en) * | 2015-06-04 | 2015-09-30 | 中国科学院微电子研究所 | SOIMOSFET device modeling method |
| CN112052636A (en) * | 2020-08-31 | 2020-12-08 | 中国科学院微电子研究所 | BSIMSOI-based FDSOI MOSFET device modeling method and device |
Non-Patent Citations (4)
| Title |
|---|
| MUTHUBALAN VARADHARAJAPERUMAL 等: "Modeling of High Frequency Noise in SOI MOSFETs", 2010 23RD INTERNATIONAL CONFERENCE ON VLSI DESIGN, pages 212 - 217 * |
| WENJUN LI 等: "An improved model for substrate in RF SOI MOSFET varactor", INTERNATIONAL JOURNAL OF NUMERICAL MODELLING: ELECTRONIC NETWORKS, DEVICES AND FIELDS, vol. 30, no. 2, pages 1 - 12 * |
| 周文勇: "基于BSIMSOI的SOI-MOSFET模型研究", 中国优秀硕士学位论文全文数据库（信息科技辑）, pages 135 - 315 * |
| 黄瑜萍: "SOI MOSFET高频特性及噪声模型研究", 中国优秀硕士学位论文全文数据库（信息科技辑）, pages 135 - 536 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100517766B1 (en) | Circuit simulation apparatus incorporating diffusion length dependence of transistors and method for creating transistor model | |
| US8606557B2 (en) | Table lookup method for physics based models for SPICE-like simulators | |
| WO2023207184A1 (en) | Data selection method, system and apparatus for extracting device model parameters of integrated circuit | |
| US20100169848A1 (en) | Method of Migrating Electronic Devices Operating in Current Mode to a Target Technology | |
| US20130024828A1 (en) | Solutions for netlist reduction for multi-finger devices | |
| CN113221489A (en) | Method and apparatus for extracting device model parameters of an integrated circuit device | |
| JP3269459B2 (en) | MISFET overlap length measuring method, measuring device, and recording medium recording extraction program | |
| JPWO2010041633A1 (en) | Simulation method and simulation apparatus | |
| CN105226054B (en) | A kind of general mismatch model and its extracting method | |
| CN112883675A (en) | Semiconductor device modeling method and device | |
| Roy et al. | Numerically convex forms and their application in gate sizing | |
| Ibáñez et al. | A comprehensive characterization of the threshold voltage extraction in MOSFETs transistors based on smoothing splines | |
| CN106802991B (en) | Simulation method of MOS device | |
| Kondo et al. | Model-adaptable MOSFET parameter-extraction method using an intermediate model | |
| CN112861297B (en) | MOS transistor feature extraction method, device, medium and electronic equipment | |
| CN106446476A (en) | General layout proximity effect representation model and extracting method thereof | |
| Jia et al. | A novel surface potential-based short channel MOSFET model for circuit simulation | |
| CN109388911B (en) | Equivalent model establishing method and device for semiconductor device and terminal equipment | |
| JP2005340340A (en) | Semiconductor simulation apparatus and method therefor | |
| CN112052636A (en) | BSIMSOI-based FDSOI MOSFET device modeling method and device | |
| CN105844006B (en) | A kind of MOSFET BSIM4 sub-circuits device model and its modeling method | |
| CN113095037B (en) | MOS device flicker noise model and extraction method | |
| KR100567069B1 (en) | Method for design of semiconductor device | |
| JP5546160B2 (en) | Model parameter determination device, model parameter determination method and program | |
| Habal et al. | Evaluating analog circuit performance in light of MOSFET aging at different time scales |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |