JP2005340340A - Semiconductor simulation apparatus and method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor simulation apparatus and a semiconductor simulation method capable of calculating, with high accuracy, a gate-drain capacitance when source-drain voltage of a MOS transistor is not 0 V. <P>SOLUTION: A process simulator 21 executes process simulation to calculate a shape/impurity distribution 23. A device simulator 22 executes device simulation to calculate gate-drain capacitance (C-V characteristic 5) when source-drain voltage is not 0 V. A calibration part 13 changes a model parameter used for the simulation such that a simulation result is coincident with a previously given actual measured value. Consequently, it is possible to calculate the gate to drain capacitance of the MOS transistor. As a result, it is possible to accurately estimate delay time of circuit elements of an LSI. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor simulation apparatus and a semiconductor simulation method, and more particularly to a semiconductor simulation apparatus and a semiconductor simulation method for calculating a capacitance between a gate and a drain of a MOS transistor.

  In LSI (Large Scale Integration) design, where miniaturization is progressing, new technologies such as phase shift and OPC (Optical Proximity Correction) are introduced as layout design technologies, and the mask cost is 100 million yen. The level has been exceeded. For this reason, it is not easy to remake the mask, and it is very important to verify the circuit operation before the mask is made. In order to verify the circuit operation, it is necessary to accurately know the delay time of each element constituting the circuit. Usually, the delay time of each circuit element is calculated using a circuit simulator such as SPICE (Simulation Program with Integrated Circuit Emphasis) developed at the University of California, Berkeley, USA.

  In order to accurately calculate the delay time, it is necessary to accurately know the gate capacitance of the MOS transistor. There are several types of gate capacitances, but here, in particular, the capacitance between the gate and drain of a MOS transistor (hereinafter also simply referred to as gate-drain capacitance) is targeted.

  Conventionally, the gate-drain capacitance of a MOS transistor was actually measured using a semiconductor parameter analyzer and an impedance analyzer. In this case, a constant potential is applied to the substrate of the MOS transistor by the semiconductor parameter analyzer. Also, one terminal of the impedance analyzer is connected to the source and drain of the MOS transistor, the other terminal is connected to the gate of the MOS transistor, and an AC bias is applied between these two terminals so that the capacitance between the gate and drain of the MOS transistor Measure.

Patent Document 1 below discloses a method for improving circuit simulation accuracy by extracting a parasitic capacitance (overlap capacitance value) of an overlapping portion of a gate electrode and a source / drain region of a MOS transistor with a small area test pattern with high accuracy. Is disclosed.
JP 2002-261272 A

  As described above, in the conventional method for measuring the gate-drain capacitance of the MOS transistor, the measurement is performed with the source-drain voltage fixed at 0V. In this case, the gate-drain capacitance can be measured with high accuracy.

  However, when the MOS transistor operates in an actual circuit, the source-drain voltage is not 0V. Since the characteristics of the gate capacitance change depending on the source-drain voltage, it is necessary to know the gate capacitance when the source-drain voltage is not 0 V in order to accurately estimate the delay time of each circuit element.

  Therefore, a constant potential is applied to the substrate and source of the MOS transistor by the semiconductor parameter analyzer, one terminal of the impedance analyzer is connected to the drain of the MOS transistor, the other terminal is connected to the gate of the MOS transistor, and between these two terminals. There is a method of measuring the gate-drain capacitance of a MOS transistor by applying an AC bias to the MOS transistor. However, in this case, there is a problem that the gate-drain capacitance is not accurately measured because the source-drain voltage is not accurately fixed at a constant value due to the influence of the AC bias for measurement. This is particularly noticeable in a fine MOS transistor having a short gate length.

  SUMMARY OF THE INVENTION Therefore, a main object of the present invention is to provide a semiconductor simulation apparatus and a semiconductor simulation method capable of calculating with high accuracy the gate-drain capacitance when the source-drain voltage of the MOS transistor is not 0V. .

  A semiconductor simulation apparatus according to the present invention is a semiconductor simulation apparatus for calculating a capacitance between a gate and a drain of a transistor, a geometric dimension that defines the structure of the transistor, and a process flow that defines a manufacturing process of the transistor, The process simulation is executed using the first parameter necessary for the simulation, the process simulator for calculating the impurity distribution of the transistor, the impurity distribution calculated by the process simulator, and the bias indicating the bias applied to the electrode of the transistor A device simulation is performed using the conditions and the second parameter necessary for the simulation, and a capacitance for calculating the capacitance between the gate and the drain when the voltage between the source and the drain of the transistor is not zero is calculated. It is that a chair simulator.

  A semiconductor simulation method according to the present invention is a semiconductor simulation method for calculating a capacitance between a gate and a drain of a transistor, a geometric dimension that defines the structure of the transistor, and a process flow that defines a manufacturing process of the transistor, First, a process simulation is executed using the first parameter necessary for the simulation, and the first step of calculating the impurity distribution of the transistor, the impurity distribution calculated by the first step, and the application to the transistor electrode A device simulation is executed using a bias condition indicating a bias and a second parameter necessary for the simulation, and a second step of calculating electrical characteristic data of the transistor, and an impurity distribution calculated by the first step Is given in advance The first parameter is calibrated to match the first actual measurement value within the allowable range, and the electrical characteristic data calculated in the second step matches the second actual measurement value given in advance within the allowable range. A first step in which the third step for calibrating the second parameter, the impurity distribution calculated by the first step, and the electrical characteristic data calculated by the second step are respectively given in advance. A fourth step of performing device simulation to calculate the capacitance between the gate and the drain when the voltage between the source and the drain of the transistor is not zero when the second measured value is within an allowable range; including.

  In the semiconductor simulation apparatus according to the present invention, the process simulation is executed using the geometric dimension that defines the structure of the transistor, the process flow that defines the manufacturing process of the transistor, and the first parameter necessary for the simulation, Execute device simulation using the process simulator for calculating the impurity distribution of the transistor, the impurity distribution calculated by the process simulator, the bias condition indicating the bias applied to the electrode of the transistor, and the second parameter required for the simulation A device simulator for calculating the capacitance between the gate and the drain when the voltage between the source and the drain of the transistor is not zero is provided. Therefore, the capacitance between the gate and the drain when the voltage between the source and the drain of the transistor is not 0 V can be calculated with high accuracy. As a result, the delay time of each circuit element of the LSI can be accurately estimated, so that mask rework can be avoided, the development cost of the LSI can be kept low, and the development period can be shortened.

  In the semiconductor simulation method according to the present invention, the process simulation is executed using the geometric dimensions that define the structure of the transistor, the process flow that defines the manufacturing process of the transistor, and the first parameter necessary for the simulation, Using the first step for calculating the impurity distribution of the transistor, the impurity distribution calculated by the first step, the bias condition indicating the bias applied to the electrode of the transistor, and the second parameter required for the simulation The device simulation is executed, and the second step of calculating the electrical characteristic data of the transistor and the impurity distribution calculated by the first step are matched with the first measured value given in advance within an allowable range. Calibrate the first parameter and go to the second step A third step of calibrating the second parameter so that the electrical characteristic data calculated in the above agrees with a second measured value given in advance within an allowable range, and the impurity calculated by the first step When the distribution and the electrical characteristic data calculated in the second step coincide with the first and second measured values given in advance within an allowable range, a device simulation is performed to determine the source of the transistor A fourth step is provided for calculating the capacitance between the gate and drain when the voltage across the drain is not zero. Therefore, the capacitance between the gate and the drain when the voltage between the source and the drain of the transistor is not 0 V can be calculated with high accuracy. As a result, the delay time of each circuit element of the LSI can be accurately estimated, so that mask rework can be avoided, the development cost of the LSI can be kept low, and the development period can be shortened.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a schematic configuration of a semiconductor simulation apparatus 1 according to the first embodiment of the present invention. In FIG. 1, the semiconductor simulation apparatus 1 includes an input unit 11, a simulation unit 12, a calibration unit 13, and an output unit 14. The simulation unit 12 includes a process simulator 21 and a device simulator 22. Input data 2, process flow 3 and model parameter 4 are given to input unit 11. The CV characteristic 5 is output from the output unit 14. The shape / impurity distribution 23 is calculated by the process simulator 21 and given to the device simulator 22.

  The input unit 11 includes external input data 2 such as a bias condition (source-drain voltage Vds, gate-source voltage Vgs) and a geometric dimension (gate length Lg) of the MOS transistor, and a series of integrated circuit manufacturing. A process flow 3 indicating a process (ion implantation process, oxidation process, impurity diffusion process, etc.) and model parameters 4 such as an impurity diffusion coefficient, a segregation coefficient, a point defect parameter, and a mobility parameter necessary for the simulation are read. Here, the source-drain voltage Vds given as the bias condition is a voltage other than 0 V (for example, 0.5 V).

  The process simulator 21 executes a process simulation using the input data 2 and the model parameter 4 according to the contents of the process flow 3 read by the input unit 11 to calculate the shape / impurity distribution 23 of the MOS transistor. The device simulator 22 executes a device simulation for obtaining the electrical characteristics of the MOS transistor by using the shape / impurity distribution 23 calculated by the process simulator 21, the input data 2 read by the input unit 11, and the model parameter 4. Then, a CV characteristic 5 representing the relationship between the gate-drain capacitance Cgd of the MOS transistor and the gate-source voltage Vgs is calculated.

  The calibration unit 13 changes the model parameters used for the simulation so that the execution results of the process simulation and the device simulation coincide with the actually measured values given in advance. The process simulator 21 and the device simulator 22 execute simulation again using the changed model parameter. This operation is repeated until a sufficient match is found between the simulation result and the actually measured value. Since the accuracy of process simulation and device simulation is not sufficient, it is necessary to change the model parameters in this way.

  The output unit 14 outputs the CV characteristic 5 calculated by the device simulator 22 to the outside. This CV characteristic 5 is displayed on a monitor as a graph or numerical data, or output as a file, for example.

  FIG. 2 is a conceptual diagram for explaining the gate-drain capacitance Cgd of the MOS transistor. Referring to FIG. 2, the MOS transistor capacitance includes gate-drain capacitance Cgd, gate-source capacitance Cgs, gate-substrate capacitance Cgb, drain-substrate capacitance Cjd, source-substrate capacitance Cjs, and the like. Exists. In order to accurately calculate the delay time of the circuit element, it is necessary to accurately know the gate-drain capacitance Cgd when the source-drain voltage of the MOS transistor is not 0V.

  FIG. 3 is a block diagram for explaining the operation of the simulation unit 12 shown in FIG. 1 in detail. Referring to FIG. 3, device simulator 22 includes sub simulators 24 and 25.

  The process simulator 21 is a process flow showing input data such as a MOS transistor geometric dimension (gate length Lg) and a series of integrated circuit manufacturing processes (ion implantation process, impurity diffusion process, oxidation process, etching process, etc.). And a process simulation is executed using model parameters such as an impurity diffusion coefficient, a segregation coefficient, and a point defect parameter necessary for the process simulation. This makes it possible to predict the processed shape of the device and the impurity distribution inside the device without actually making a prototype of the device.

  Here, the impurity diffusion process in the manufacturing process executed by the process simulator 21 will be described. Various models have been proposed as models used for the simulation of the impurity diffusion process. For example, it is described in the literature (T. Uchida, “Simulation of Dopant Redistribution During Gate Oxidation Including Transient-Enhanced Diffusion Caused by Implantation Damage”, Jpn. J. Appl. Phys. Vol. 39 (2000), pp. 2565-2576). In the Mulvaney model, the following basic equations (1) to (4) are used.

Here, C _A and N _A are the chemical concentration and the activation concentration of the dopant impurity A, respectively. C _I , C _V , and C ₃₁₁ are the concentrations of free interstitial silicon, vacancies, and interstitial silicon trapped in clusters. a _Si is the average interatomic distance of silicon, α is the capture radius, and K _decluster is the _decluster rate of the interstitial silicon cluster. J _A ↑, J _I ↑, and J _V ↑ indicate the fluxes of dopant impurities, interstitial silicon, and vacancies, respectively, and are expressed by the following formulas (5) to (7). The arrow ↑ represents a vector.

Here, D _I and D _V are the diffusion coefficients of interstitial silicon and holes, respectively. C ^* _I and C ^* _V are thermal equilibrium concentrations of interstitial silicon and vacancies, respectively. f _IA is the ratio of the portion due to the interstitial mechanism in the dopant diffusion. K _AI and K _AV are pair reaction coefficients between dopant impurities and point defects (interstitial silicon, vacancies), respectively. K _R is the recombination velocity between interstitial silicon and vacancies. Z _A is the charge of the dopant impurity A, and n is the electron density.

D ^* _A is the impurity diffusion coefficient of the dopant impurity A in the thermal equilibrium state. There are four types of vacancies with different charge states ^: V ⁺ , V ⁰ , V ⁻ and V ²⁻ . Diffusion coefficient by each cavity _{^{is, D + A, D 0 A}} , D - A, represented by D _^2-A. The impurity diffusion coefficient D ^* _A including the contribution of vacancies in various charged states is expressed by the following formula (8).

Here, n _i is the intrinsic carrier concentration. In addition, it is important to set boundary conditions in the impurity diffusion process. Boundary conditions for point defects at the silicon / oxide film interface are expressed by the following mathematical formulas (9) to (11).

Here, n ↑ is the unit normal vector outward from the silicon region, and K _I and K _V are the surface coupling rates of interstitial silicon and holes, respectively. g _I is the flux of interstitial silicon generated at the interface due to oxidation, | v _interface | ^s is the moving speed of the silicon / oxide interface during oxidation, N _Si is the number density of silicon, and θ is the consumed silicon It is the ratio of what is injected into the substrate silicon.

The main variables in the impurity diffusion process are C _A , C _I and C _V. D _I , D _V , C ^* _I , C ^* _V , K _R , K _I and K _V are called point defect parameters.

  In addition, as described in the literature (edited by Dan Ryo, “Process, Device, and Simulation Technology” Industrial Book, 1988, p. 43-45), it is one of the phenomena related to the oxidation process in process simulation. The redistribution of dopant impurities at the silicon / oxide interface is important. In the thermal equilibrium state, the impurities redistribute so that the chemical potentials coincide on both sides of the silicon / oxide interface. This phenomenon is called segregation.

When a phenomenological model is used to explain the segregation of impurities in the thermal equilibrium state, the impurity flux J _s ↑ at the silicon / oxide film interface is expressed by the following equation (12).

Here, m _eq is a segregation coefficient, and h is a mass transport coefficient. C _A [Si] and C _A [SiO ₂ ] are the concentrations of the dopant impurity A on the silicon side and the oxide film side, respectively.

  4 and 5 are diagrams showing the shape and impurity distribution obtained by the process simulation. FIG. 4 shows the donor concentration distribution, and FIG. 5 shows the acceptor concentration distribution. FIG. 6 is a diagram showing a state of mesh division for discretization and executing a simulation. Referring to FIG. 6, the analysis region is divided into a plurality of regions by the mesh, and the shape / impurity distribution as shown in FIGS. 4 and 5 is obtained by solving the equation at each mesh point.

  Referring to FIG. 3 again, the device simulator 22 includes the transistor shape / impurity distribution 23 calculated by the process simulator 21, the MOS transistor bias conditions (source-drain voltage Vds, gate-source voltage Vgs), and the like. A device simulation for obtaining the electrical characteristics of the MOS transistor is executed using model parameters such as input data and mobility parameters. The sub-simulator 24 includes a potential distribution, an electron density distribution, a hole density distribution, an IV characteristic indicating a relationship between the current and bias of the MOS transistor, a threshold voltage Vth at which the MOS transistor conducts, and a gate length of the MOS transistor. A Vth-Lg characteristic indicating a relationship with Lg is calculated. The sub simulator 25 calculates a CV characteristic indicating the relationship between the gate capacitance of the MOS transistor and the bias. Here, the source-drain voltage Vds given as the bias condition is a voltage other than 0 V (for example, 0.5 V). With this device simulation, it is possible to grasp in detail electrically and physically even matters that cannot be measured with current technology and transient phenomena. In the device simulation, the following basic equations (13) to (15) are used.

Here, φ is a potential, n is an electron density, p is a hole density, ε is a dielectric constant of silicon, and q is a charge amount of electrons. N _D is the donor concentration, N _A is the acceptor concentration, and G is the number of electrons (or the number of holes) generated per unit time and unit volume. J _n ↑ and J _p ↑ are an electron current and a hole current, respectively, and are expressed by the following equations (16) and (17).

Here, μ _n and μ _p are the mobility of electrons and holes, respectively, and D _n and D _p are the diffusion coefficients of electrons and holes, respectively. Equation (13) is called Poisson's equation, Equation (14) is called the continuity equation of electron current, and Equation (15) is called the continuity equation of hole current. The main variables in device simulation are φ, n, and p.

  The device simulator 22 reads the donor concentration distribution and the acceptor concentration distribution (see FIGS. 4 and 5) from the process simulator 21 and maps them on the mesh shown in FIG. 6 for all the specified bias conditions. Solve basic equations (13)-(15). As a result, a potential distribution, an electron density distribution, and a hole density distribution are required. Further, by integrating the current density on each electrode (gate, drain, source), the current of each electrode is calculated and plotted against specified bias conditions to obtain IV characteristics.

  Also, the shape / impurity distribution is calculated by process simulation for the geometric dimension (gate length Lg) given as input data, and IV characteristics are obtained by device simulation based on the calculated shape / impurity distribution. It is done. The threshold voltage Vth of the MOS transistor is obtained from this IV characteristic, and the Vth-Lg characteristic is obtained.

  Further, as shown in the following formula (18), according to Gauss's law, the integration of the electric field vector E ↑ along the closed phase surrounding the electrode is equal to the electrode charge Q divided by the dielectric constant ε. .

The gate electrode charge Q _g corresponding to a certain drain voltage V _d specified in the bias condition, and the gate electrode charge (Q _g + dQ _g ) corresponding to the drain voltage (V _d + dV _d ) changed by a minute voltage. Is calculated, the gate-drain capacitance Cgd shown in the following formula (19) is calculated.

  The calculation of the gate-drain capacitance Cgd according to the equation (19) is performed on the gate-source voltage Vgs having a plurality of values specified in the bias condition, thereby obtaining the CV characteristic.

  In the device simulation, it is necessary to model the mobility μ. Many models have been proposed for the mobility μ, and is represented by, for example, the following formula (20).

  FIG. 7 is a flowchart showing a procedure for calculating the gate-drain capacitance (Cgd-Vgs characteristic) by the semiconductor simulation apparatus 1. Referring to FIGS. 1 and 7, in step S <b> 1, a process simulation is executed by process simulator 21 to calculate MOS transistor shape / impurity distribution 23.

  In step S2, device simulation by the sub simulator 24 is executed using the shape / impurity distribution 23 calculated by the process simulator 21, and the Ids-Vgs characteristic in the linear region, the Ids-Vgs characteristic, and the Ids-Vds characteristic in the saturation region. And the Vth-Lg characteristic is calculated.

  In step S3, the calibration unit 13 compares the execution results of the process simulation and the device simulation with the corresponding previously measured values, and if they do not match within the allowable range (NO), the process proceeds to step S4. In step S4, model parameters (point defect parameters, impurity diffusion coefficients, segregation coefficients, mobility parameters, etc.) are obtained by the calibration unit 13 so that the execution results of the process simulation and the device simulation coincide with the corresponding predetermined actual measurement values. ) Is changed.

  Returning to step S1 again, the process simulator 21 performs a simulation again using the changed model parameters (point defect parameters, impurity diffusion coefficients, segregation coefficients, etc.). In step S2, the sub-simulator 24 performs the simulation again using the changed model parameter (such as mobility parameter). This series of operations is repeated until the simulation result and the actually measured value given in advance match within an allowable range.

FIG. 8 is a diagram for explaining how the donor concentration calculated by the process simulation is calibrated by changing the point defect parameter C ^* _I (thermal equilibrium concentration of interstitial silicon). Referring to FIG. 8, the donor concentration immediately after the dopant impurity is implanted in the simulation of the ion implantation process, and the point defect parameter C ^* _I in the simulation of the impurity diffusion process is 4 times, 2 times, 1 time, 1/2. It shows the donor concentration when changed to double. Further, the actually measured values given in advance are indicated by black dots. In this case, in order to make the donor concentration calculated by the process simulation coincide with the actually measured value, the point defect parameter C ^* _I may be changed to about twice. By changing the point defect parameter C ^* _I in this way, the donor concentration distribution and the acceptor concentration distribution (see FIGS. 4 and 5) calculated from the process simulator 21 are calibrated.

  FIG. 9 is a diagram for explaining how the Ids-Vgs characteristic (linear region) calculated by device simulation is calibrated by changing the mobility parameter α. Referring to FIG. 9, the simulation result of the Ids-Vgs characteristic in the linear region (region corresponding to the low drain-source voltage Vds) calculated by the sub-simulator 24 before and after calibration by the calibration unit 13 is shown. Further, the actually measured values given in advance are indicated by black dots. In this case, in order to make the Ids-Vgs characteristic (linear region) calculated by device simulation coincide with the actual measurement value, the mobility parameter α may be changed to a large value. Thus, by changing the mobility parameter α, the Ids-Vgs characteristic (linear region) calculated from the sub simulator 24 is calibrated.

  FIG. 10 is a diagram for explaining how the Ids-Vgs characteristic (saturation region) calculated by device simulation is calibrated by changing the mobility parameter α. Referring to FIG. 10, the simulation result of the Ids-Vgs characteristic in the saturation region (region corresponding to the high drain-source voltage Vds) calculated by the sub simulator 24 before and after calibration by the calibration unit 13 is shown. . Further, the actually measured values given in advance are indicated by black dots. In this case, in order to make the Ids-Vgs characteristic (saturation region) calculated by device simulation coincide with the actual measurement value, the mobility parameter α may be changed to a large value. Thus, by changing the mobility parameter α, the Ids-Vgs characteristic (saturation region) calculated from the sub simulator 24 is calibrated.

11, by changing the mobility parameter v _s, is a diagram for explaining how the Ids-Vds characteristics calculated by device simulation is calibrated. Referring to FIG. 11, the simulation result of the Ids-Vds characteristic calculated by the sub simulator 24 before and after calibration by the calibration unit 13 is shown. Further, the actually measured values given in advance are indicated by black dots. In this case, in order to match the Ids-Vds characteristics calculated by device simulation and the measured values may be changed mobility parameter v _s to a smaller value. By changing the way the mobility parameter v _s, Ids-Vds characteristics calculated from the sub-simulator 24 is calibrated.

FIG. 12 is a diagram for explaining how the Vth-Lg characteristics calculated by device simulation are calibrated by changing the point defect parameters D _I and K _I. With reference to FIG. 12, the simulation result of the Vth-Lg characteristic calculated by the sub simulator 24 before and after calibration by the calibration unit 13 is shown. Further, the actually measured values given in advance are indicated by black dots. In this case, in order to make the Vth-Lg characteristic calculated by the device simulation coincide with the actual measurement value, the point defect parameter (D _I / K _I ) may be changed to a large value. In this way, by changing the point defect parameter (D _I / K _I ), the Vth-Lg characteristic calculated from the sub simulator 24 is calibrated.

Although not shown, the process simulation, Ya model parameters, such as other point defect parameters ^{_{D I, D V, C *}} V, K R, K I, K V, the impurity diffusion coefficient D ^* _A, the segregation coefficient m _eq The model parameters used in other manufacturing processes (for example, the range in the ion implantation process) may be changed.

  In the device simulation, model parameters other than the mobility parameters α and vs may be changed.

  Returning to FIG. 7, in step S3, if the execution results of the process simulation and the device simulation coincide with the corresponding measured values within the allowable range (YES), the process proceeds to step S5. In step S5, a device simulation is executed by the sub simulator 25, and a Cgd-Vgs characteristic is calculated.

  FIGS. 13A to 13E are device simulations for geometric dimensions (gate lengths Lg = 0.10 μm, 0.20 μm, 0.50 μm, 1.0 μm, 10.0 μm) given as input data, respectively. It is a figure which shows the Cgd-Vgs characteristic calculated by these. 13A to 13E, simulation results for the bias condition (source-drain voltage Vds = 0.0 V) given as input data are indicated by dotted lines, and the bias condition (source-drain voltage Vds = The simulation results for 0.5V) are indicated by solid lines. In this case, the gate-drain capacitance Cgd when the source-drain voltage Vds = 0.5V is smaller than the gate-drain capacitance Cgd when the source-drain voltage Vds = 0.0V. Thus, when the source-drain voltage Vds is increased, the channel depletion layer width is increased, so that the gate-drain capacitance Cgd is decreased.

  FIG. 14 is a diagram showing a measurement result of Cgd-Vgs characteristics by a conventional method. FIG. 14 shows the actual measurement results for the geometric dimension (gate length Lg = 0.20 μm). The actual measurement result under the bias condition (source-drain voltage Vds = 0.0 V) is indicated by a dotted line, and the actual measurement result under the bias condition (source-drain voltage Vds = 0.5 V) is indicated by a solid line. In this case, the gate-drain capacitance Cgd when the source-drain voltage Vds = 0.5V is larger than the gate-drain capacitance Cgd when the source-drain voltage Vds = 0.0V.

  Comparing FIG. 13B and FIG. 14, when the gate length Lg given as input data is 0.20 μm, the Cgd-Vgs characteristics corresponding to the source-drain voltage Vds = 0.0 V are almost the same. However, the Cgd-Vgs characteristics corresponding to the source-drain voltage Vds = 0.5 V are different. The measured Cgd-Vgs characteristic shown in FIG. 14 contradicts the theory that the gate-drain capacitance Cgd decreases as the source-drain voltage Vds increases. As described above, the conventional method based on actual measurement has a problem that the gate-drain capacitance Cgd cannot be accurately measured. However, the Cgd-Vgs characteristic calculated by the simulation shown in FIG. 13 is consistent with the theory that the gate-drain capacitance Cgd decreases as the source-drain voltage Vds increases.

  FIG. 15 is a diagram showing a hardware configuration of the semiconductor simulation apparatus 1 shown in FIG. Referring to FIG. 15, the semiconductor simulation apparatus 1 includes a CPU (central processing unit) 31, a bus 32, a magnetic storage device 33, an external device connection unit 34, a monitor 35, a keyboard 36, a mouse 37, a communication unit 38, and a printer output. Part 39 is included.

  The CPU 31 is connected to the magnetic storage device 33, the external device connection unit 34, the monitor 35, the keyboard 36, the mouse 37, the communication unit 38, and the printer output unit 39 via the bus 32, and controls the entire semiconductor simulation device 1. The magnetic storage device 33 stores an operating system (OS) 41 that is basic software, a program group 42 that defines the operation of simulation, and a data group 43 that is used for simulation. The optical disk drive 53 is connected to the external device connection unit 34 and reads the program 51 and data 52. The program 51 and data 52 read by the optical disk drive 53 are stored in the program group 42 and the data group 43, respectively.

  The user operates the semiconductor simulation apparatus 1 using the keyboard 36 and the mouse 37. The monitor 35 displays information necessary for the user such as a simulation result. The communication unit 38 communicates with an external device. The printer 54 is connected to the printer output unit 39 and prints data from the semiconductor simulation apparatus 1.

  Here, the input data 2, the process flow 3, and the model parameter 4 shown in FIG. 1 are given from the data 52 shown in FIG. 15 or the keyboard 36 and stored in the data group 43. A program that defines the operations of the process simulator 21 and the device simulator 22 shown in FIG. 1 is given from the program 51 shown in FIG. 15 and stored in the program group 42. Programs that define the operations of the input unit 11, the calibration unit 13, and the output unit 14 illustrated in FIG. 1 are stored in the program group 42 illustrated in FIG. The shape / impurity distribution 23 shown in FIG. 1 is stored in the data group 43 shown in FIG. The CV characteristic 5 shown in FIG. 1 is displayed as a graph or numerical data on the monitor 35 shown in FIG.

  As described above, in the first embodiment, the gate-drain capacitance Cgd when the source-drain voltage of the MOS transistor is not 0 V is calculated not by actual measurement but by high-precision simulation. Therefore, the gate-drain capacitance Cgd, which has been difficult to measure, can be calculated with high accuracy. As a result, the delay time of each circuit element of the LSI can be accurately estimated, so that mask rework can be avoided, the development cost of the LSI can be kept low, and the development period can be shortened.

Embodiment 2. FIG.
FIG. 16 is a block diagram showing a schematic configuration of a semiconductor simulation apparatus 61 according to the second embodiment of the present invention, which is compared with FIG. Referring to the semiconductor simulation apparatus 61 in FIG. 16, the difference from the semiconductor simulation apparatus 1 in FIG. 1 is that the output unit 14 is replaced with an output unit 62. In FIG. 16, portions corresponding to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The output unit 62 outputs the CV characteristic 5 calculated by the device simulator 22 to the outside and extracts the SPICE parameter 63 from the simulation result of the device simulator 22.

  FIG. 17 is a block diagram showing a configuration of the SPICE parameter extraction unit 71 included in the output unit 62 shown in FIG. Referring to FIG. 17, SPICE parameter extraction unit 71 calculates SPICE parameters from the CV characteristics (Cgd-Vgs characteristics) and IV characteristics (Ids-Vgs characteristics, Ids-Vds characteristics) calculated by device simulator 22. To extract. Here, the SPICE parameter is a parameter necessary for circuit simulation by the circuit simulator SPICE. The circuit simulator SPICE solves Kirchhoff's current law and voltage law at each node of the node network constituting the circuit, and calculates the temporal change in potential at each node. In circuit simulation, a model showing the behavior of a device in a circuit is required. As a model showing the behavior of a MOS transistor, for example, there is a BSIM (Berkley Short-channel IGFET Model). The circuit simulator SPICE calculates a delay time of each circuit element of the LSI by performing a circuit simulation using the SPICE parameter.

  Therefore, in the second embodiment, the gate-drain capacitance Cgd when the source-drain voltage of the MOS transistor is not 0 V can be calculated with high accuracy and the SPICE parameter can be extracted. As a result, the delay time of each circuit element of the LSI can be accurately estimated by using the circuit simulator SPICE, so that the re-creation of the mask can be avoided, the development cost of the LSI can be reduced, and the development period can be shortened. The

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a block diagram which shows schematic structure of the semiconductor simulation apparatus by Embodiment 1 of this invention. It is a conceptual diagram for demonstrating the gate-drain capacity | capacitance Cgd of a MOS transistor. It is a block diagram for demonstrating in detail the operation | movement of the simulation part shown in FIG. It is a figure which shows the shape and impurity distribution obtained by process simulation. It is a figure which shows the shape and impurity distribution obtained by process simulation. It is a figure which shows the mode of the mesh division | segmentation for discretizing and performing a simulation. It is a flowchart which shows the procedure in which the capacity | capacitance between gates and drains is calculated by the semiconductor simulation apparatus. It is a figure for demonstrating a mode that the donor density | concentration calculated by process simulation is calibrated by changing point defect parameter C ^* _I. It is a figure for demonstrating a mode that the Ids-Vgs characteristic (linear area | region) calculated by device simulation is calibrated by changing the mobility parameter (alpha). It is a figure for demonstrating a mode that the Ids-Vgs characteristic (saturation area | region) calculated by device simulation is calibrated by changing the mobility parameter (alpha). By changing the mobility parameter v _s, it is a diagram for explaining how the Ids-Vds characteristics calculated by device simulation is calibrated. Point defect parameter D _I, by changing the K _I, is a diagram for explaining how the Vth-Lg characteristics calculated by device simulation is calibrated. It is a figure which shows the Cgd-Vgs characteristic calculated by the device simulation with respect to the geometric dimension (gate length Lg) given as input data. It is a figure which shows the actual measurement result of the Cgd-Vgs characteristic by the conventional method. It is a figure which shows the hardware constitutions of the semiconductor simulation apparatus shown in FIG. It is a block diagram which shows schematic structure of the semiconductor simulation apparatus by Embodiment 2 of this invention. It is a block diagram which shows the structure of the output part shown in FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,61 Semiconductor simulation apparatus, 2 input data, 3 process flow, 4 model parameter, 5 CV characteristic, 11 input part, 12 simulation part, 13 calibration part, 14, 62 output part, 21 process simulator, 22 device simulator , 23 Shape / impurity distribution, 24, 25 Sub simulator, 31 CPU, 32 bus, 33 Magnetic storage device, 34 External device connection part, 35 Monitor, 36 Keyboard, 37 Mouse, 38 Communication part, 39 Printer output part, 41 OS , 42 program group, 43 data group, 51 program, 52 data, 53 optical disc drive, 54 printer, 63 SPICE parameter, 71 SPICE parameter extraction unit.

Claims (4)

A semiconductor simulation device for calculating a capacitance between a gate and a drain of a transistor,
A process simulator for calculating the impurity distribution of a transistor by executing a process simulation using a geometric dimension that defines the structure of the transistor, a process flow that defines a transistor manufacturing process, and a first parameter required for the simulation And a device simulation is performed using the impurity distribution calculated by the process simulator, a bias condition indicating a bias applied to the electrode of the transistor, and a second parameter necessary for the simulation, and the source and drain of the transistor A semiconductor simulation apparatus comprising a device simulator for calculating a capacitance between the gate and the drain when the voltage between is not zero. The device simulator includes a first sub-simulator that calculates electrical characteristic data of a transistor, and a second sub-simulator that calculates a capacitance between the gate and the drain,
The semiconductor simulation apparatus further calibrates the first parameter so that the impurity distribution calculated by the process simulator matches a first measured value given in advance within an allowable range, and the first parameter A calibration unit that calibrates the second parameter so that the electrical characteristic data calculated by the sub-simulator matches a second actual measurement value given in advance within an allowable range;
In the second sub-simulator, the first and second actual measurements in which the impurity distribution calculated by the process simulator and the electrical characteristic data calculated by the first sub-simulator are respectively given in advance. The semiconductor simulation apparatus according to claim 1, wherein a capacitance between the gate and the drain is calculated when the value matches within an allowable range. The electrical property data is
First characteristic data indicating a relationship between a current between the drain and the source of the transistor and a voltage between the gate and the source of the transistor;
Second characteristic data showing the relationship between the current between the drain and the source of the transistor and the voltage between the drain and the source of the transistor, and the relationship between the threshold voltage at which the transistor conducts and the gate length of the transistor The semiconductor simulation apparatus according to claim 2, comprising third characteristic data. A semiconductor simulation method for calculating a capacitance between a gate and a drain of a transistor,
A process simulation is executed using a geometric dimension that defines the structure of the transistor, a process flow that defines the transistor manufacturing process, and a first parameter necessary for the simulation, and a first impurity distribution is calculated. Steps,
A device simulation is executed using the impurity distribution calculated in the first step, a bias condition indicating a bias applied to the electrode of the transistor, and a second parameter necessary for the simulation, and the electrical characteristics of the transistor A second step of calculating data,
The first parameter is calibrated so that the impurity distribution calculated in the first step matches a first actual measurement value given in advance within an allowable range, and the first parameter calculated in the second step is calculated. A third step of calibrating the second parameter so that electrical characteristic data agrees with a second measured value given in advance within an allowable range; and the impurity distribution calculated by the first step; When the electrical characteristic data calculated in the second step agrees with the first and second measured values given in advance within an allowable range, the device simulation is executed to perform the transistor simulation. Including a fourth step of calculating a capacitance between the gate and drain when the voltage between the source and drain is not zero. Simulation method.

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