JP2005064164A - Method of extracting characteristic of mosfet - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that the overlap capacity and overlap length of MOSFET are extracted from the measured capacitance between a gate and a source/drain when the MOSFET is turned off, but the accurate overlap length cannot be derived because the measured capacitance includes an internal fringe capacitance, moreover a present transistor model lacks in performance, and therefore errors are increased in the gate capacitance simulation of a short channel device. <P>SOLUTION: An overlap capacitance parameter is previously derived within a gate voltage range in which the MOSFET is kept in an off-state, the simulation of overlap capacitance characteristics is run using the overlap capacitance parameter, and an overlap length is derived from the overlap capacitance value when the MOSFET is turned on, whereby a correlation between the overlap capacitance and the overlap length is obtained to improve gate capacitance simulation in accuracy. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for extracting an overlap capacitance parameter and an overlap length, which are important characteristics when performing a circuit simulation of a MISFET (metal-insulator-semiconductor field effect transistor) such as a MOSFET.

  In recent years, the miniaturization of the minimum dimension of a semiconductor element has progressed, and a design with a gate length dimension of 0.1 μm or less has begun to be studied. In the technical field of VLSI composed of such fine elements, each time you want to newly design and develop the above-mentioned semiconductor elements or change the manufacturing process such as impurity diffusion concentration, the semiconductor integrated circuit is actually prototyped. This increases the time required for development and increases the development cost. Therefore, instead of proceeding with designing an actual circuit as a prototype, work is being carried out using a series of computer simulations to advance the design.

  This series of simulations includes a process simulator for extracting process data such as impurity concentration, a device simulation for extracting electrical characteristics of a MOSFET as a semiconductor element, and a circuit simulation.

  Here, in the above circuit simulation, model parameters for a circuit analysis program called SPICE (Simulation Program with Integrated Circuit Emphasis) are extracted from the accurate MOSFET electrical characteristics obtained based on the above device parameters, The SPICE is activated using the SPICE parameters, and the memory operation, flip-flop operation, and the like are analyzed.

  If the results of these simulations deviate significantly from the actual measurement results, the circuit characteristics desired at the time of design cannot be obtained, and in the worst case, the design must be reworked. Therefore, as the simulation result matches the actual measurement result with higher accuracy, a desired VLSI can be developed in a shorter period of time. Therefore, development of a highly accurate simulation technique is strongly desired.

  For this purpose, the SPICE parameters are extracted from the elements that have been implemented in advance by the above-mentioned process simulation and device simulation so that the device model incorporated in the circuit simulation can reproduce the actual device characteristics, or from the prototype manufactured at the prototype stage. Must be done accurately.

  Among such SPICE parameters, a particularly important characteristic is, for example, the overlap length ΔL of the MOS transistor. Here, the overlap length ΔL is defined as the length of the region where the gate electrode of the MOS transistor and the source / drain diffusion layer region overlap. Here, the gate electrode is formed on the channel region of the MOS transistor and the overlap region via the gate insulating film. FIG. 10 is a diagram for explaining this conventional overlap length extraction method and shows the dependency of the channel resistance R on the gate length for each execution gate voltage Vge.

  The effective channel length Leff of the MOS transistor is the distance between the source-side PN junction and the drain-side PN junction on the surface of the silicon substrate as shown in the device cross-sectional schematic diagram of FIG. Therefore, if the overlap length ΔL is accurately obtained, the accurate execution channel length Leff can be obtained at the same time.

  As a conventional technique, the derivation of the overlap length ΔL is, for example, as described in (Patent Document 1), with respect to a plurality of MOS transistors having different gate lengths L, as shown in the following formula (1). For each execution gate voltage Vge, the channel resistance (resistance between the source electrode and the drain electrode) R given by the equation (2) when the drain voltage Vd of the MOS transistor is very small is measured (hereinafter referred to as “reduction voltage”). This is referred to as a first conventional example).

That is,
Vge = Vg−Vth (1)
Here, Vg is a gate voltage (gate-source voltage), and Vth is a threshold voltage. Also,
R = (ΔId / ΔVd) ⁻¹ Formula (2)
Here, Vd is a drain voltage (drain-source voltage), and Id is a drain current (drain-source current).

  FIG. 10 is a characteristic diagram showing the dependence of the channel length R on the gate length L for each effective gate voltage Vge, which is obtained when the overlap length ΔL is extracted in the first conventional example. Here, FIG. 10 shows nMOS transistor data, where the plot is a measurement point, and the straight line group is a regression line group for each effective gate voltage Vge1 to Vge5 obtained by a complementary operation by the least square method.

  A plurality of regression lines corresponding to the effective gate voltages Vge1 to Vge5 converge to approximately one point (a, b) as shown in FIG. A coordinate point a on the horizontal axis at the convergence point corresponds to the overlap length ΔL. The coordinate value b on the vertical axis corresponds to the parasitic resistance of the source / drain diffusion layer.

Further, there is a technique for obtaining the gate overlap length from the capacitance characteristics as in the second conventional example (Patent Document 2). FIG. 12 shows this extraction flow. This is because the gate-source / drain capacitance characteristics are measured from the measurement elements having different gate lengths as in the gate capacitance (Cg) -gate voltage (Vg) characteristics shown in FIG. The gate length dependency of the drain capacitance value is drawn as shown in FIG. 11, and the gate side fringe capacitance is obtained from the side surface of the gate electrode from the intercept of the vertical axis. Let Cx be the capacitance value at the point Vg = Vx at which the point begins to have an overlap capacitance. This Vx is also obtained as a point where a steep change appears by differentiating the gate-source / drain capacitance characteristics by the gate voltage to obtain the characteristics as shown in FIG. Then, the overlap length ΔL is calculated from the point where the capacitance value in FIG. 11 becomes Cx.
JP-A-7-176740 (pages 8-9, FIG. 4, FIG. 5) JP 2001-338986 A (pages 11-12, FIG. 4, FIG. 6)

As described above, with the recent miniaturization and higher density of VLSI, the MOS transistor structure used tends to have a shorter gate length.
However, in the method of deriving the overlap length ΔL as in the first conventional example, when the gate length is shortened, the linearity of the channel resistance R dependency on the gate length L is lost, and the regression line group does not converge to one point. For this reason, it is difficult to uniquely determine the overlap length ΔL. This is because a two-dimensional effect (two-dimensional distribution of current density) that is one of the short channel effects of the MOS transistor cannot be ignored.

  In the second conventional example, since the overlap length is derived under the voltage condition in which the inner fringe capacitance CF_in as shown in FIG. 8 exists, an overlap length larger than the structural overlap length is derived, When a capacity simulation is performed with the transistor model BSIM3 and the transistor model BSIM4 that are currently most popular using the overlap length, a simulation error increases in a low threshold MOS transistor.

  As shown in FIG. 8, the inner fringe capacitance CF_in is one of the parasitic capacitances between the gate, the source and the drain. The capacitance when viewed from the gate through the PN junction and oxide film from the source or drain. The fringe capacitance from the side surface of the gate electrode to the source or drain is defined as the outer fringe capacitance CF_side. From the analysis by the device simulator, it was found that in the Nch transistor, the inner fringe capacitance exists when the surface of the P-type substrate is depleted, and disappears because the channel is shielded by the channel when it is formed on the substrate surface. . When the MOSFET is in a saturated state and a channel is formed, the overlap capacitance takes a capacitance value corresponding to the overlap length of the oxide film capacitance as shown in the following formula (4), and the gate-source-drain capacitance Cds_g was found to be the sum of the gate length of the gate oxide film capacitance and the fringe capacitance from the side surface of the gate electrode as shown in the following equation (5).

Cov (Vgs = V1) = εox · W · ΔL / Tox (4)
Cds_g (Vgs = V1) = εox · W · L / Tox + 2 · CF_side (5)
Similarly, in the case of the Pch transistor, the same phenomenon occurs only by switching between the P-type and the N-type. The reason why the fringe capacitance CF_side is doubled in the equation (5) is because both the source side and the drain side are considered.

  Currently, BSIM3 and BSIM4, which are the most popular transistor models, do not consider the inner fringe capacity in the overlap capacity model formula, and the oxide film thickness and overlap length are not included in the formula. There are cases in which equations (4) and (5) do not hold in the state (Non-Patent Document BSIM3v3, Manual, 1995 p4-18 to 4-20 UC Berkeley).

  In other words, even if the overlap capacity parameter is extracted from the Cds_g characteristic and an accurate overlap length is inserted, there is no correlation between the overlap length and the overlap capacity. This is not satisfied, and in particular, the accuracy of MOS gate capacitance simulation is reduced in a fine device.

  The overlap length extracted in the second conventional example is several nanometers longer than the structural overlap length by the amount of the inner fringe capacity, and an accurate overlap length cannot be derived. As a result, the decrease in the MOS gate capacitance in the effective channel length portion of the simulation represents the disappearance effect of the inner fringe capacitance at the time of channel formation, so that Vx is in the range of 0 volts or more. For example, the simulation accuracy of the gate capacitance in the strong inversion state was avoided. This is because, as shown in FIG. 6, the current overlap capacitance model characteristic has a characteristic of increasing until saturation as the gate voltage increases, and is almost saturated when Vg is 0 volts or more. It is. That is, the error δCov occurs when the overlap capacitance model characteristic used at the bias point from which the overlap length is extracted is not saturated.

  However, in recent years, the threshold of MOS transistors has been lowered, and there are devices in which Vx is 0 volts or less. When the second conventional example is applied to a MOS transistor having Vx of 0 volts or less, an overlap capacitance model is obtained. The overlap length is estimated in the region where the characteristics are not saturated, and the simulation overlap capacity is larger than the overlap capacity calculated by multiplying the overlap length by the oxide film capacity in the strong inversion state. The difference was an error.

  There is an urgent need to provide a method for extracting an overlap capacity parameter and an overlap length that enable highly accurate capacity simulation even in a micro device having a low threshold.

  Provided is a method for extracting characteristics of an overlap capacitance parameter and an overlap length MOSFET that can accurately simulate a capacitance characteristic when a transistor is on and an overlap capacitance characteristic when the transistor is off.

Conventionally, the overlap length has been calculated from the voltage characteristics where the overlap capacitance is the main component, based on the measured characteristics of the drain / source-gate capacitance.
In the present invention, from the measured characteristics of the drain-source-gate capacitance characteristics, the overlap capacitance model parameter is extracted in the gate voltage range in which the channel is not formed in the MOS transistor and the MOSFET is off, and the extracted model Overlap capacitance characteristics are simulated using parameters, and the voltage condition under which the channel is formed, that is, the value obtained by subtracting the gate electrode side fringe capacitance from the simulated overlap capacitance value at Vg = V1, is divided by the gate oxide film capacitance. The overlap length is derived. In this way, it is possible to achieve consistency between the overlap capacity model value and the overlap length in the saturated state, and as a result, the overlap length is obtained from the structure by the amount that cancels out the effects of the inner fringe capacity disappearance and the model error. It will take a value that is different from the value obtained.

  The gate voltage range in which the MOSFET is turned off is a voltage range in which the channel of the MOS transistor is not formed, takes the differential characteristics of the drain-source-gate capacitance characteristics, and the voltage until just before a steep change appears. Value. This voltage boundary condition is the same as Vx in FIG. 5 of (Patent Document 1).

  The gate electrode side fringe capacitance can be obtained by reproducing and simulating the cross-sectional structure of the MOSFET on a TCAD (Technology Computer Aided Design) or a capacitance simulator. First, when the mesh near the side surface of the gate electrode is increased, the gate electrode is divided at the electrode ends as shown in FIG. 9A, and the divided electrode 105 is named a dummy gate. Is obtained, the sum of the side fringe capacitance CF_side and the capacitance CF_ox via the oxide film is obtained. From this, in order to remove the capacitive component CF_ox via the oxide film, a structure in which the divided electrode lengths are cut out is created on the simulator as shown in FIG. By analyzing the capacitance CF_ox and removing CF_ox from the analysis value of FIG. 9A, the side fringe capacitance CF_side can be obtained.

  The gate oxide film capacitance is in the same wafer as the overlap capacitance measuring element, and the Cds_g characteristics of MOSFETs having the same gate width and different gate lengths are measured as shown in FIG. When the capacitance values when the gate voltage is V1 are CL1 and CL2, the gate oxide film capacitance per unit gate width is expressed by the following equation (6). By making the gate width W equal and taking the difference in capacitance between the gate and source / drain of MOSFETs that differ only in gate length L, the overlap capacitance component and the outer fringe capacitance component can be removed, and the gate oxide film around the unit gate length A capacitive component can be obtained.

Cox = (CL2-CL1) / (L2-L1) (6)
Alternatively, the gate oxide film capacitance may be a capacitance per unit area at Vg = V1 obtained from the Cds_g measurement characteristic of the large area MOS transistor. This is because if the gate length and gate width of the MOSFET are increased, the ratio of the overlap length and overlap width to the whole is reduced, and the main component of the capacitance is the oxide film capacitance. Note that the gate oxide film thickness estimated from the capacitance value is thicker than the gate oxide film thickness obtained from the optical measurement, because the gate electrode is depleted and the inversion layer has a finite thickness.

  When the MOSFET is in a saturated state by analysis by TCAD, the gate capacitance Cds_g of the MOSFET can be regarded as the sum of the gate length of the oxide film capacitance value and the gate electrode side surface fringe capacitance. The capacity simulation value matches the actual measurement value. That is, the simulation accuracy of the MOS gate capacitance can be ensured by deriving the overlap length so that the overlap capacitance simulation value at the time of strong inversion corresponds to the overlap length of the oxide film capacitance. Even if the overlap length derived by the above method takes a value different from the overlap length obtained from the structure, the capacitance at saturation is the sum of the gate length of the oxide film capacitance and the fringe capacitance on the side surface of the gate electrode. Therefore, the measured capacity value is the same value.

Such an overlap length ΔL is obtained from the following equation (7).
ΔL = (Cov_model1−CF_side) / Cox (7)
Cov_model1 in the above equation (7) is obtained by SPICE simulation using an overlap capacitance parameter extracted from a gate voltage range in which no channel is formed in the transistor as shown in FIG. 6, when Vg = V1. It is an overlap capacity model characteristic value. At this time, when simulating the overlap capacitance model characteristics, if the overlap capacitance model is independent of the MOS capacitance model of the effective channel length portion, the MOS gate capacitance component of the effective channel length portion corresponds to the oxide film thickness. In the BSIM3 parameter, only overlap capacitance simulation characteristics can be obtained by substituting a large value such as 1 m for Tox and performing SPICE simulation.

  In other words, this overlap length extraction method does not consider the inner fringe capacity and does not use the overlap capacity model in which the overlap length and the overlap capacity are not correlated, unlike the transistor model BSIM3 or BSIM4. This is a technology that can ensure the MOS gate capacitance simulation accuracy.

  As described above, according to the present invention, the overlap capacitance and the overlap length in the state where the MOSFET is turned on are matched, and in the voltage range in which the MOS transistor operates, it is possible to ensure a high-accuracy gate capacitance simulation accuracy. More accurate circuit simulation becomes possible.

Even in a short channel device, it is possible to extract the overlap capacitance and the overlap length that can simulate the gate capacitance including the overlap capacitance with high accuracy.
As described above, the present invention facilitates the realization of a semiconductor device that is miniaturized, highly integrated, or multi-functional, and can contribute to the promotion of the realization of a high-performance semiconductor device.

(Embodiment 1)
(Embodiment 1) of the present invention will be described with reference to the drawings.
FIG. 2 shows the configuration of the MOSFET overlap length extraction device of the present invention, and FIG. 3 shows the configuration of the capacitance measuring device constituting the extraction device.

  A major feature of the present invention is that the overlap capacitance parameter is extracted using a transistor model in a gate voltage range where a channel is not formed in the transistor from the gate voltage dependence of the gate-source / drain capacitance characteristics, and the above extraction is performed. Perform SPICE simulation by using the existing parameters and transistor model to obtain overlap capacitance model characteristics, and divide the value obtained by subtracting the fringe capacitance from the overlap capacitance model value when the gate voltage is the power supply voltage by the oxide film capacitance The overlap length is calculated by

  In order to embody the present invention, as shown in FIG. 2, an overlap length calculation device of this example includes a capacitance measuring device 2 that measures the gate-source-drain capacitance described above for a device group 1 to be measured, An input device 3 such as a keyboard and a mouse; a data processing device 5 such as a CPU that operates under the control of various processing programs written in the recording medium 4; a storage device 6 that temporarily stores measurement data, calculation data, and the like; An output device 7 such as a display or a printer is schematically configured.

  As shown in FIG. 3, the capacitance measuring device 2 controls the gate-source for each measurement target element of the measured element group 1 under the control of the element mounting portion 21 for mounting the measured element group 1 and the data processing device 5. -It is comprised from the measurement part 22 for measuring the electric current and voltage between drains.

  The element mounting portion 21 has mounting terminals that are electrically connected to the gate 1g, the source 1s, the drain 1d, and the semiconductor substrate 1b. These mounting terminals are used when a probe is placed on the device group 1 to be measured in a wafer state. Consists of a prober, and when the device group 1 to be measured is incorporated in a package, it consists of a socket for mounting the package. A gate insulating film 1ox exists between the gate 1g and the substrate 1b.

  The measurement unit 22 includes a variable DC bias voltage source 221 for applying a DC bias voltage to each gate 1g, a voltmeter 223 for measuring an applied voltage between the gate 1g-source 1s and the drain 1d, And an ammeter 224 for measuring a current flowing from the gate 1g to the source 1s and the drain 1d.

  In this example, the DC bias voltage source 221 and the AC voltage source 222 are connected in series with each other, one output end of which is connected to the element mounting terminal, and the other output end is grounded. Here, the substrate mounting terminal of the element mounting portion 21 is grounded, and the source mounting terminal and the drain mounting terminal are grounded via the ammeter 224. A voltmeter 223 is connected between the gate mounting terminal and the source / drain mounting terminal. In this way, each measuring element is electrically connected to the measuring section 22 via the element mounting section 21.

  The recording medium 4 also includes a capacity measurement program 4a, a capacity curve calculation program 4b, a capacity characteristic differential calculation program 4c, an overlap capacity parameter extraction program 4d, an overlap, and the like for realizing various processing functions in the data processing device 5. A capacity characteristic display program 4e, a gate oxide film thickness calculation program 4f, a fringe capacity calculation program 4g, and an overlap length calculation program 4h are stored.

  The capacity measurement program 4a controls the capacity measurement device 2 to sequentially change the gate voltage Vg, and performs a procedure for performing current / voltage measurement necessary for calculating the gate-source-drain capacity Cg for each gate voltage. The processing device 5 is executed.

  The capacitance measurement program 4b obtains the gate voltage Vg dependency of the gate-source-drain capacitance Cg for each measurement target element based on the measurement result of the capacitance measurement device 2, and the Cg-Vg characteristic as shown in FIG. Is derived by the data processing device 5.

  The capacity characteristic differential calculation program 4c causes the data processing device 5 to execute a process of calculating a differential value based on the gate voltage of Cg at the gate bias voltage in a region where a channel starts to be formed in each measurement target element. Obtaining such characteristics, a gate voltage Vg = Vx at which a MOSFET channel starts to be formed is obtained.

  The overlap capacitance parameter extraction program 4d is a parameter extraction process related to overlap capacitance by combining simulation characteristics with the gate length dependency of Cg under a gate bias condition in which a channel region is not formed in the measurement target element. I do. In the case of using the transistor model BSIM3 or the transistor model BSIM4, extraction is performed by using the parameters CGSO, CGDO, CGSL, CGDL, CGBO, CKAPPA, CF and combining the simulation characteristics with the measured characteristics using the least square method. .

  The overlap capacity characteristic display program 4e performs SPICE simulation using the parameters extracted by the overlap capacity parameter extraction program 4d to display the overlap capacity model characteristics as shown in FIG. 6 on the display.

  Based on the Cds_g characteristics of the MOSFETs having different gate lengths obtained by the capacitance measurement program 4b, the gate oxide film capacitance calculation program 4f is overlapped if the capacitance values when the gate voltage to be saturated is V1 are CL1 and CL2. The gate oxide film capacity per unit gate width corresponding to the gate width of the long extraction element is calculated from the above equation (6).

Cox = (CL2-CL1) / (L2-L1) (6)
The fringe capacity calculation program 4g reproduces the L-direction cross-sectional structure of the MOSFET on the device simulator, increases the mesh near the side surface of the gate electrode, divides the gate electrode at the electrode end as shown in FIG. If the electrode 105 is a dummy gate, the capacitance between the dummy gate and the source is analyzed, and the sum of the side fringe capacitance CF_side and the capacitance CF_ox via the oxide film is calculated. Further, in order to remove the capacitive component CF_ox via the oxide film, a structure obtained by cutting out the divided electrode length L_flinge is created on a TCAD (Technology Computer Aided Design) simulator as shown in FIG. The side-side fringe capacitance CF_side is calculated by analyzing the capacitance CF_ox between the dummy gate and the source in the structure and removing CF_ox from the analysis value of FIG.

  Then, the overlap length calculation program 4h reads the capacitance value Cov_model1 under the voltage condition of Vg = V1 from the overlap capacitance model characteristic obtained by the overlap capacitance characteristic display program 4e, and from this value, the fringe capacitance calculation program 4g The overlap length obtained by subtracting the fringe capacitance CF_side obtained in the above step is divided by the oxide film capacitance Cox around the unit gate length obtained by the gate oxide capacitance calculation program 4f. Is extracted.

ΔL = (Cov_model−CF_side) / Cox (7)
The recording medium 4 may be a magnetic memory such as a magnetic disk or a magnetic tape, a semiconductor memory such as a ROM or a RAM, a magneto-optical memory such as a CR-ROM, an optical memory, or another recording medium.

  The above-described apparatus can be realized by combining TCAD software with measurement extraction software such as ICCAP of Agilent Technologies, UTMOST of Silvaco Japan.

Next, a procedure for extracting the overlap length ΔL, which is a feature of the present invention, will be described with reference to the flowchart of FIG.
First, an element group to be subjected to device parameter extraction is prepared and attached to the element attaching portion 21 of the capacitance measuring apparatus 2. This attachment is as shown in FIG.

  Thus, the DC bias power source 221 and the AC voltage source 222 are connected to the gate 1g, and the source terminal and the drain terminal are grounded via the ammeter 224. Since the voltmeter 223 is connected between the gate mounting terminal, the source mounting terminal, and the drain mounting terminal, the applied voltage between the gate, the source, and the drain can be measured.

  When an instruction to start measurement is given from the input device 3 in this state, the capacity measurement control program 4a is read from the recording medium 4 to the data processing device 5 to control the operation of the data processing device 5. The data processing device 5 executes a MISFET capacitance measurement process (step 1) under the control of the capacitance measurement program 4a.

  In (Step 1), the data processing device 5 applies the gate voltage Vg to the gate 1g of the MOS transistor by the variable DC bias voltage source 221 and further applies an AC voltage having an amplitude of 100 mV from 10 kHz to 100 kHz by the AC voltage source 222. In addition, an alternating current value is measured with an ammeter 224 and converted into a capacitance value. In this way, the gate-source-drain capacitance Cg at a predetermined gate voltage Vg is measured. The capacitance measurement is performed while sequentially switching a plurality of measurement target n-channel elements. At this time, it is assumed that the elements to be measured are created on the same process and on the same wafer, the gate width is the same at 10 μm, and the gate length is two or more in the range of several μm from the minimum dimension of the process used. Keep it. A large-area nMOS transistor (gate length 100 μm, gate width 100 μm) is also prepared.

  In the measurement of Cg, if the pad capacity and the wiring capacity cannot be ignored, a pattern capable of measuring the pad capacity and the wiring capacity is made in advance and measured. Next, the measured values of the pad capacitance and the wiring capacitance are subtracted from the calculated Cg.

  Next, in (Step 2), the gate voltage (Vg) dependency of the gate capacitance (Cg) is calculated from the capacitance value obtained by the capacitance measurement process. In this way, the capacitance Cg-gate voltage Vg curve is derived. An example of this curve is shown in FIG. In FIG. 4, the horizontal axis represents the gate voltage Vg, and the vertical axis represents the capacitance Cg.

  As shown in FIG. 4, when the gate voltage Vg increases, Cg increases in a characteristic pattern. This will be briefly described. When the gate voltage Vg is less than or equal to the threshold value of the nMOS transistor, the MOS transistor is in an off state, and the charge in the channel region of the MOS transistor does not respond to the AC voltage. For this reason, Cg is a small value. When the gate voltage increases and exceeds the threshold value, an inversion layer is formed in the channel region, and Cg increases. When the substrate surface under the gate insulating film is completely inverted and a sufficient electron carrier layer is formed, the Cg value becomes saturated. A predetermined Vg in this saturation region, that is, the Cg value of the MOSFET at V1 shown in FIG.

  Next, in (Step 3), a characteristic obtained by differentiating the Cg characteristic with respect to the gate voltage, that is, FIG. 5 is drawn, and a point where the differential characteristic rises sharply with an increase in the gate voltage is defined as Vx. In the voltage range in which no channel is formed. Note that Vx is the same as Vx in FIG. 5 of (Patent Document 2).

  Next, in (Step 4), SPICE parameter extraction is performed by using the transistor model BSIM3 or BSIM4 in the voltage range of Vg ≦ Vx with respect to the capacitance Cg−Vg characteristic, and combining the SPICE simulation capacitance characteristic. .

  Next, in (Step 5), SPICE simulation is performed using the overlap capacitance model parameter obtained in (Step 4), thereby obtaining an overlap capacitance model characteristic. At this time, in order to display only the overlap capacitance characteristic, the simulation is performed by excluding the MOS capacitance of the effective channel length portion. Specifically, in the transistor models BSIM3 and BSIM4, the formulas of the MOS capacitance and the overlap capacitance of the effective channel length portion are independent, and a large value such as 1 m is substituted for the parameter corresponding to the gate oxide film thickness. It can be obtained by simulation. Here, an overlap capacitance model value of Vg = V1 in which the MOSFET is saturated is referred to as Cov_model1.

  Next, in (Step 6), the gate oxide film capacitance per unit gate length is derived from the gate-source / drain capacitance values CL1 and CL2 of the MOSFETs whose gate lengths are different from L1 and L2 using Equation (6).

  Next, in (Step 7), the cross section of the nMOS • Tr is measured with a TEM, SEM, or the like, and the fringe capacitance is analyzed from the obtained gate cross-sectional structure using a device simulator or the like. Specifically, as shown in FIG. 13, the fringe capacitance can be obtained by arranging a fringe capacitance deriving electrode near the side surface of the gate electrode and performing device simulation.

  In (Step 8), the value obtained by subtracting the fringe capacity CF_side obtained in (Step 7) from the overlap-on capacity Cov_model1 of the model obtained in (Step 5) is the unit gate length obtained in (Step 6). ΔL is calculated by dividing by the oxide film capacitance Cox.

In this embodiment, even when the MOS transistor is miniaturized, it is possible to easily extract the overlap length ΔL that enables accurate capacitance simulation.
(Embodiment 2)
Of the above (Embodiment 1), converting the oxide film capacitance per unit gate length in (Step 6) from the capacitance value of Vg = V1 of the gate-source / drain capacitance measurement characteristics of the large-area MOSFET. It is a feature.

  Since the oxide film capacitance around the unit gate length around the same gate width as that of the overlap length extraction element is used in the subsequent calculation, if the gate width of the overlap length extraction element is W_cov, Cox = CL / W / L · W_cov Calculate as The subsequent form is the same as that of (Embodiment 1).

  In each of the above embodiments, a CAD that performs analog simulation generally called a SPICE simulator is used as a circuit simulator. However, the product name is HSPICE (US SYNOPSYS (US)) and the product name is SmartSpice (US). SILVACO (Silvaco)) can be used in the same manner. The product name: Eldo (Mentor Graphics, USA) can also be used as the circuit simulator.

  The MOSFET characteristic extraction method of the present invention is useful for realizing high-accuracy capacitance simulation of various fine devices having a low threshold value.

The flowchart which showed the procedure of overlap length extraction of this invention Configuration diagram of MOSFET characteristic extraction apparatus according to an embodiment of the present invention Configuration diagram of the capacity measuring apparatus of the embodiment The graph which showed the gate capacity (Cg) -gate voltage (Vg) characteristic used for this invention Graph when Cg is differentiated once by Vg with the above Cg-Vg characteristics The figure which showed the example which displayed the gate voltage dependence of the overlap capacity model characteristic which is the feature of the present invention Device sectional view for explaining overlap length ΔL The figure which showed the capacity | capacitance component accompanying a gate-source in the state in which the channel is not formed. The figure which showed the TCAD analysis example which calculates | requires the gate electrode side surface fringe capacity | capacitance in this invention FIG. 6 is a diagram for explaining the overlap length extraction method of the first conventional example, showing the gate length dependence of the channel resistance R for each execution gate voltage Vge; The figure for demonstrating the overlap length extraction method of the 2nd prior art example, and the figure which showed the gate length dependence of Cg gate capacity Overlap length extraction flow diagram of the second conventional example

Explanation of symbols

1 Device group to be measured 1g Gate 1ox Gate oxide film 1s Source (diffusion layer region)
1d drain (diffusion layer region)
1b Substrate (semiconductor substrate)
DESCRIPTION OF SYMBOLS 2 Capacity measuring device 21 Element attachment part 22 Measuring part 221 DC bias voltage source 222 AC voltage source 223 Voltmeter 224 Ammeter 4 Recording medium 4a Capacity measurement program 4b Capacity curve calculation program 4c Capacity characteristic differential calculation program 4d Overlap capacity parameter extraction Program 4e Overlap capacitance model characteristic display program 4f Gate oxide film capacitance calculation program 4g Fringe capacitance calculation program 4h Overlap length calculation program

Claims (7)

Measure the capacitance characteristics between MOSFET gate-source-drain,
Overlapping capacitance parameters are extracted as model parameters by combining the simulation characteristics with the measured characteristics using the transistor model and circuit simulator in the gate voltage range where the MOSFET channel is not formed,
Using the above model parameters, the gate voltage dependence of the overlap capacitance model characteristics is obtained, and the overlap length is extracted by dividing the value obtained by subtracting the fringe capacitance from the overlap capacitance model characteristic value in the saturated state by the oxide film capacitance value. MOSFET characteristic extraction method. 2. The MOSFET according to claim 1, wherein when the gate voltage dependence of the overlap capacitance model characteristic is obtained by circuit simulation, only the overlap capacitance is displayed excluding the MOS gate capacitance of the execution channel length portion. Characteristic extraction method. The fringe capacitance is reproduced on the TCAD or capacitance simulator of the cross-sectional structure of the MOSFET, the gate electrode is divided at the electrode end by increasing the mesh near the gate electrode side surface, and the gate electrode side surface fringe capacitance is obtained using the divided electrodes. The MOSFET characteristic extraction method according to claim 1, wherein: The capacitance of the oxide film is measured on the capacitance value between the gate and source / drain of two MOSFETs formed on the same wafer as the overlap capacitance measuring element and having the same gate width and different gate length. 2. The MOSFET characteristic extraction method according to claim 1, wherein the oxide film capacitance per unit gate length is obtained by dividing the difference by the gate length difference. Alternatively, the capacitance per unit area is calculated as the gate oxide film capacitance from the capacitance value between the gate, source and drain of the large area MOSFET formed on the same wafer as the overlap capacitance measuring element. The MOSFET characteristic extraction method according to claim 1, wherein: Means for measuring the capacitance between the MOSFET gate-source and drain;
Means for extracting an overlap capacitance as a model parameter in a gate voltage range in which a MOSFET channel is not formed;
Means for circuit simulation of overlap capacitance characteristics using the model parameters;
Means for deriving an oxide film capacitance value from the capacitance characteristics of MOSFETs having different gate lengths;
Means for deriving the fringe capacitance of the side surface of the gate electrode from the device cross-sectional structure by TCAD simulation;
A MOSFET characteristic extraction device comprising: means for deriving an overlap length by dividing a value obtained by subtracting a fringe capacitance value from an overlap capacitance simulation value under a condition of a power supply voltage to be used by an oxide film capacitance.   A recording medium on which a program necessary for executing the MOSFET characteristic extraction method according to claim 1 using a data processor is recorded.

Images