CN112867998A - 运算加速器、交换器、任务调度方法及处理系统 - Google Patents

运算加速器、交换器、任务调度方法及处理系统 Download PDF

Info

Publication number
CN112867998A
CN112867998A CN201880098081.XA CN201880098081A CN112867998A CN 112867998 A CN112867998 A CN 112867998A CN 201880098081 A CN201880098081 A CN 201880098081A CN 112867998 A CN112867998 A CN 112867998A
Authority
CN
China
Prior art keywords
pcie
data
address
accelerator
subtask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201880098081.XA
Other languages
English (en)
Inventor
程传宁
彭胜勇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Publication of CN112867998A publication Critical patent/CN112867998A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4027Coupling between buses using bus bridges
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026PCI express

Abstract

一种运算加速器、交换器及处理系统,该运算加速器包括:与第一外设部件互连标准PCIe设备直接通过PCIe链路连接的分流电路;所述分流电路,用于接收所述第一PCIe设备通过PCIe链路发送的第一数据,并通过内部总线传输所述第一数据,所述第一数据携带的第一地址位于第一区间。由于第一PCIe设备通过加速运算器内部的分流电路与该加速运算器直接进行通信,因此可以减轻PCIe链路的传输负担,进而避免PCIe链路产生的流量阻塞。

Description

PCT国内申请,说明书已公开。

Claims (27)

  1. PCT国内申请,权利要求书已公开。
CN201880098081.XA 2018-09-30 2018-09-30 运算加速器、交换器、任务调度方法及处理系统 Pending CN112867998A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2018/109214 WO2020062305A1 (zh) 2018-09-30 2018-09-30 运算加速器、交换器、任务调度方法及处理系统

Publications (1)

Publication Number Publication Date
CN112867998A true CN112867998A (zh) 2021-05-28

Family

ID=69951029

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201880098081.XA Pending CN112867998A (zh) 2018-09-30 2018-09-30 运算加速器、交换器、任务调度方法及处理系统

Country Status (4)

Country Link
US (1) US11403250B2 (zh)
EP (1) EP3851970A4 (zh)
CN (1) CN112867998A (zh)
WO (1) WO2020062305A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113238838B (zh) * 2021-04-22 2023-01-24 中国银联股份有限公司 一种任务调度方法、装置及计算机可读存储介质
CN113609056B (zh) * 2021-06-25 2023-08-25 曙光信息产业(北京)有限公司 数据传输测试方法、装置、设备以及存储介质
CN117076140B (zh) * 2023-10-17 2024-01-23 浪潮(北京)电子信息产业有限公司 一种分布式计算方法、装置、设备、系统及可读存储介质

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050273590A1 (en) * 2004-06-04 2005-12-08 Asustek Computer Inc. Multiple over-clocking main board and control method thereof
CN101046724A (zh) * 2006-05-10 2007-10-03 华为技术有限公司 磁盘接口处理器以及磁盘操作命令的处理方法
US20120254587A1 (en) * 2011-03-31 2012-10-04 International Business Machines Corporation Accelerator engine commands submission over an interconnect link
US20120284446A1 (en) * 2011-05-05 2012-11-08 International Business Machines Corporation Accelerator engine emulation over an interconnect link
CN103714039A (zh) * 2013-12-25 2014-04-09 中国人民解放军国防科学技术大学 通用计算数字信号处理器
US20140333634A1 (en) * 2013-05-10 2014-11-13 Yoshimichi Kanda Image processing apparatus and image processing method
CN104391820A (zh) * 2014-11-25 2015-03-04 清华大学 基于fpga的通用浮点矩阵处理器硬件结构
CN108536642A (zh) * 2018-06-13 2018-09-14 北京比特大陆科技有限公司 大数据运算加速系统和芯片

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8161209B2 (en) * 2008-03-31 2012-04-17 Advanced Micro Devices, Inc. Peer-to-peer special purpose processor architecture and method
CN103631671B (zh) * 2013-11-19 2016-05-04 无锡众志和达数据计算股份有限公司 一种ssd存储器的数据保护方法及控制器
US9684614B2 (en) * 2014-01-27 2017-06-20 Signalchip Innovations Private Limited System and method to convert lock-free algorithms to wait-free using a hardware accelerator
CN104102579B (zh) * 2014-06-30 2017-07-28 重庆邮电大学 一种基于多核或众核嵌入式处理器的网络测量系统及方法
US10802995B2 (en) * 2018-07-26 2020-10-13 Xilinx, Inc. Unified address space for multiple hardware accelerators using dedicated low latency links
US11079958B2 (en) * 2019-04-12 2021-08-03 Intel Corporation Apparatus, system and method for offloading data transfer operations between source and destination storage devices to a hardware accelerator
US11231868B2 (en) * 2020-04-07 2022-01-25 Eidetic Communications Inc. System and method for performing computational storage utilizing a hardware accelerator

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050273590A1 (en) * 2004-06-04 2005-12-08 Asustek Computer Inc. Multiple over-clocking main board and control method thereof
CN101046724A (zh) * 2006-05-10 2007-10-03 华为技术有限公司 磁盘接口处理器以及磁盘操作命令的处理方法
US20120254587A1 (en) * 2011-03-31 2012-10-04 International Business Machines Corporation Accelerator engine commands submission over an interconnect link
US20120284446A1 (en) * 2011-05-05 2012-11-08 International Business Machines Corporation Accelerator engine emulation over an interconnect link
US20140333634A1 (en) * 2013-05-10 2014-11-13 Yoshimichi Kanda Image processing apparatus and image processing method
CN103714039A (zh) * 2013-12-25 2014-04-09 中国人民解放军国防科学技术大学 通用计算数字信号处理器
CN104391820A (zh) * 2014-11-25 2015-03-04 清华大学 基于fpga的通用浮点矩阵处理器硬件结构
CN108536642A (zh) * 2018-06-13 2018-09-14 北京比特大陆科技有限公司 大数据运算加速系统和芯片

Also Published As

Publication number Publication date
US11403250B2 (en) 2022-08-02
WO2020062305A1 (zh) 2020-04-02
US20210216489A1 (en) 2021-07-15
EP3851970A1 (en) 2021-07-21
EP3851970A4 (en) 2021-10-27

Similar Documents

Publication Publication Date Title
US10324873B2 (en) Hardware accelerated communications over a chip-to-chip interface
US11403250B2 (en) Operation accelerator, switch, task scheduling method, and processing system
EP3798835A1 (en) Method, device, and system for implementing hardware acceleration processing
RU2597556C2 (ru) Структура компьютерного кластера для выполнения вычислительных задач и способ функционирования указанного кластера
US7643477B2 (en) Buffering data packets according to multiple flow control schemes
CN102135950B (zh) 基于星型互联架构的片上异构多核系统及其通信方法
US10206175B2 (en) Communications fabric with split paths for control and data packets
US20090307408A1 (en) Peer-to-Peer Embedded System Communication Method and Apparatus
US20100049892A1 (en) Method of routing an interrupt signal directly to a virtual processing unit in a system with one or more physical processing units
CN110347635A (zh) 一种基于多层总线的异构多核微处理器
US20180137082A1 (en) Single-chip multi-processor communication
US7564860B2 (en) Apparatus and method for workflow-based routing in a distributed architecture router
WO2023123902A1 (zh) 芯片系统中的数据传输处理方法及相关装置
JP5477112B2 (ja) ネットワークシステムの試験方法
TW200407712A (en) Configurable multi-port multi-protocol network interface to support packet processing
US20160217094A1 (en) Input/output control device, input/output control system, and input/output control method
JP2009282917A (ja) サーバ間通信機構及びコンピュータシステム
Abdallah et al. I/O contention aware mapping of multi-criticalities real-time applications over many-core architectures
US20230208776A1 (en) On chip router
US20220245009A1 (en) Application data flow graph execution using network-on-chip overlay
JP6928280B2 (ja) 情報処理システム
JP7146075B2 (ja) 複数のプロセッサ装置と複数のインターフェースを有するデータ処理装置
CN110413562B (zh) 一种具有自适应功能的同步系统和方法
KR20210006127A (ko) 다중 프로세서 인터럽트 신호 처리 장치
US9678905B2 (en) Bus controller, bus control system and network interface

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination