CN112864032A - Spliced screen and manufacturing method - Google Patents

Spliced screen and manufacturing method Download PDF

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Publication number
CN112864032A
CN112864032A CN202110157113.2A CN202110157113A CN112864032A CN 112864032 A CN112864032 A CN 112864032A CN 202110157113 A CN202110157113 A CN 202110157113A CN 112864032 A CN112864032 A CN 112864032A
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electrode
layer
hole
manufacturing
thin film
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温质康
乔小平
苏智昱
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Fujian Huajiacai Co Ltd
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Fujian Huajiacai Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/18—Tiled displays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32137—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract

The invention discloses a spliced screen and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: manufacturing a thin film transistor and a first electrode on one surface of a substrate; manufacturing a flat layer; manufacturing a first hole and a second hole on the flat layer; manufacturing a second electrode and a third electrode; manufacturing a pixel definition layer, and manufacturing a third hole on the pixel definition layer; manufacturing a light-emitting layer in the third hole, wherein the light-emitting layer is connected with the second electrode, and thus a display sub-screen is obtained; splicing the connecting side walls of the two display sub-screens together, and coating conductive silver paste at a fourth hole, wherein the conductive silver paste is connected with third electrodes on the two display sub-screens; and manufacturing a driving chip on the other surface of the substrate, wherein the driving chip is connected with the conductive silver paste between the two connecting side walls. According to the technical scheme, seamless splicing of the two screens is realized through the conductive silver paste, a plurality of dark areas of splicing seams on the spliced screen are avoided, and the display quality of the spliced screen is improved.

Description

Spliced screen and manufacturing method
Technical Field
The invention relates to the technical field of display screens, in particular to a spliced screen and a manufacturing method thereof.
Background
The spliced screen is formed by combining a plurality of display sub-screens into a whole according to a certain number and layout so as to meet the requirement of large-size display. Common spliced screens include liquid crystal spliced screens, plasma spliced screens, transparent screens and the like.
In the splicing screens of the LCD display panel, the OLED display panel and the LED display panel, in order to ensure the coordination of the display images of the two splicing screens, the display driving parts of the display sub-screens need to be connected, so as to realize the automatic distribution of the screen brightness and the images. Generally, a welding lead is arranged below a display area and used for being connected with an external driving chip, the area where the welding lead is located cannot be used for displaying, the display effect of the spliced screen is deteriorated due to the welding wire, the splicing seam of the display sub-screen is obvious, and the display impression of the spliced screen is also influenced.
Disclosure of Invention
Therefore, a spliced screen and a manufacturing method thereof are needed to be provided, and the problems that the display effect of the spliced screen is poor and the splicing seam of the spliced screen is obvious are solved.
In order to achieve the above object, this embodiment provides a method for manufacturing a tiled screen, including the following steps:
manufacturing a thin film transistor and a first electrode on one surface of a substrate, wherein the first electrode is positioned on one side of the thin film transistor;
manufacturing a flat layer, wherein the flat layer is positioned on the thin film transistor and the first electrode;
manufacturing a first hole and a second hole on the flat layer, wherein the bottom of the first hole is a source electrode or a drain electrode of the thin film transistor, and the bottom of the second hole is a first electrode;
manufacturing a second electrode and a third electrode, wherein the second electrode is connected with the source electrode or the drain electrode of the thin film transistor through the first hole, and the third electrode is connected with the first electrode through the second hole;
manufacturing a pixel definition layer, and manufacturing a third hole on the pixel definition layer, wherein the bottom of the third hole is a second electrode;
manufacturing a light-emitting layer in the third hole, wherein the light-emitting layer is connected with the second electrode, and thus a display sub-screen is obtained;
manufacturing a fourth hole on the pixel defining layer, wherein the bottom of the fourth hole is provided with a second electrode, connecting side walls of the two display sub-screens are spliced together through conductive silver paste, the conductive silver paste is connected with third electrodes on the two display sub-screens through the fourth hole, the conductive silver paste is also positioned between the connecting side walls of the two display sub-screens, and the third electrode in each display sub-screen is positioned between the light emitting layer and the connecting side wall;
and manufacturing a driving chip on the other surface of the substrate, wherein the driving chip is connected with the conductive silver paste.
Further, the specific steps of fabricating the light emitting layer in the third hole are:
and connecting a lamp bead pin of a luminescent layer of the Mini LED with the second electrode by adopting solder paste.
Further, the method also comprises the following steps:
and manufacturing an organic packaging layer on the pixel definition layers of the two display sub-screens, wherein the organic packaging layer covers the pixel definition layers and the conductive silver paste in the fourth hole.
Further, after the thin film transistor and the first electrode are formed on one surface of the substrate, before the planarization layer is formed, the method further includes the following steps:
and manufacturing a light shielding layer, wherein the light shielding layer is positioned between the thin film transistor and the flat layer and is used for blocking light rays from irradiating an active layer in the thin film transistor.
Furthermore, the thin film transistor is of a bottom gate structure, and the first electrode and the source electrode are arranged on the same layer.
The embodiment also provides a spliced screen, which comprises conductive silver paste, a driving chip and a display sub-screen;
the display sub-screen comprises a thin film transistor, a first electrode, a flat layer, a second electrode, a third electrode, a pixel definition layer and a light-emitting layer;
the thin film transistor and the first electrode are both arranged on one surface of the substrate, and the first electrode is positioned on one side of the thin film transistor;
the planarization layer is disposed on the thin film transistor and the first electrode;
the second electrode and the third electrode are both arranged on the flat layer, the second electrode is connected with a source electrode or a drain electrode of the thin film transistor through a first hole in the flat layer, and the third electrode is connected with the first electrode through a second hole in the flat layer;
the pixel defining layer is disposed on the planarization layer, the second electrode, and the third electrode;
the light emitting layer is disposed in the third hole of the pixel defining layer, and the light emitting layer is connected to the second electrode;
the connecting side walls of the two display sub-screens are spliced together through the conductive silver paste, and the conductive silver paste is also connected with the third electrode in each display sub-screen through a fourth hole in the pixel defining layer, wherein the third electrode in each display sub-screen is positioned between the light emitting layer and the connecting side wall;
the driving chip is arranged on the other surface of the substrate and connected with the conductive silver paste.
Furthermore, the luminescent layer is a luminescent layer of a Mini LED, and a lamp bead pin of the luminescent layer of the Mini LED is connected with the second electrode through solder paste.
Furthermore, the spliced screen further comprises an organic packaging layer, and the organic packaging layer covers the pixel definition layer in each display sub-screen and also covers the conductive silver paste in the fourth hole.
Furthermore, the display sub-screen further comprises a light shielding layer, wherein the light shielding layer is located between the thin film transistor and the flat layer and used for blocking light rays from irradiating an active layer in the thin film transistor.
Furthermore, the thin film transistor is of a bottom gate structure, and the first electrode and the source electrode are arranged on the same layer.
Different from the prior art, the seamless splicing of the two screens is realized through the conductive silver paste in the technical scheme, and the conductive silver paste has excellent printing property, water resistance, hardness, adhesive force, flexibility, weather resistance and conductive performance, so that the splicing seam on the spliced screen is thin, and a sharp feeling is not easy to bring to people. Meanwhile, the technical scheme also avoids a plurality of dark areas of the splicing seams on the spliced screen, improves the display quality of the spliced screen and improves the competitiveness of products.
Drawings
FIG. 1 is a schematic cross-sectional view illustrating a gate electrode, a gate insulating layer, an active layer and an etching stop layer formed on a substrate according to the present embodiment;
FIG. 2 is a schematic cross-sectional view illustrating a source, a drain, a first electrode, a buffer layer and a light-shielding layer formed on a substrate according to the present embodiment;
FIG. 3 is a schematic cross-sectional view illustrating a second electrode and a third electrode formed on a substrate according to the present embodiment;
FIG. 4 is a schematic cross-sectional view illustrating a pixel defining layer and a light emitting layer formed on a substrate according to the present embodiment;
fig. 5 is a schematic cross-sectional view illustrating the two display sub-panels spliced together by conductive silver paste according to the present embodiment.
Description of reference numerals:
1. a substrate;
2. a thin film transistor;
21. a gate electrode; 22. a gate insulating layer; 23. an active layer; 24. etching the barrier layer; 25. a source electrode; 26. a drain electrode;
3. a first electrode;
4. a buffer layer;
5. a light-shielding layer;
6. a planarization layer;
7. a second electrode;
8. a third electrode;
9. a pixel defining layer;
10. a light emitting layer;
101. a lamp bead pin;
11. conductive silver paste;
12. an organic encapsulation layer;
13. a driving chip;
14. connecting the side walls.
Detailed Description
To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
Referring to fig. 1 to 5, the present embodiment provides a method for manufacturing a tiled display, which can be performed on a glass substrate 1 or a plastic substrate 1, where the substrate 1 is used to support each film layer. The manufacturing method of the spliced screen comprises the following steps: a thin film transistor 2 and a first electrode 3 are formed on one surface of a substrate 1. The first electrode 3 is located at one side of the thin film transistor 2. The display panel driven by the thin film transistor 2 as a switch can achieve the characteristics of high speed, high brightness and high contrast. The thin film transistor 2 may be a top gate structure or a bottom gate structure, and the thin film transistor 2 having a bottom gate structure is exemplified herein.
First, a gate electrode 21 is formed on a substrate, and the structure is shown in fig. 1. Specifically, a photoresist is coated on a substrate, then the photoresist is exposed and developed so that a portion where the gate electrode 21 is to be fabricated is opened, and then a gate metal is plated on the substrate, thereby forming the gate electrode 21 on the substrate. It should be noted that the gate metal may be deposited by physical vapor deposition. After the gate 21 is fabricated, the photoresist is removed.
The gate metal may be one or a combination of more of aluminum, molybdenum, copper, and gold, but is not limited thereto. For example, the gate metal is a combination of aluminum (Al)/molybdenum (Mo), and the thickness of the aluminum film layer in the combination of Al/Mo is 0.3um (micrometer) to 0.4um (micrometer). Preferably, the thickness of the aluminum film in the Al/Mo combination is 0.33 um. The thickness of the molybdenum film layer in the Al/Mo combination is 0.02 (micrometer) to 0.08 (micrometer). Preferably, the thickness of the molybdenum film layer in the Al/Mo combination is 0.06 um.
After the gate is manufactured, in order to isolate the gate from the active layer, a gate insulating layer 22 is formed on the gate, and the structure is shown in fig. 1. Specifically, the gate electrode 21 may be coated with an insulating material by plasma enhanced chemical vapor deposition, and then etched to obtain a suitable gate insulating layer 22. Among them, the insulating material is, but not limited to, nitride (silicon nitride, etc.), oxide (silicon oxide, etc.), and the like. In order to achieve effective isolation, the gate insulating layer 22 covers the gate and may cover the entire surface of the substrate.
The thickness of the gate insulating layer is 0.2um to 0.4 um. Preferably, the thickness of the gate insulating layer is 0.3 um.
After the gate insulating layer is formed, an active layer 23 is formed on the gate insulating layer, and the structure is shown in fig. 1. An active layer material is deposited on the gate insulating layer by sputtering, and the active layer material attached to the gate insulating layer forms an active layer 23 after exposure, development, etching, and stripping. The active layer material may be an oxide semiconductor, such as Indium Gallium Zinc Oxide (IGZO), Indium Zinc Tin Oxide (IZTO), Indium Gallium Zinc Titanium Oxide (IGZTO), etc., but is not limited thereto.
The thickness of the active layer is 0.03um to 0.06 um. Preferably, the thickness of the active layer is 0.04 um.
After the active layer is manufactured, an etching stop layer 24 is manufactured on the active layer, and the etching stop layer 24 can protect the active layer from being corroded by etching liquid and stripping liquid, and the structure is shown in fig. 1. Specifically, the gate electrode may be coated with an insulating material by plasma enhanced chemical vapor deposition and then etched to provide a suitable etch stop layer 24. Among them, the insulating material is, but not limited to, nitride (silicon nitride, etc.), oxide (silicon oxide, etc.), and the like. In order to effectively protect, the etch stopper layer 24 covers not only the active layer 23 but also the gate insulating layer 22. In some embodiments, the etch stop layer may not need to be fabricated.
The thickness of the etching stopper layer is 0.15um to 0.3 um. Preferably, the etch stop layer has a thickness of 0.02 um.
After the etching stop layer is formed, the source electrode 25, the drain electrode 26 and the first electrode 3 are formed on the etching stop layer, and the structure is as shown in fig. 2. The source and drain metals may be plated by sputtering, and the source and drain metals may be exposed, developed, etched, and stripped to form the source 25, the drain 26, and the first electrode 3. The source electrode 25 and the drain electrode 26 are connected to the active layer 23 through holes in the etch stopper layer, and the source electrode 25 and the drain electrode 26 are in ohmic contact with the underlying active layer 23. The source electrode 25, the drain electrode 26, the active layer 23 and the gate electrode are formed as a part of one thin film transistor 2, and the first electrode 3 is formed as another part, and the first electrode 3 may be formed simultaneously with the source electrode 25 or a metal film such as the gate electrode.
The source-drain metal may be one or a combination of more than one of aluminum, molybdenum, copper, gold, and titanium, but is not limited thereto. For example, the source-drain metal is a combination of aluminum (Al)/molybdenum (Mo), and the thickness of the aluminum film layer in the combination of Al/Mo is 0.3um (micrometer) to 0.4um (micrometer). Preferably, the thickness of the aluminum film in the Al/Mo combination is 0.33 um. The thickness of the molybdenum film layer in the Al/Mo combination is 0.02 (micrometer) to 0.08 (micrometer). Preferably, the thickness of the molybdenum film layer in the Al/Mo combination is 0.06 um.
Before the source and drain electrodes are formed, holes are formed in the etching stopper layer, and the holes serve as connection points between the active layer and the source electrode and between the active layer and the drain electrode.
In order to protect the thin film transistor from being damaged by an external circuit, a buffer layer 4 is formed on the thin film transistor, and the structure is as shown in fig. 2. Specifically, the thin film transistor 2 may be coated with an insulating material by plasma enhanced chemical vapor deposition, and then etched to obtain the appropriate buffer layer 4. Among them, the insulating material is, but not limited to, nitride (silicon nitride, etc.), oxide (silicon oxide, etc.), and the like. The buffer layer 4 covers the thin film transistor 2 and the first electrode 3, and when an external structure is blocked by the buffer layer 4, the thin film transistor 2 and the first electrode 3 under the buffer layer are not contacted.
The active layer in the thin film transistor is susceptible to the influence of light, and further affects the stability of the thin film transistor, and in order to avoid the active layer being irradiated by light, a light shielding layer 5 is formed on the buffer layer, and the structure is as shown in fig. 2. The light shielding layer 5 may be made of a light-impermeable material such as metal, black resin, light shielding tape, or the like. Among them, the metal may be molybdenum, copper, aluminum, etc. When light is irradiated on the active layer, the light is shielded by the light shielding layer 5, and the active layer is not irradiated by the light, thereby ensuring the performance of the thin film transistor.
The thickness of the light-shielding layer is 0.1um to 0.2 um. Preferably, the light-shielding layer has a thickness of 0.15um.
The light-shielding layer may be provided between the thin film transistor and the flat layer, or may be provided on the flat layer.
An uneven plane is formed on the substrate due to a plurality of processes, and in order to make the substrate flat and facilitate the subsequent film layer fabrication, a flat layer 6 is fabricated on the buffer layer, and the structure is shown in fig. 3. In particular, the buffer layer may be coated with an insulating material by plasma enhanced chemical vapor deposition and then etched to provide a suitable planar layer 6. Among them, the insulating material is, but not limited to, nitride (silicon nitride or the like), oxide (silicon oxide or the like), polyimide, or the like. The flat layer 6 is located on the thin film transistor and the first electrode 3, the flat layer 6 has a certain thickness, and the upper surface of the flat layer 6 is a plane and is parallel to one surface of the substrate.
And manufacturing a first hole and a second hole on the flat layer 6, wherein the bottom of the first hole is a source electrode 25 or a drain electrode 26 of the thin film transistor, and the first hole is used as a connection point of the light-emitting layer 10 and the thin film transistor. The bottom of the second hole is the first electrode, and the second hole serves as the connection point of the first electrode and the third electrode 8.
After the formation of the planarization layer, a second electrode 7 and a third electrode 8 are formed on the planarization layer, and the structure is shown in fig. 3. The electrode layer metal can be plated by sputtering and evaporation, and the second electrode 7 and the third electrode 8 are formed after the electrode layer metal is exposed, developed, etched and stripped. The electrode layer metal may be a metal or a metal oxide, and for example, the metal oxide may be Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), or the like. The second electrode 7 is connected to the source electrode 25 or the drain electrode 26 of the thin film transistor through the first hole, and the second electrode 7 serves as an anode of the display panel. The third electrode 8 is connected with the first electrode 3 through the second hole, and the third electrode 8 and the first electrode 3 are conducted to form a switched capacitor which is used for controlling the on and off of the display luminescent layer.
It should be noted that a metal gate is further disposed below the first electrode, the metal gate is connected to the first electrode 3, and the metal gate and the gate of the thin film transistor can be disposed in the same layer.
The thickness of the electrode layer metal is 0.06um to 0.08 um. Preferably, the thickness of the electrode layer metal is 0.075 um.
After the second electrode is formed, the pixel defining layer 9 is formed, and the structure is shown in fig. 4. The pixel definition layer 9 is to define each individual sub-pixel unit of the display panel. The pixel defining layer 9 covers the second electrode 7, the third electrode 8 and the planarization layer 6. And a third hole is made in the pixel defining layer 9, the bottom of the third hole being the second electrode 7. The third hole serves as a connection point between the second electrode 7 and the light-emitting layer 10.
A light emitting layer 10 is fabricated in the third hole. The luminescent layer 10 is connected with the second electrode 7, so that a display sub-screen is obtained. One of the light emitting layers 10 may form sub-pixels of R (RED), G (GREEN), B (BLUE), or W (WHITE) to realize a display function of the panel.
The light Emitting layer 10 may be a light Emitting layer of an OLED (organic light-Emitting Diode) or a light Emitting layer of a Mini LED. The light Emitting layer of the OLED makes the display panel an OLED display panel, which is also called an organic light-Emitting display (OLED) or an organic light-Emitting semiconductor. The luminescent layer of the Mini LED makes the display panel a Mini LED display panel. The Mini LED display panel has the advantages of high response speed, high-temperature reliability and long service life while maintaining excellent display effect and flexibility. Here, taking the manufacturing of the light emitting layer of the Mini LED as an example, the bead pin 101 of the light emitting layer of the Mini LED is connected to the second electrode 7 by using solder paste, and the structure is shown in fig. 4. At this time, the substrate (i.e. the display sub-screen) of the light emitting layer of the bound Mini LED is a normally displayed screen. So that the thin film transistor controls the light emitting condition of the light emitting layer through the second electrode.
The display sub-panel obtained through the above steps includes a thin film transistor, a first electrode, a planarization layer, a second electrode, a third electrode, a pixel defining layer, and a light emitting layer. The third electrode in each display sub-screen is located between the light-emitting layer and the connecting sidewall 14, i.e. the third electrode and the first electrode are close to the connecting sidewall.
And manufacturing a fourth hole on the pixel definition layer, wherein the fourth hole is positioned above the third electrode, the fourth hole is a through hole on the pixel definition layer, the bottom of the fourth hole is the third electrode on the display sub-screen, and a part of flat layer is arranged at the bottom of the fourth hole. The fourth hole can be made before the two display sub-screens are spliced together, or a large fourth hole can be made after the two display sub-screens are aligned.
Taking the example of simultaneously manufacturing a large fourth hole after aligning the two display sub-screens, the connecting side walls 14 of the two display sub-screens are spliced together, and the connecting side walls 14 of the two display sub-screens are opposite to each other, and the structure is shown in fig. 5. In fig. 5, the connecting sidewall of the display sub-screen on the left is the right sidewall of the display sub-screen, and the connecting sidewall of the display sub-screen on the right is the left sidewall of the display sub-screen. And then, simultaneously forming holes on the two display sub-screens to form a fourth hole, wherein the left part of the fourth hole is positioned on the display sub-screen on the left side, and the right part of the fourth hole is positioned on the display sub-screen on the right side. If the fourth hole is manufactured before the two display sub-screens are spliced, the holes are punched on the pixel definition layers of the display sub-screens in sequence to form the fourth hole, and the fourth holes on the two display sub-screens are preferably communicated, so that the conductive silver paste is conveniently filled. Of course, the fourth holes of the two display sub-screens may not be connected together.
Coating conductive silver paste 11 at a fourth hole, wherein the conductive silver paste 11 is connected with the third electrodes 8 on the two display sub-screens, and the conductive silver paste 11 is filled between the connecting side walls 14 of the two display sub-screens (namely, at the splicing seams on the splicing screens). After the conductive silver paste 11 is cured, a driving chip 13 is fabricated on the other surface of the substrate, and the driving chip 13 is connected to the conductive silver paste 11 between the two connecting side walls 14, and the structure is shown in fig. 5.
Above-mentioned technical scheme uses the concatenation seam to form the wire as the model, and the outside drive chip is bound to the wire, and electrically conductive silver thick liquid possesses excellent printability, water proofness, hardness, adhesive force, flexibility and weatherability, electric conductive property, still can not make the concatenation seam grow on the concatenation screen. The main components of the conductive silver paste are conductive silver powder and organic resin. The conductive silver powder has a conductive effect, the organic resin has the effects of packaging and bonding the fixed screens, the conductive silver paste is adopted for packaging and bonding the two screens, so that the gap between the two screens can be reduced, and the large gap caused by welding the screens by adopting welding wires for traditional splicing screens is avoided. Wherein the welding area does not have drive module, does not have display device yet, consequently can't give out light and present the dark space, and the concatenation seam does not have the dark space on the concatenation screen on this application, improves the display quality of concatenation screen.
The conductive silver paste is generally a paste suspension system prepared by mechanically stirring and dispersing conductive silver powder, an organic polymer, an organic solvent and other additives by a high-speed dispersing machine, and uniformly mixing and finely rolling the mixture by a three-roll grinder.
The organic encapsulation layer 12 is coated on the surface of the tiled screen, and the organic encapsulation layer 12 can cover the whole pixel definition layer, and the structure is shown in fig. 5. The thickness of the organic encapsulation layer 12 is 1um to 3um, and preferably, the thickness of the organic encapsulation layer 12 is 2 m. The organic packaging layer 12 fills all the openings of the pixel definition layer, effectively seals the lamp beads and the conductive silver paste of the luminescent layer of the Mini LED, and protects the lamp bead pins and the conductive silver paste of the luminescent layer of the Mini LED from being eroded by water vapor and oxygen.
According to the technical scheme, seamless splicing of the two screens is realized through the conductive silver paste, namely, the splicing seam on the spliced screen is thin, and a sharp feeling is not easy to bring to people. Meanwhile, the technical scheme also avoids a plurality of dark areas of the splicing seams on the spliced screen, improves the display quality of the spliced screen and improves the competitiveness of products.
Referring to fig. 5, the present embodiment further provides a tiled display including a conductive silver paste 11, a driving chip and a display sub-screen. The display sub-screen is used as an independent and complete display screen and has a normal display function. And the plurality of display sub-screens are spliced to form a spliced display panel. The display sub-screen comprises a thin film transistor 2, a first electrode 3, a flat layer 6, a second electrode 7, a third electrode 8, a pixel defining layer 9 and a light emitting layer 10.
The thin film transistor 2 and the first electrode 3 are both arranged on one surface of the substrate, and the first electrode 3 is positioned on one side of the thin film transistor 2. The display panel driven by the thin film transistor 2 as a switch can achieve the characteristics of high speed, high brightness and high contrast. The thin film transistor 2 may be a top gate structure or a bottom gate structure. The planarization layer 6 is disposed on the thin film transistor 2 and the first electrode 3, and the planarization layer 6 is made of an insulating material and can protect the thin film transistor 2 and the first electrode 3. The planarization layer 6 also has a thickness to planarize irregularities on the substrate. The second electrode 7 and the third electrode 8 are both disposed on the planarization layer 6. The second electrode 7 is connected to the source 25 or the drain 26 of the thin film transistor through a first hole in the planarization layer 6, and the second electrode 7 serves as an anode of the display panel. If the second electrode 7 needs to be connected with the source electrode 25, the second electrode 7 is connected with the source electrode 25; if the second electrode 7 needs to be connected to the drain electrode 26, the second electrode 7 may be connected to the drain electrode 26. The third electrode 8 is connected to the first electrode 3 via a second hole in the planarization layer 6. The pixel defining layer 9 is disposed on the planarization layer 6, the second electrode 7 and the third electrode 8, and the pixel defining layer 9 is each individual sub-pixel unit defining the display panel. The light emitting layer 10 is disposed in the third hole of the pixel defining layer 9, and the light emitting layer 10 is connected to the second electrode 7. The connecting side walls 14 of the two display sub-screens are spliced together through the conductive silver paste 11. The conductive silver paste 11 is further connected to the third electrode 8 in each display sub-panel through a fourth hole on the pixel defining layer 9, wherein the third electrode 8 in each display sub-panel is located between the light emitting layer 10 and the connecting sidewall 14. The driving chip 13 is arranged on the other surface of the substrate, and the driving chip 13 is connected with the conductive silver paste 11. The driving chip 13 is used for driving a thin film transistor, a light emitting layer, and the like on the display panel.
According to the technical scheme, the seamless splicing of the two screens is realized through the conductive silver paste, and the conductive silver paste has excellent printing property, water resistance, hardness, adhesive force, flexibility, weather resistance and conductivity, so that the splicing seam on the spliced screen is thin, and a sharp feeling is not easy to give people. Meanwhile, the technical scheme also avoids a plurality of dark areas of the splicing seams on the spliced screen, improves the display quality of the spliced screen and improves the competitiveness of products.
It should be noted that, when the two display sub-panels are spliced, the same film layer on the two display sub-panels is located on the same horizontal plane, for example, the substrate of the left display sub-panel is flush with the substrate of the right display sub-panel, and the gate insulating layer 22 of the left display sub-panel is flush with the gate insulating layer 22 of the right display sub-panel.
In this embodiment, the light Emitting layer may be a light Emitting layer of an OLED (organic light-Emitting Diode) or a light Emitting layer of a Mini LED. The light Emitting layer of the OLED makes the display panel an OLED display panel, which is also called an organic light-Emitting display (OLED) or an organic light-Emitting semiconductor. The luminescent layer of the Mini LED makes the display panel a Mini LED display panel. The Mini LED display panel has the advantages of high response speed, high-temperature reliability and long service life while maintaining excellent display effect and flexibility. Taking the manufacturing of the light emitting layer of the Mini LED as an example, the bead pin of the light emitting layer of the Mini LED is connected to the second electrode 7 by using solder paste, and at this time, the substrate (i.e., the display sub-screen) of the light emitting layer of the Mini LED which is well bound is a screen for normal display. So that the thin film transistor controls the light emitting condition of the light emitting layer through the second electrode.
In this embodiment, in order to protect the bead pins of the light emitting layer of the Mini LED and the conductive silver paste from being corroded by water vapor and oxygen, the display panel further includes an organic encapsulation layer 12. The organic packaging layer 12 covers not only the pixel defining layer 9 in each display sub-screen, but also the conductive silver paste in the fourth hole, so that the lamp beads and the conductive silver paste of the luminescent layer of the Mini LED are effectively sealed.
The thickness of the organic encapsulating layer is 1um to 3um, and preferably 2 m.
In this embodiment, the active layer in the thin film transistor is susceptible to the influence of light, and then influences the stability of the thin film transistor, in order to avoid the active layer being irradiated by light, the display sub-screen further includes a light shielding layer 5, the light shielding layer 5 is located between the thin film transistor and the flat layer 6, and the light shielding layer 5 is used for blocking the light from irradiating the active layer 23 in the thin film transistor. The light shielding layer 5 may be made of a light-impermeable material such as metal, black resin, light shielding tape, or the like. Among them, the metal may be molybdenum, copper, aluminum, etc. When light is irradiated on the active layer 23, the light is shielded by the light shielding layer 5, and the active layer 23 is not irradiated by the light, thereby ensuring the performance of the thin film transistor.
In this embodiment, the thin film transistor 2 has a bottom gate structure. The gate electrode 21 is provided on one surface of the substrate. A gate insulating layer 22 is disposed on the gate. An active layer 23 is disposed on the gate insulating layer 22, and the active layer 23 is positioned directly above the gate electrode. An etch stopper layer 24 is disposed on the gate insulating layer and the active layer 23. A source electrode 25 and a drain electrode 26 are disposed on the etch stopper layer 24. The source and drain electrodes 25 and 26 are connected to the active layer 23, respectively. The first electrode 3 and the source electrode 25 are disposed in the same layer to reduce the number of processes. In order to protect the tft, the source electrode 25, the drain electrode 26, and the etch stop layer 24 are covered by a buffer layer 4, and the buffer layer 4 may also cover the first electrode 3, when an external structure is blocked by the buffer layer 4, the tft and the first electrode 3 under the buffer layer 4 are not contacted.
The first electrode may be provided on another insulating layer.
It should be noted that, although the above embodiments have been described herein, the invention is not limited thereto. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by making changes and modifications to the embodiments described herein, or by using equivalent structures or equivalent processes performed in the content of the present specification and the attached drawings, which are included in the scope of the present invention.

Claims (10)

1. A manufacturing method of a spliced screen is characterized by comprising the following steps:
manufacturing a thin film transistor and a first electrode on one surface of a substrate, wherein the first electrode is positioned on one side of the thin film transistor;
manufacturing a flat layer, wherein the flat layer is positioned on the thin film transistor and the first electrode;
manufacturing a first hole and a second hole on the flat layer, wherein the bottom of the first hole is a source electrode or a drain electrode of the thin film transistor, and the bottom of the second hole is a first electrode;
manufacturing a second electrode and a third electrode, wherein the second electrode is connected with the source electrode or the drain electrode of the thin film transistor through the first hole, and the third electrode is connected with the first electrode through the second hole;
manufacturing a pixel definition layer, and manufacturing a third hole on the pixel definition layer, wherein the bottom of the third hole is a second electrode;
manufacturing a light-emitting layer in the third hole, wherein the light-emitting layer is connected with the second electrode, and thus a display sub-screen is obtained;
manufacturing a fourth hole on the pixel defining layer, wherein the bottom of the fourth hole is provided with a second electrode, connecting side walls of the two display sub-screens are spliced together through conductive silver paste, the conductive silver paste is connected with third electrodes on the two display sub-screens through the fourth hole, the conductive silver paste is also positioned between the connecting side walls of the two display sub-screens, and the third electrode in each display sub-screen is positioned between the light emitting layer and the connecting side wall;
and manufacturing a driving chip on the other surface of the substrate, wherein the driving chip is connected with the conductive silver paste.
2. The method for manufacturing the spliced screen as claimed in claim 1, wherein the step of manufacturing the luminescent layer in the third hole comprises the following steps:
and connecting a lamp bead pin of a luminescent layer of the Mini LED with the second electrode by adopting solder paste.
3. The method for manufacturing the spliced screen as claimed in claim 1 or 2, further comprising the steps of:
and manufacturing an organic packaging layer on the pixel definition layers of the two display sub-screens, wherein the organic packaging layer covers the pixel definition layers and the conductive silver paste in the fourth hole.
4. The method of claim 1, wherein after the thin film transistor and the first electrode are formed on one surface of the substrate, and before the planarization layer is formed, the method further comprises the steps of:
and manufacturing a light shielding layer, wherein the light shielding layer is positioned between the thin film transistor and the flat layer and is used for blocking light rays from irradiating an active layer in the thin film transistor.
5. The method for manufacturing the spliced screen as claimed in claim 1, wherein the thin film transistor is of a bottom gate structure, and the first electrode and the source electrode are arranged on the same layer.
6. A spliced screen is characterized by comprising conductive silver paste, a driving chip and a display sub-screen;
the display sub-screen comprises a thin film transistor, a first electrode, a flat layer, a second electrode, a third electrode, a pixel definition layer and a light-emitting layer;
the thin film transistor and the first electrode are both arranged on one surface of the substrate, and the first electrode is positioned on one side of the thin film transistor;
the planarization layer is disposed on the thin film transistor and the first electrode;
the second electrode and the third electrode are both arranged on the flat layer, the second electrode is connected with a source electrode or a drain electrode of the thin film transistor through a first hole in the flat layer, and the third electrode is connected with the first electrode through a second hole in the flat layer;
the pixel defining layer is disposed on the planarization layer, the second electrode, and the third electrode;
the light emitting layer is disposed in the third hole of the pixel defining layer, and the light emitting layer is connected to the second electrode;
the connecting side walls of the two display sub-screens are spliced together through the conductive silver paste, and the conductive silver paste is also connected with the third electrode in each display sub-screen through a fourth hole in the pixel defining layer, wherein the third electrode in each display sub-screen is positioned between the light emitting layer and the connecting side wall;
the driving chip is arranged on the other surface of the substrate and connected with the conductive silver paste.
7. The spliced screen of claim 6, wherein the luminescent layer is a luminescent layer of a Mini LED, and a lamp bead pin of the luminescent layer of the Mini LED is connected with the second electrode through solder paste.
8. The tiled screen of claim 6 or 7 further comprising an organic encapsulation layer covering not only the pixel definition layer in each display sub-screen but also the conductive silver paste in the fourth hole.
9. The tiled display screen of claim 6, wherein the display sub-screen further comprises a light shielding layer between the thin film transistor and the planarization layer, the light shielding layer being configured to block light from impinging on the active layer of the thin film transistor.
10. The spliced screen of claim 6, wherein the thin film transistor is a bottom gate structure, and the first electrode and the source electrode are disposed on the same layer.
CN202110157113.2A 2021-02-04 2021-02-04 Spliced screen and manufacturing method Withdrawn CN112864032A (en)

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Application Number Priority Date Filing Date Title
CN202110157113.2A CN112864032A (en) 2021-02-04 2021-02-04 Spliced screen and manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110157113.2A CN112864032A (en) 2021-02-04 2021-02-04 Spliced screen and manufacturing method

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Application publication date: 20210528