CN112834913B - High-voltage testing method for stacking tester channel - Google Patents
High-voltage testing method for stacking tester channel Download PDFInfo
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- CN112834913B CN112834913B CN202110025104.8A CN202110025104A CN112834913B CN 112834913 B CN112834913 B CN 112834913B CN 202110025104 A CN202110025104 A CN 202110025104A CN 112834913 B CN112834913 B CN 112834913B
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- 238000012360 testing method Methods 0.000 title claims abstract description 44
- 238000012545 processing Methods 0.000 claims abstract description 30
- 238000001514 detection method Methods 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 12
- 230000001629 suppression Effects 0.000 claims abstract description 11
- 238000002955 isolation Methods 0.000 claims description 37
- 238000012544 monitoring process Methods 0.000 claims description 6
- 238000011282 treatment Methods 0.000 claims description 6
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- 230000000694 effects Effects 0.000 description 2
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- 238000006243 chemical reaction Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
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Abstract
The invention relates to the technical field of semiconductor testing, in particular to a high-voltage testing method for a channel of a stacking tester. The specific method comprises the following steps: s1: starting power-on initialization; s2: starting a self-checking test, and judging whether the user is allocated in groups if the self-checking test passes; if not, sending a signal of no pass to a main control system; s3: judging whether the user groups the configuration, if so, carrying out channel stacking processing configuration and circuit noise suppression processing configuration; if not, directly entering the channel configuration; s4: entering a channel configuration; s5: performing channel self-checking, and if the self-checking is successful, finishing the self-checking by the whole machine; if the self-check is unsuccessful, sending an unsuccessful signal to a main control system; s6: the whole machine completes self-checking; s7: and (5) ending. Compared with the prior art, different voltage output and detection channels are isolated, so that different channels can be stacked for use, each channel can output 8-10V voltage, and the purpose of outputting high voltage is achieved through stacking of positive and negative terminals.
Description
Technical Field
The invention relates to the technical field of semiconductor testing, in particular to a high-voltage testing method for a channel of a stacking tester.
Background
In the field of chip testing, there is often a need to measure and provide high voltages, and in practical applications, the voltage range often needs to be covered to above 100V. The automatic tester not only needs to provide more than 100V as a power supply, but also needs to accurately measure the corresponding voltage. However, in general, most manufacturers cannot directly provide high voltage above 100V, and a common practice is to amplify a voltage output range by using a specially designed high voltage module, which has a disadvantage of poor accuracy in terms of output voltage, because the added primary operational amplifier circuit introduces a second level error, resulting in poor accuracy of output voltage. The accuracy also deteriorates in terms of measured voltage, because the number of measured ADC bits does not become large, but the voltage range is enlarged, and the accuracy of conversion is inevitably lowered. Meanwhile, due to the adoption of the specially designed high-voltage module, a user needs to purchase different equipment modules, waste of the existing low-voltage module of the user is also caused, and the testing cost is increased.
Disclosure of Invention
The invention provides a high-voltage testing method for a channel of a stacking tester, which is improved based on the existing circuit, and different voltage output and detection channels are isolated, so that the different channels can be stacked for use, each channel can output 8-10V voltage, and the purpose of outputting high voltage is achieved through stacking positive and negative terminals, and meanwhile, the cost is reduced and the output precision is improved.
In order to achieve the above object, a high-voltage testing method for stacking tester channels is designed, which comprises an automatic tester and is characterized in that: the specific method comprises the following steps:
s1: the automatic tester is powered on to initialize configuration;
S2: the main control system of the automatic testing machine starts a self-checking test, and if the self-checking test passes, whether the user grouping configuration is carried out or not is judged; if the self-checking test is not passed, sending a non-passing signal to a main control system, and carrying out error monitoring and error recording by the main control system;
S3: judging whether the user groups the configuration, if so, carrying out channel stacking processing configuration and circuit noise suppression processing configuration; if not, directly entering the channel configuration;
S4: after the channel stacking processing configuration and the suppression circuit noise processing configuration are completed, entering the channel configuration;
S5: after the channel configuration is completed, carrying out channel self-checking, and if the self-checking is successful, completing the self-checking by the whole machine; if the self-check is unsuccessful, an unsuccessful signal is sent to a main control system, and the main control system performs error monitoring and error recording;
S6: the whole machine completes self-checking;
S7: and (5) ending.
The channel stacking process flow is as follows:
S11: the main control system of the automatic testing machine sends the stacking signal to the PCB circuit, and each channel on the PCB circuit is connected by adopting Kelvin four wires;
S12: if high-voltage output is required, the channel adopts Kelvin four-wire connection to carry out high-voltage stacking treatment; if the detection processing is required, the channel adopts Kelvin four-wire connection to carry out test stacking processing;
s13: and connecting the stacked circuit with the common ground selection circuit, and controlling signals of the common ground selection circuit by the FPGA of the main control system so as to select a high-voltage output mode or a detection mode.
The noise treatment of the suppression circuit is completed by an isolation chip circuit, the isolation chip circuit comprises an isolation chip, a No. 1 port of the isolation chip is respectively connected with 3V voltage and one end of a first resistor, and the other end of the first resistor is connected with a No. 7 port of the isolation chip; the port 1 and the port 8 of the isolation chip are connected and grounded; the 3 to 6 ports of the isolation chip are connected with a main control circuit of the automatic testing machine; the 16 # port of the isolation chip is respectively connected with 3V voltage and one end of the second resistor, and the other end of the second resistor is connected with the 10 # port of the isolation chip; the port No. 9 and the port No. 15 of the isolation chip are connected and grounded; the 11 to 14 ports of the isolation chip are connected with a main control circuit of the automatic testing machine.
The stacking processing circuit comprises a high-voltage output stacking circuit and a detection processing stacking circuit, wherein the high-voltage output stacking circuit comprises a S3_Mf6 and S3_Ms6 passage, the S3_Mf6 and S3_Ms6 passages are combined and connected with one end of a resistor III, the other end of the resistor III is connected with one end of a resistor IV, a resistor V, a resistor VI, a resistor V, a resistor eight, a resistor nine, a resistor ten and a resistor eleven respectively through Kelvin four wires, the other end of the resistor IV is connected with one end of a signal relay I and one end of a resistor twelve respectively, and the other end of the resistor twelve is connected with 100V voltage; the other end of the resistor V is connected with one end of the signal relay I and one end of the resistor thirteen respectively, and the other end of the resistor thirteen is connected with 100V voltage; the other end of the resistor six is respectively connected with one end of the signal relay I and one end of the resistor fourteen, and the other end of the resistor fourteen is connected with 100V voltage; the other end of the resistor seven is respectively connected with one end of the signal relay I and one end of the resistor fifteen, and the other end of the resistor fifteen is connected with 100V voltage; the other end of the resistor eight is connected with one end of the second signal relay and one end of the resistor sixteen respectively, and the other end of the resistor sixteen is connected with 100V voltage; the other end of the resistor nine is respectively connected with the signal relay II and one end of the resistor seventeen, and the other end of the resistor seventeen is connected with 100V voltage; the other end of the resistor ten is respectively connected with the second signal relay and one end of the resistor eighteen, and the other end of the resistor eighteen is connected with 100V voltage; the other end of the resistor eleven is connected with one end of the signal relay II and one end of the resistor nineteenth respectively, and the other end of the resistor nineteenth is connected with 100V voltage; the detection processing stacking circuit comprises a S2_DS5 and S2_DF5 passage, wherein the S2_DS5 and S2_DF5 passages are combined and connected with one end of a resistor twenty, the other end of the resistor twenty is connected with one end of a resistor twenty-one, a resistor twenty-two, a resistor twenty-three, a resistor twenty-four wire, a resistor twenty-five, a resistor twenty-six, a resistor twenty-seven and one end of a resistor twenty-eight respectively, the other end of the resistor twenty-one is connected with a signal relay I, the other end of the resistor twenty-two is connected with the signal relay I, the other end of the resistor twenty-four is connected with the signal relay II, the other end of the resistor twenty-six is connected with the signal relay II, and the other end of the resistor twenty-eight is connected with the signal relay II.
The common ground selection circuit comprises a first signal relay and a second signal relay, wherein a first port of the first signal relay is respectively connected with 5V voltage and an anode of the first light emitting diode, a cathode of the first light emitting diode is connected with one end of a resistor twenty-ninth, the other end of the resistor twenty-ninth is respectively connected with an FPGA of a main control system and a second port of the first signal relay, a second port of the first signal relay is connected with one end of a resistor thirty, the other end of the resistor thirty is connected with a resistor six and a resistor fourteen or a resistor twenty-third, a third port of the first signal relay is grounded, a fourth port of the first signal relay is connected with one end of a resistor thirty-eleventh, the other end of the resistor thirty-eleventh is connected with a resistor seven and a resistor fifteen or a twenty-fourth, a5 port of the first signal relay is connected with one end of a resistor thirty-eighth, the other end of the resistor thirty-eighth or a resistor twenty-eighth, a 6 port of the first signal relay is grounded, a 7 port of the first signal relay is connected with one end of a resistor thirty-third and the resistor twelve or a resistor twenty-eighth are connected with the other end of the resistor; the port 1 of the signal relay II is respectively connected with 5V voltage and the anode of the light emitting diode II, the cathode of the light emitting diode II is connected with one end of a resistor thirty-four, the other end of the resistor thirty-four is respectively connected with the FPGA of the master control system and the port 8 of the signal relay II, the port 2 of the signal relay II is connected with one end of the resistor thirty-five, the other end of the resistor thirty-five is connected with the resistor eighty and the resistor eighteen or the resistor twenty-seven, the port 3 of the signal relay II is grounded, the port 4 of the signal relay II is connected with one end of the resistor thirty-six, the other end of the resistor thirty-six is connected with the resistor eleven and the resistor ninety or the resistor twenty-eight, the port 5 of the signal relay II is connected with one end of the resistor thirty-seven or the resistor twenty-six, the port 6 of the signal relay II is grounded, the port 7 of the signal relay II is connected with one end of the resistor thirty-eight, and the other end of the resistor eighty and the resistor sixteen or the twenty-fifteen.
The model of the isolation chip is ADUM, 34 and XXCRWZ.
The type of the signal relay I and the signal relay II is G6K-2P-5VDC.
Compared with the prior art, the invention provides a high-voltage testing method for stacking tester channels, which is improved based on the existing circuit, and different voltage output and detection channels are isolated, so that different channels can be stacked for use, each channel can output 8-10V voltage, and the purpose of outputting high voltage is achieved through stacking of positive and negative terminals, and meanwhile, the cost is reduced and the output precision is improved.
Drawings
Fig. 1 is a schematic diagram of the prior art.
Fig. 2 is a schematic diagram of the principle of the present invention.
FIG. 3 is a flow chart of the present invention.
Fig. 4 is a schematic diagram of an isolated chip circuit.
Fig. 5 is a schematic diagram of a stacking process circuit.
Fig. 6 is a schematic diagram of a common ground selection circuit.
Fig. 7 is an effect diagram of the conventional operational amplifier.
Fig. 8 is an effect diagram of the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
As shown in fig. 1, the prior art adopts a specially designed high-voltage module to amplify the voltage output range, and this approach has a disadvantage of poor accuracy in terms of output voltage, because the added one-stage operational amplifier circuit introduces a second-stage error, resulting in poor output voltage accuracy.
As shown in FIG. 2, which is a schematic diagram of the invention, different voltage output and detection channels are isolated, so that different channels can be stacked for use, each channel can output 8-10V voltage, and the purpose of outputting high voltage is achieved through stacking positive and negative terminals, and meanwhile, the cost is reduced and the output precision is improved.
As shown in fig. 3, a high-voltage testing method for stacking tester channels is as follows:
s1: the automatic tester is powered on to initialize configuration;
S2: the main control system of the automatic testing machine starts a self-checking test, and if the self-checking test passes, whether the user grouping configuration is carried out or not is judged; if the self-checking test is not passed, sending a non-passing signal to a main control system, and carrying out error monitoring and error recording by the main control system;
S3: judging whether the user groups the configuration, if so, carrying out channel stacking processing configuration and circuit noise suppression processing configuration; if not, directly entering the channel configuration;
S4: after the channel stacking processing configuration and the suppression circuit noise processing configuration are completed, entering the channel configuration;
S5: after the channel configuration is completed, carrying out channel self-checking, and if the self-checking is successful, completing the self-checking by the whole machine; if the self-check is unsuccessful, an unsuccessful signal is sent to a main control system, and the main control system performs error monitoring and error recording;
S6: the whole machine completes self-checking;
S7: and (5) ending.
The channel stacking process flow is as follows:
S11: the main control system of the automatic testing machine sends the stacking signal to the PCB circuit, and each channel on the PCB circuit is connected by adopting Kelvin four wires;
S12: if high-voltage output is required, the channel adopts Kelvin four-wire connection to carry out high-voltage stacking treatment; if the detection processing is required, the channel adopts Kelvin four-wire connection to carry out test stacking processing;
s13: and connecting the stacked circuit with the common ground selection circuit, and controlling signals of the common ground selection circuit by the FPGA of the main control system so as to select a high-voltage output mode or a detection mode.
As shown in fig. 4, the noise processing of the suppression circuit is completed by an isolation chip circuit, the isolation chip circuit comprises an isolation chip U18, the port No. 1 of the isolation chip U18 is respectively connected with a 3V voltage and one end of a resistor No. R158, and the other end of the resistor No. R158 is connected with the port No. 7 of the isolation chip U18; the port No. 1 and the port No. 8 of the isolation chip U18 are grounded; the 3 to 6 ports of the isolation chip U18 are connected with a main control circuit of the automatic testing machine; the No. 16 port of the isolation chip U18 is respectively connected with one end of a voltage of 3V and one end of a resistor II R157, and the other end of the resistor II R157 is connected with the No. 10 port of the isolation chip U18; the port No. 9 and the port No. 15 of the isolation chip U18 are grounded; the 11 to 14 ports of the isolation chip U18 are connected with a main control circuit of the automatic testing machine.
As shown in fig. 5, the stacking processing circuit includes a high-voltage output stacking circuit and a detection processing stacking circuit, the high-voltage output stacking circuit includes s3_mf6 and s3_ms6 paths, the s3_mf6 and s3_ms6 paths are combined and connected with one end of a resistor tri R18, the other end of the resistor tri R18 is connected with one end of a resistor tetra R10, a resistor pentar 11, a resistor hexar 12, a resistor heptar 13, a resistor octar 14, a resistor nonar 15, a resistor decar 16 and a resistor undecar 17 by kelvin four wires, the other end of the resistor tetra R10 is connected with one end of a signal relay RL13 and one end of a resistor twelve R2, and the other end of the resistor twelve R2 is connected with 100V voltage; the other end of the resistor five R11 is respectively connected with one end of a signal relay RL13 and one end of a resistor thirteen R3, and the other end of the resistor thirteen R3 is connected with 100V voltage; the other end of the resistor six R12 is respectively connected with one end of a signal relay RL13 and one end of a resistor fourteen R4, and the other end of the resistor fourteen R4 is connected with 100V voltage; the other end of the resistor seven R13 is respectively connected with one end of a signal relay RL13 and one end of a resistor fifteen R5, and the other end of the resistor fifteen R5 is connected with 100V voltage; the other end of the resistor eight R14 is respectively connected with one end of the signal relay two RL14 and one end of the resistor sixteen R6, and the other end of the resistor sixteen R6 is connected with 100V voltage; the other end of the resistor nine R15 is respectively connected with one end of the signal relay two RL14 and one end of the resistor seventeen R7, and the other end of the resistor seventeen R7 is connected with 100V voltage; the other end of the resistor ten R16 is respectively connected with one end of the signal relay two RL14 and one end of the resistor eighteen R8, and the other end of the resistor eighteen R8 is connected with 100V voltage; the other end of the resistor eleven R17 is respectively connected with one end of the signal relay II RL14 and one end of the resistor nineteen R9, and the other end of the resistor nineteen R9 is connected with 100V voltage; the detection processing stacking circuit comprises a S2_DS5 passage and a S2_DF5 passage, wherein the S2_DS5 passage and the S2_DF5 passage are combined and connected with one end of a resistor twenty R35, the other end of the resistor twenty R35 is respectively connected with one end of a resistor twenty-one R26, a resistor twenty-two R27, a resistor twenty-three R28, a resistor twenty-four R29, a resistor twenty-five R30, a resistor twenty-six R31, a resistor twenty-seven R32 and one end of a resistor twenty-eight R33 by adopting Kelvin four lines, the other end of the resistor twenty-one R26 is connected with a signal relay one RL13, the other end of the resistor twenty-two R27 is connected with a signal relay one RL13, the other end of the resistor twenty-three R28 is connected with a signal relay twenty-two RL14, the other end of the resistor twenty-three R31 is connected with a signal relay twenty-two RL14, the other end of the resistor twenty-three R32 is connected with a signal relay twenty-eight RL14, and the other end of the resistor twenty-three R33 is connected with a signal relay twenty-eight RL14.
As shown in fig. 6, the common ground selection circuit includes a signal relay one RL13 and a signal relay two RL14, the port No. 1 of the signal relay one RL13 is respectively connected with 5V voltage and the anode of the light emitting diode one D24, the cathode of the light emitting diode one D24 is connected with one end of a resistor twenty-nine R85, the other end of the resistor twenty-nine R85 is respectively connected with the FPGA of the master control system and the port No. 8 of the signal relay one RL13, the port No.2 of the signal relay one RL13 is connected with one end of a resistor thirty R91, the other end of the resistor thirty R91 is connected with a resistor six R12 and a resistor fourteen R4 or a resistor twenty-three R28, the port No. 3 of the signal relay one RL13 is connected with one end of a resistor thirty-one R90, the other end of the resistor thirty-one R90 is connected with a resistor seventy-one R13 or a resistor twenty-four R29, the port No. 5 of the signal relay one RL13 is connected with one end of a resistor thirty-two-twelve R89, the other end of the resistor thirty-two twelve R89 is connected with a resistor fifty-11 and a resistor thirty-three R3 or the signal relay one end of the resistor twenty-twelve R27, and the port No. 6 of the signal relay one RL13 is connected with a resistor twelve R10; the port 1 of the signal relay twenty-RL 14 is respectively connected with 5V voltage and the anode of the light-emitting diode twenty-D25, the cathode of the light-emitting diode twenty-D25 is connected with one end of a resistor thirty-four R92, the other end of the resistor thirty-four R92 is respectively connected with the FPGA of the master control system and the port 8 of the signal relay twenty-four R14, the port 2 of the signal relay twenty-four R14 is connected with one end of a resistor thirty-five R96, the other end of the resistor thirty-five R96 is connected with a resistor ten R16 and a resistor eighteen R8 or a resistor twenty-four R32, the port 3 of the signal relay twenty-four R14 is grounded, the port 4 of the signal relay twenty-four R14 is connected with one end of a resistor thirty-four R95, the other end of the resistor thirty-four R95 is connected with a resistor eleven R17 and a resistor nineteen R9 or a resistor twenty-four R33, the other end of the signal relay twenty-four R14 is connected with a resistor thirty-four R15 and a resistor seventeen R7 or a resistor twenty-four R31, the port 6 of the signal relay twenty-four R14 is grounded, and the port 7 of the signal relay twenty-four R14 is connected with one end of the resistor thirty-four R94 or the resistor thirty-eight R14.
The model number of the isolation chip U18 is ADUM, 34 and XXCRWZ.
The model of the signal relay one RL13 and the signal relay two RL14 is G6K-2P-5VDC.
As shown in fig. 7, by the conventional operational amplifier scheme, a special single channel operational amplifier circuit is designed to amplify to 40V, with the result that significant nonlinearity is exhibited at both ends of the curve.
As shown in fig. 8, by the stacking method of the present invention, the stacking 8V channels are sequentially increased to 40V, with the result that good linear characteristics are exhibited, only with some nonlinear point values at the segmentation points.
Based on the existing circuit, all channels are isolated, the circuit PCB is designed to be independent blocks, and noise suppression and other treatments are needed. In order to reduce the voltage drop caused by the PCB wiring, each channel is connected by Kelvin four wires.
The isolation chip of ADuM34XX series of AD company is used for isolating the control logic circuit and the analog channel circuit, and for suppressing digital circuit noise.
To provide the user with the channel common ground option and to suppress noise, a relay channel common ground selection control circuit is added for group selection of the channels common ground. The control of two signals of RLY11 and RLY12 of the common ground selection control circuit is performed through the FPGA, so that whether 8 channels of CH0/1/2/3/4/5/6/7 are common ground or not can be freely selected.
Sx_DRx is a channel, each channel can output 8-10V voltage, and the aim of outputting high voltage is fulfilled by stacking positive and negative terminals, and meanwhile, the cost is reduced and the output precision is improved.
Claims (6)
1. A high-voltage testing method for a stacking tester channel comprises an automatic tester and is characterized in that: the specific method comprises the following steps:
s1: the automatic tester is powered on to initialize configuration;
S2: the main control system of the automatic testing machine starts a self-checking test, and if the self-checking test passes, whether the user grouping configuration is carried out or not is judged; if the self-checking test is not passed, sending a non-passing signal to a main control system, and carrying out error monitoring and error recording by the main control system;
S3: judging whether the user groups the configuration, if so, carrying out channel stacking processing configuration and circuit noise suppression processing configuration; if not, directly entering the channel configuration;
S4: after the channel stacking processing configuration and the suppression circuit noise processing configuration are completed, entering the channel configuration;
S5: after the channel configuration is completed, carrying out channel self-checking, and if the self-checking is successful, completing the self-checking by the whole machine; if the self-check is unsuccessful, an unsuccessful signal is sent to a main control system, and the main control system performs error monitoring and error recording;
S6: the whole machine completes self-checking;
S7: ending;
The channel stacking processing configuration flow is as follows:
S11: the main control system of the automatic testing machine sends the stacking signal to the PCB circuit, and each channel on the PCB circuit is connected by adopting Kelvin four wires;
S12: if high-voltage output is required, the channel adopts Kelvin four-wire connection to carry out high-voltage stacking treatment; if the detection processing is required, the channel adopts Kelvin four-wire connection to carry out test stacking processing;
s13: and connecting the stacked circuit with the common ground selection circuit, and controlling signals of the common ground selection circuit by the FPGA of the main control system so as to select a high-voltage output mode or a detection mode.
2. A method of high pressure testing of a stack tester channel according to claim 1, wherein: the noise treatment of the suppression circuit is completed by an isolation chip circuit, the isolation chip circuit comprises an isolation chip (U18), a No. 1 port of the isolation chip (U18) is respectively connected with 3V voltage and one end of a resistor I (R158), and the other end of the resistor I (R158) is connected with a No. 7 port of the isolation chip (U18); the port No. 2 and the port No. 8 of the isolation chip (U18) are grounded; the 3 to 6 ports of the isolation chip (U18) are connected with a main control circuit of the automatic testing machine; the 16 # port of the isolation chip (U18) is respectively connected with 3V voltage and one end of a resistor II (R157), and the other end of the resistor II (R157) is connected with the 10 # port of the isolation chip (U18); the port No. 9 and the port No. 15 of the isolation chip (U18) are grounded; the 11 to 14 ports of the isolation chip (U18) are connected with a main control circuit of the automatic testing machine.
3. A method of high pressure testing of a stack tester channel according to claim 1, wherein: the stacking circuit comprises a high-voltage output stacking circuit and a detection processing stacking circuit, wherein the high-voltage output stacking circuit comprises a S3_MQ6 passage and a S3_MQ6 passage, the S3_MQ6 passage and the S3_MQ6 passage are combined and connected with one end of a resistor III (R18), the other end of the resistor III (R18) is respectively connected with one end of a resistor IV (R10), one end of a resistor V (R11), one end of a resistor VI (R12), one end of a resistor V (R13), one end of a resistor eight (R14), one end of a resistor nine (R15), one end of a resistor ten (R16) and one end of a resistor eleven (R17) by adopting Kelvin four wires, the other end of the resistor IV (R10) is respectively connected with one end of a signal relay I (RL 13) and one end of a resistor twelve (R2), and the other end of the resistor twelve (R2) is connected with 100V voltage; the other end of the resistor five (R11) is respectively connected with one end of a signal relay one (RL 13) and one end of a resistor thirteen (R3), and the other end of the resistor thirteen (R3) is connected with 100V voltage; the other end of the resistor six (R12) is respectively connected with one end of the signal relay one (RL 13) and one end of the resistor fourteen (R4), and the other end of the resistor fourteen (R4) is connected with 100V voltage; the other end of the resistor seven (R13) is respectively connected with one end of the signal relay one (RL 13) and one end of the resistor fifteen (R5), and the other end of the resistor fifteen (R5) is connected with 100V voltage; the other end of the resistor eight (R14) is respectively connected with one end of a signal relay II (RL 14) and one end of a resistor sixteen (R6), and the other end of the resistor sixteen (R6) is connected with 100V voltage; the other end of the resistor nine (R15) is respectively connected with one end of the signal relay II (RL 14) and one end of the resistor seventeen (R7), and the other end of the resistor seventeen (R7) is connected with 100V voltage; the other end of the resistor ten (R16) is respectively connected with one end of the signal relay II (RL 14) and one end of the resistor eighteen (R8), and the other end of the resistor eighteen (R8) is connected with 100V voltage; the other end of the resistor eleven (R17) is respectively connected with one end of the signal relay II (RL 14) and one end of the resistor nineteen (R9), and the other end of the resistor nineteen (R9) is connected with 100V voltage;
The detection processing stacking circuit comprises a S2_DS5 and S2_DF5 passage, wherein the S2_DS5 and S2_DF5 passage are combined and connected with one end of a resistor twenty (R35), the other end of the resistor twenty (R35) is respectively connected with a resistor twenty-one (R26), a resistor twenty-two (R27), a resistor twenty-three (R28), a resistor twenty-four (R29), a resistor twenty-five (R30), a resistor twenty-six (R31), a resistor twenty-seven (R32) and one end of a resistor twenty-eight (R33), the other end of the resistor twenty-one (R26) is connected with a signal relay one (RL 13), the other end of the resistor twenty-two (R27) is connected with a signal relay one (RL 13), the other end of the resistor twenty-four (R29) is connected with a signal relay one (RL 13), the other end of the resistor twenty-five (R30) is connected with a signal relay twenty-two (RL 14), the other end of the resistor twenty-five (R31) is connected with a signal relay twenty-six (RL 14), and the other end of the resistor twenty-eight (R32) is connected with a signal relay two-eight (RL 14).
4. A method of high pressure testing of a stack tester channel according to claim 1, wherein: the common ground selection circuit comprises a first signal relay (RL 13) and a second signal relay (RL 14), wherein the first port of the first signal relay (RL 13) is respectively connected with 5V voltage and the anode of a first light-emitting diode (D24), the cathode of the first light-emitting diode (D24) is connected with one end of a resistance twenty-nine (R85), the other end of the resistance twenty-nine (R85) is respectively connected with an FPGA of a master control system and the 8 port of the first signal relay (RL 13), the 2 port of the first signal relay (RL 13) is connected with one end of a resistance thirty (R91), the other end of the resistance thirty (R91) is connected with a resistance six (R12) and a resistance fourteen (R4) or a resistance twenty-three (R28), the 3 port of the first signal relay (RL 13) is grounded, the 4 port of the first signal relay (RL 13) is connected with one end of a resistance thirty-one (R90), the other end of the resistance thirty-one (R90) is connected with a resistance seventy (R13) and a resistance fifteen (R5) or a resistance twenty-four (R29), the other end of the signal relay (RL 13) is connected with one end of the resistance thirty-one (RL 9) and the resistance thirty-three (R27) is connected with the resistance of the second signal relay (RL 7), the other end of the resistor thirty-three (R88) is connected with a resistor four (R10), a resistor twelve (R2) or a resistor twenty-one (R26); the port 1 of the signal relay II (RL 14) is respectively connected with 5V voltage and the anode of the light emitting diode II (D25), the cathode of the light emitting diode II (D25) is connected with one end of a resistor thirty-four (R92), the other end of the resistor thirty-four (R92) is respectively connected with the FPGA of a main control system and the port 8 of the signal relay II (RL 14), the port 2 of the signal relay II (RL 14) is connected with one end of a resistor thirty-five (R96), the other end of the resistor thirty-five (R96) is connected with a resistor ten (R16) and a resistor eighteen (R8) or a resistor twenty-seven (R32), the port 3 of the signal relay II (RL 14) is grounded, the port 4 of the signal relay II (RL 14) is connected with one end of a resistor thirty-six (R95), the other end of the resistor thirty-six (R95) is connected with a resistor eleven (R17) and a resistor ninety-six (R9) or a resistor twenty-eight (R33), the port 5 of the signal relay II (RL 14) is connected with one end of a resistor thirty-seven (R93), the other end of the resistor thirty-seven (R93) is connected with a resistor thirty-seven (R31) and the port 7 of the signal relay II (RL 14) is connected with a resistor II (R14) and one end of the resistor II-sixteen (R14) is grounded, the other end of the resistor thirty-eight (R94) is connected with the resistor eight (R14) or the resistor sixteen (R6) or the resistor twenty-five (R30).
5. A method of high pressure testing of a stack tester channel according to claim 2, wherein: the model number of the isolation chip (U18) is ADUM and XXCRWZ.
6. A method of high pressure testing of stack tester channels according to claim 3 or 4, characterized in that: the model of the signal relay I (RL 13) and the signal relay II (RL 14) is G6K-2P-5VDC.
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