CN114942395B - Wafer multi-DIE electric leakage rapid test system and method - Google Patents
Wafer multi-DIE electric leakage rapid test system and method Download PDFInfo
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- CN114942395B CN114942395B CN202210874211.2A CN202210874211A CN114942395B CN 114942395 B CN114942395 B CN 114942395B CN 202210874211 A CN202210874211 A CN 202210874211A CN 114942395 B CN114942395 B CN 114942395B
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Abstract
The invention discloses a wafer multi-DIE electric leakage rapid test system and a method thereof, and the system comprises more than one current processing module, a test channel selection module and a voltage-current conversion module, wherein the current processing module is used for converting acquired required current into test voltage, amplifying the converted test voltage and inputting the amplified test voltage into the test channel selection module; the test path selection module is used for selecting corresponding test voltage according to the required current to be tested and inputting the selected test voltage into the voltage-current conversion module; the voltage-current conversion module is used for converting the input test voltage into current, and the current is the required current to be tested. The invention can realize multi-path parallel sampling test, has simple and stable circuit, improves the test efficiency, reduces the test time and reduces the test cost.
Description
Technical Field
The invention relates to a wafer multi-DIE electric leakage rapid test system and a method, and belongs to the field of wafer testing.
Background
A wafer refers to a silicon wafer used in the fabrication of semiconductor integrated circuits, and is called a wafer because its shape after dicing is circular, which is an upstream product of discrete devices. The wafer is tested in advance before being cut and packaged, bad products are removed, and waste of subsequent processes caused by the bad wafer can be reduced. Although the single value of the discrete device is low, the discrete device needs mass production, and the production cost can be reduced by improving the testing efficiency.
In the prior art, a single circuit is used for completing the test no matter the single-end test or the parallel test is performed, namely each test head corresponds to an independent test circuit, so that a plurality of same test circuits need to be configured, and the mechanism is complex, the cost is high and the efficiency is not high.
Disclosure of Invention
The purpose of the invention is as follows: aiming at the defect that the existing test circuit corresponds to a single test head, the invention provides the wafer multi-DIE electric leakage rapid test system and the method thereof, which can realize the circuit design of multi-path synchronous parallel test, make up the defect of the original test circuit and improve the test efficiency.
The technical scheme is as follows: in order to achieve the purpose, the invention adopts the technical scheme that:
a wafer multi-DIE electric leakage rapid test system comprises more than one current processing module, a test path selection module and a voltage-current conversion module, wherein:
the current processing module is used for converting the acquired required current into test voltage, amplifying the converted test voltage and inputting the amplified test voltage into the test access selection module.
The test path selection module is used for selecting corresponding test voltage according to the required current to be tested and inputting the selected test voltage into the voltage-current conversion module.
The voltage-current conversion module is used for converting the input test voltage into current, and the current is the required current to be tested.
Preferably: the current processing module comprises a current-voltage conversion circuit and a voltage amplification circuit, the current-voltage conversion circuit is used for converting the acquired required current into test voltage and inputting the converted test voltage into the voltage amplification circuit, and the voltage amplification circuit is used for amplifying the converted test voltage and inputting the amplified test voltage into the test access selection module.
Preferably: the current-voltage conversion circuit comprises a B _ IV _ IN joint, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteen resistor R18, a nineteen resistor R19, a twenty resistor R20, a first rheostat D1, a second rheostat D2, a first capacitor C1, a second resistor eight R28 and a Fein-class input bias current operational amplifier U1A, wherein:
one end of the first resistor R1 is connected with the B _ IV _ IN connector, and the other end of the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, the tenth resistor R10 and an OUT pin of the FeiAmp-level input bias current operational amplifier U1A are sequentially connected. One end of the resistor eleven R11 is connected with the B _ IV _ IN connector, and the other end of the resistor eleven R11, the resistor twelve R12, the resistor thirteen R13, the resistor fourteen R14, the resistor fifteen R15, the resistor sixteen R16, the resistor seventeen R17, the resistor eighteen R18, the resistor nineteen R19, the resistor twenty R20 and a-IN pin of the Fei-Amp level input bias current operational amplifier U1A are sequentially connected.
One end of the rheostat I D1 is connected with an OUT pin of the operational amplifier U1A of the flying safety level input bias current, and the other end of the rheostat I D1 is connected with a connecting wire of an-IN pin of the operational amplifier U1A of the flying safety level input bias current. The capacitor C1 is connected in parallel to two ends of the rheostat D1. And one end of the second rheostat D2 is connected with a-IN pin of the input bias current operational amplifier U1A of the flying safety class, and the other end of the second rheostat D2 is connected with the analog ground AG. One end of the resistor twenty-eight R28 is connected with the + IN pin of the flying safety level input bias current operational amplifier U1A, and the other end is connected with the analog ground AG. And a GRD pin of the flying safety level input bias current operational amplifier U1A is connected with a B _ IV _ GUARD connector.
Preferably, the following components: the voltage amplifying circuit comprises a resistor II R22, a resistor II R23, a capacitor II C2, a capacitor III C3, an operational amplifier II U2A, a resistor II five R25, a high-voltage latch-proof type 4-channel multiplexer S1A, a capacitor six C6, a capacitor seven C7, a capacitor eight C8, a capacitor nine C9, a resistor II six R26, a resistor II seven R27, a resistor II eight R28, a resistor II nine R29, a resistor III one R31, a resistor III two R32, a resistor III three R33, a resistor III four R34, a resistor III five R35, an operational amplifier III U3A, a capacitor five C5 and a rheostat III D3, wherein:
the OUT pin of the operational amplifier U1A of the input bias current of the flying safety class, the two resistors R22, the two resistors R23 and the non-inverting input end of the operational amplifier U2A are connected in sequence. One end of the capacitor II C2 is connected to a connecting line between the resistor II R22 and the resistor II R23, and the other end of the capacitor II C2 is connected to the analog ground AG. And one end of the capacitor III C3 is connected to a connecting line between the resistor II R23 and the positive phase input end of the operational amplifier II U2A, and the other end of the capacitor III C3 is connected with the analog ground AG. One end of the second resistor-five R25 is connected with the negative phase input end of the second operational amplifier U2A, and the other end of the second resistor-five R is connected with the analog ground AG. One end of the high-voltage latch-preventing type 4-channel multiplexer S1A is connected with the negative phase input end of the second operational amplifier U2A, the first open end of the high-voltage latch-preventing type 4-channel multiplexer S1A, the second resistor six R26 and the output end of the second operational amplifier U2A are sequentially connected, and the capacitor six C6 is connected at two ends of the second resistor six R26 in parallel. The second open end of the high-voltage anti-latch type 4-channel multiplexer S1A, the second seven R27 of the resistor and the output end of the second operational amplifier U2A are sequentially connected, and the seventh capacitor C7 is connected in parallel with the two ends of the second seven R27 of the resistor. The high-voltage anti-latch type 4-channel multiplexer S1A is characterized in that the open end III, the resistor twenty-eight R28 and the output end of the operational amplifier twenty-2A are sequentially connected, and the capacitor eigh C8 is connected to two ends of the resistor twenty-eight R28 in parallel. The four open ends of the high-voltage anti-latch type 4-channel multiplexer S1A, the two-nine resistor R29 and the output end of the operational amplifier U2A are sequentially connected, and the nine capacitor C9 is connected to the two ends of the two-nine resistor R29 in parallel.
The output end of the second operational amplifier U2A, the first resistor R31 and the negative phase input end of the third operational amplifier U3A are sequentially connected. One end of the resistor III-II R32 is connected with the negative phase input end of the operational amplifier III U3A, the other end of the resistor III-II R32 is connected with the output end of the operational amplifier III U3A, and the capacitor V C5 is connected to two ends of the resistor III-II R32 in parallel. One end of the resistor III-III R33 is connected with the non-inverting input end of the operational amplifier III U3A, and the other end of the resistor III-III R is connected with the analog ground AG.
The output end of the operational amplifier three U3A, the resistor three four R34, the resistor three five R35, the rheostat three D3 and the analog ground AG are sequentially connected, and a connecting line between the resistor three four R34 and the resistor three five R35 is connected with the non-inverting input end of the operational amplifier three U3A. And a connecting line between the resistor three-five R35 and the rheostat three-D3 is connected with the test path selection module.
Preferably: the voltage and current conversion module comprises a high-voltage anti-latching single-channel SPDT switch S2A, wherein a first pin of the high-voltage anti-latching single-channel SPDT switch S2A is connected with the test path selection module, a sixth pin of the high-voltage anti-latching single-channel SPDT switch S2A is connected with an SB _ EN connector, a eighth pin of the high-voltage anti-latching single-channel SPDT switch S2A is connected with an II _ OUT connector, and a second pin of the high-voltage anti-latching single-channel SPDT switch S2A is connected with an analog ground AG.
Preferably: the testing path selection module is an ADG1308BRUZ chip, a pin S1, a pin S2, a pin S3, a pin S4, a pin S5, a pin S6, a pin S7 and a pin S8 of the ADG1308BRUZ chip are used for being connected with a corresponding current processing module, a VDD pin of the ADG1308BRUZ chip is connected with a power supply voltage VCC, and a VSS pin and a GND pin of the ADG1308BRUZ chip are respectively connected with an analog ground AG. And the D pin of the ADG1308BRUZ chip is connected with a pin I of a high-voltage anti-latching single-channel SPDT switch S2A.
A wafer multi-DIE electric leakage rapid test method comprises the following steps:
And 2, converting the acquired required current into a test voltage by the current processing module, amplifying the converted test voltage and inputting the amplified test voltage into the test path selection module.
And 3, selecting a corresponding test voltage by the test path selection module according to the required current to be tested, and inputting the selected test voltage into the voltage-current conversion module.
And 4, converting the input test voltage into current by the voltage-current conversion module, wherein the current is the required current to be tested.
Preferably: and synchronously testing 10 wafers.
Compared with the prior art, the invention has the following beneficial effects:
1. the circuit design can realize multi-path parallel sampling test, and the circuit is simple and stable, thereby improving the test efficiency;
2. under the same test condition, the circuit can realize rapid test, and compared with the original test circuit, the test time is reduced, and the test cost is reduced;
3. the circuit design is completely matched with the existing test machine structure, can be quickly and conveniently transplanted to the existing test mechanism, and improves the practicability.
Drawings
FIG. 1 is a circuit diagram of an embodiment of the present invention.
Fig. 2 is a current-voltage conversion circuit diagram.
Fig. 3 is a voltage amplifying circuit diagram.
FIG. 4 is a block diagram of a test path selection block and a voltage-to-current conversion block.
Fig. 5 is a test flow chart.
Detailed Description
The present invention is further illustrated by the following description in conjunction with the accompanying drawings and the specific embodiments, it is to be understood that these examples are given solely for the purpose of illustration and are not intended as a definition of the limits of the invention, since various equivalent modifications will occur to those skilled in the art upon reading the present invention and fall within the limits of the appended claims.
A wafer multi-DIE electric leakage rapid test system comprises more than one current processing module, a test path selection module and a voltage-current conversion module, wherein:
the current processing module is used for converting the acquired required current into test voltage, amplifying the converted test voltage and inputting the amplified test voltage into the test access selection module.
The current processing module comprises a current-voltage conversion circuit and a voltage amplification circuit, the current-voltage conversion circuit is used for converting the acquired required current into test voltage and inputting the converted test voltage into the voltage amplification circuit, and the voltage amplification circuit is used for amplifying the converted test voltage and inputting the amplified test voltage into the test access selection module.
As shown IN fig. 2, the current-voltage conversion circuit includes a B _ IV _ IN connector, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteen resistor R18, a nineteen resistor R19, a twenty R20, a first varistor D1, a second varistor D2, a first capacitor C1, a second resistor R28, and a femtoan-level input bias current operational amplifier U1A, wherein:
one end of the first resistor R1 is connected with the B _ IV _ IN connector, and the other end of the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, the tenth resistor R10 and an OUT pin of the FeiAmp-level input bias current operational amplifier U1A are sequentially connected. One end of the resistor eleven R11 is connected with the B _ IV _ IN connector, and the other end of the resistor eleven R11, the resistor twelve R12, the resistor thirteen R13, the resistor fourteen R14, the resistor fifteen R15, the resistor sixteen R16, the resistor seventeen R17, the resistor eighteen R18, the resistor nineteen R19, the resistor twenty R20 and a-IN pin of the Fei-Amp level input bias current operational amplifier U1A are sequentially connected.
One end of the rheostat I D1 is connected with an OUT pin of the operational amplifier U1A of the flying safety level input bias current, and the other end of the rheostat I D1 is connected with a connecting wire of an-IN pin of the operational amplifier U1A of the flying safety level input bias current. U1A represents a flying amp class input bias current operational amplifier. The capacitor I C1 is connected in parallel to two ends of the rheostat I D1. And one end of the second rheostat D2 is connected with a-IN pin of the input bias current operational amplifier U1A of the flying safety class, and the other end of the second rheostat D2 is connected with the analog ground AG. One end of the resistor twenty-eight R28 is connected with the + IN pin of the flying safety level input bias current operational amplifier U1A, and the other end is connected with the analog ground AG. The GRD pin of the flying safety level input bias current operational amplifier U1A is connected with a B _ IV _ GUARD connector.
As shown in fig. 3, the voltage amplifying circuit includes a resistor two R22, a resistor two three R23, a capacitor two C2, a capacitor three C3, an operational amplifier two U2A, a resistor two five R25, a high-voltage latch-proof 4-channel multiplexer S1A, a capacitor six C6, a capacitor seven C7, a capacitor eight C8, a capacitor nine C9, a resistor two six R26, a resistor two seven R27, a resistor two eight R28, a resistor two nine R29, a resistor three one R31, a resistor three two R32, a resistor three R33, a resistor three four R34, a resistor three five R35, an operational amplifier three U3A, a capacitor five C5, and a varistor three D3, wherein:
the OUT pin of the operational amplifier U1A of the input bias current of the flying safety class, the two resistors R22, the two resistors R23 and the non-inverting input end of the operational amplifier U2A are connected in sequence. One end of the capacitor II C2 is connected to a connecting line between the resistor II R22 and the resistor II R23, and the other end of the capacitor II C2 is connected to the analog ground AG. And one end of the capacitor III C3 is connected to a connecting line between the resistor II R23 and the positive phase input end of the operational amplifier II U2A, and the other end of the capacitor III C3 is connected with the analog ground AG. One end of the second five R25 resistor is connected with the negative phase input end of the second operational amplifier U2A, and the other end of the second five R25 resistor is connected with the analog ground AG. One end of the high-voltage anti-latching type 4-channel multiplexer S1A is connected with the negative phase input end of the operational amplifier II U2A, the first open end of the high-voltage anti-latching type 4-channel multiplexer S1A, the second resistor six R26 and the output end of the operational amplifier II U2A are sequentially connected, and the capacitor six C6 is connected to two ends of the second resistor six R26 in parallel. The second open end of the high-voltage anti-latch type 4-channel multiplexer S1A, the second seven R27 of the resistor and the output end of the second operational amplifier U2A are sequentially connected, and the seventh C7 of the capacitor is connected in parallel with the two ends of the second seven R27 of the resistor. S1A denotes a high-voltage latch-proof 4-channel multiplexer. The high-voltage anti-latch type 4-channel multiplexer S1A is characterized in that the open end III, the resistor twenty-eight R28 and the output end of the operational amplifier II U2A are sequentially connected, and the capacitor eighty C8 is connected to two ends of the resistor twenty-eight R28 in parallel. The four open ends of the high-voltage anti-latch type 4-channel multiplexer S1A, the two-nine resistor R29 and the output end of the two operational amplifiers U2A are sequentially connected, and the nine capacitor C9 is connected to the two ends of the two-nine resistor R29 in parallel.
The output end of the second operational amplifier U2A, the first resistor R31 and the negative phase input end of the third operational amplifier U3A are sequentially connected. One end of the resistor III-II R32 is connected with the negative phase input end of the operational amplifier III-U3A, the other end of the resistor III-II R32 is connected with the output end of the operational amplifier III-U3A, and the capacitor five C5 is connected to two ends of the resistor III-II R32 in parallel. One end of the resistor III-III R33 is connected with the non-inverting input end of the operational amplifier III U3A, and the other end of the resistor III-III R is connected with the analog ground AG.
The output end of the operational amplifier three U3A, the resistor three four R34, the resistor three five R35, the rheostat three D3 and the analog ground AG are sequentially connected, and a connecting line between the resistor three four R34 and the resistor three five R35 is connected with the non-inverting input end of the operational amplifier three U3A. And a connecting line between the resistor three-five R35 and the rheostat three-D3 is connected with the test path selection module.
The test path selection module is used for selecting corresponding test voltage according to the required current to be tested and inputting the selected test voltage into the voltage-current conversion module.
As shown in fig. 4, the test path selection module is an ADG1308BRUZ chip, and the pins S1, S2, S3, and S4 of the ADG1308BRUZ chip are connected to corresponding current processing modules, and in another embodiment of the present invention, the pins S1, S2, S3, S4, S5, S6, S7, and S8 of the ADG1308BRUZ chip are used for connecting to corresponding current processing modules. The VDD pin of the ADG1308BRUZ chip is connected with a power supply voltage VCC, and the VSS pin and the GND pin of the ADG1308BRUZ chip are respectively connected with an analog ground AG. And the D pin of the ADG1308BRUZ chip is connected with a pin I of a high-voltage anti-latching single-channel SPDT switch S2A.
The voltage-current conversion module is used for converting the input test voltage into current, and the current is the required current to be tested.
As shown in fig. 4, the voltage-current conversion module includes a high-voltage latch-proof single-channel SPDT switch S2A, S2A represents a high-voltage latch-proof single-channel SPDT switch (single pole double throw), pin one of the high-voltage latch-proof single-channel SPDT switch S2A is connected to the test path selection module, pin six of the high-voltage latch-proof single-channel SPDT switch S2A is connected to an SB _ EN connector, pin eight of the high-voltage latch-proof single-channel SPDT switch S2A is connected to an ii _ OUT connector, and pin two of the high-voltage latch-proof single-channel SPDT switch S2A is connected to an analog ground AG.
A method for rapidly testing multiple DIE leakage on a wafer, as shown in fig. 5, includes the following steps:
And 2, converting the acquired required current into a test voltage by the current processing module, amplifying the converted test voltage and inputting the amplified test voltage into the test path selection module. The current-voltage conversion circuit converts the collected micro current into voltage. The voltage amplifying circuit amplifies the voltage obtained by converting the micro current, and the amplification factor can be selected according to the magnitude of the collected current so as to obtain the proper amplified voltage.
And 3, selecting a corresponding test voltage by the test path selection module according to the required current to be tested, and inputting the selected test voltage into the voltage-current conversion module.
And 4, converting the input test voltage into current by the voltage-current conversion module, wherein the current is the required current to be tested. The voltage and current conversion module converts the voltage and current into current which can be conveniently tested for testing.
The above description is only of the preferred embodiments of the present invention, and it should be noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the invention and these are intended to be within the scope of the invention.
Claims (5)
1. A wafer multi-DIE electric leakage rapid test system is characterized in that: including multichannel current processing module, test route selection module and voltage current conversion module, wherein:
the current processing module is used for converting the acquired required current into test voltage, amplifying the converted test voltage and inputting the amplified test voltage into the test access selection module;
the current processing module comprises a current-voltage conversion circuit and a voltage amplification circuit, the current-voltage conversion circuit is used for converting the acquired required current into a test voltage and inputting the converted test voltage into the voltage amplification circuit, and the voltage amplification circuit is used for amplifying the converted test voltage and inputting the amplified test voltage into the test access selection module;
the current-voltage conversion circuit comprises a B _ IV _ IN joint, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteen resistor R18, a nineteen resistor R19, a twenty resistor R20, a first rheostat D1, a second rheostat D2, a first capacitor C1, a second resistor eight R28 and a Fein-class input bias current operational amplifier U1A, wherein:
one end of the first resistor R1 is connected with the B _ IV _ IN joint, and the other end of the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, the tenth resistor R10 and an OUT pin of the FeiAN _ SNer input bias current operational amplifier U1A are sequentially connected; one end of the resistor eleven R11 is connected with the B _ IV _ IN connector, and the other end of the resistor eleven R11, the resistor twelve R12, the resistor thirteen R13, the resistor fourteen R14, the resistor fifteen R15, the resistor sixteen R16, the resistor seventeen R17, the resistor eighteen R18, the resistor nineteen R19, the resistor twenty R20 and a-IN pin of the Fei-Amp level input bias current operational amplifier U1A are sequentially connected;
one end of the rheostat I D1 is connected with an OUT pin of the flying safety level input bias current operational amplifier U1A, and the other end of the rheostat I D1 is connected with a connecting wire of an-IN pin of the flying safety level input bias current operational amplifier U1A; the capacitor I C1 is connected in parallel to two ends of the rheostat I D1; one end of the second rheostat D2 is connected with a-IN pin of the Fei' an input bias current operational amplifier U1A, and the other end of the second rheostat D2 is connected with an analog ground AG; one end of the resistor twenty-eight R28 is connected with a + IN pin of the flying safety level input bias current operational amplifier U1A, and the other end of the resistor twenty-eight R28 is connected with an analog ground AG; a GRD pin of a flying safety level input bias current operational amplifier U1A is connected with a B _ IV _ GUARD connector;
the voltage amplifying circuit comprises a resistor II R22, a resistor II R23, a capacitor II C2, a capacitor III C3, an operational amplifier II U2A, a resistor II five R25, a high-voltage anti-latch type 4-channel multiplexer S1A, a capacitor six C6, a capacitor seven C7, a capacitor eight C8, a capacitor nine C9, a resistor II six R26, a resistor II seven R27, a resistor II eight R28, a resistor II nine R29, a resistor III one R31, a resistor III two R32, a resistor III three R33, a resistor III four R34, a resistor III five R35, an operational amplifier III U3A, a capacitor five C5 and a rheostat III D3, wherein:
the OUT pin of the operational amplifier U1A of the flying safety level input bias current, the second resistor R22, the second resistor R23 and the positive phase input end of the operational amplifier U2A are sequentially connected; one end of the capacitor II C2 is connected to a connecting line between the resistor II R22 and the resistor II R23, and the other end of the capacitor II C2 is connected with an analog ground AG; one end of the capacitor III C3 is connected to a connecting line between the resistor II R23 and the positive phase input end of the operational amplifier II U2A, and the other end of the capacitor III C3 is connected with the analog ground AG; one end of the second resistor II-V R25 is connected with the negative phase input end of the second operational amplifier U2A, and the other end of the second resistor II-V R25 is connected with the analog ground AG; one end of the high-voltage anti-latching type 4-channel multiplexer S1A is connected with the negative phase input end of the operational amplifier II U2A, the first open end of the high-voltage anti-latching type 4-channel multiplexer S1A, the second resistor VI R26 and the output end of the operational amplifier II U2A are sequentially connected, and the capacitor VI C6 is connected in parallel with the two ends of the second resistor VI R26; the second open end of the high-voltage anti-latch type 4-channel multiplexer S1A, the second seven R27 resistor and the output end of the second operational amplifier U2A are sequentially connected, and the seventh capacitor C7 is connected in parallel with the two ends of the second seven R27 resistor; the high-voltage anti-latching type 4-channel multiplexer S1A is characterized in that the open end III, the resistor twenty-eight R28 and the output end of the operational amplifier U2A are sequentially connected, and the capacitor eighty C8 is connected in parallel at two ends of the resistor twenty-eight R28; the four open ends of the high-voltage anti-latching type 4-channel multiplexer S1A, the two-nine resistor R29 and the output end of the operational amplifier U2A are sequentially connected, and the nine capacitor C9 is connected to the two ends of the two-nine resistor R29 in parallel;
the output end of the second operational amplifier U2A, the first resistor R31 and the negative phase input end of the third operational amplifier U3A are sequentially connected; one end of the resistor III-II R32 is connected with the negative phase input end of the operational amplifier III-U3A, the other end of the resistor III-II R32 is connected with the output end of the operational amplifier III-U3A, and the capacitor five C5 is connected to two ends of the resistor III-II R32 in parallel; one end of the resistor III-III R33 is connected with the positive phase input end of the operational amplifier III U3A, and the other end of the resistor III-III R33 is connected with the analog ground AG;
the output end of the operational amplifier III U3A, the resistor III-IV R34, the resistor III-V R35, the rheostat III-D3 and the analog ground AG are sequentially connected, and a connecting line between the resistor III-IV R34 and the resistor III-V R35 is connected with the positive phase input end of the operational amplifier III U3A; the connecting line between the resistor thirty-five R35 and the rheostat three-D3 is connected with the test path selection module;
the test path selection module is used for selecting corresponding test voltage according to the required current to be tested and inputting the selected test voltage into the voltage-current conversion module;
the voltage-current conversion module is used for converting the input test voltage into current, and the current is the required current to be tested.
2. The wafer multi-DIE leakage fast test system of claim 1, wherein: the voltage and current conversion module comprises a high-voltage anti-latching single-channel SPDT switch S2A, wherein a first pin of the high-voltage anti-latching single-channel SPDT switch S2A is connected with the test path selection module, a sixth pin of the high-voltage anti-latching single-channel SPDT switch S2A is connected with an SB _ EN connector, a eighth pin of the high-voltage anti-latching single-channel SPDT switch S2A is connected with an II _ OUT connector, and a second pin of the high-voltage anti-latching single-channel SPDT switch S2A is connected with an analog ground AG.
3. The wafer multi-DIE leakage fast test system of claim 2, wherein: the test path selection module is an ADG1308BRUZ chip, a pin S1, a pin S2, a pin S3, a pin S4, a pin S5, a pin S6, a pin S7 and a pin S8 of the ADG1308BRUZ chip are used for being connected with corresponding current processing modules, a VDD pin of the ADG1308BRUZ chip is connected with a power supply voltage VCC, and a VSS pin and a GND pin of the ADG1308BRUZ chip are respectively connected with an analog ground AG; and the D pin of the ADG1308BRUZ chip is connected with a pin I of a high-voltage anti-latching single-channel SPDT switch S2A.
4. A fast test method applied to the wafer multi-DIE leakage fast test system of claim 1, characterized by comprising the following steps:
step 1, a test head collects current required by each wafer and inputs the current to a current processing module through a connecting wire;
step 2, the current processing module converts the acquired required current into a test voltage, amplifies the converted test voltage and inputs the amplified test voltage into the test path selection module;
step 3, the test path selection module selects a corresponding test voltage according to the required current to be tested, and inputs the selected test voltage into the voltage-current conversion module;
and 4, converting the input test voltage into current by the voltage-current conversion module, wherein the current is the required current to be tested.
5. The rapid test method according to claim 4, wherein: and synchronously testing 10 wafers.
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| KR100340588B1 (en) * | 1997-12-26 | 2002-09-18 | 재단법인 포항산업과학연구원 | Apparatus for deciding character of silicone-wafer using leakage current |
| US7075175B2 (en) * | 2004-04-22 | 2006-07-11 | Qualcomm Incorporated | Systems and methods for testing packaged dies |
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| CN207851137U (en) * | 2017-12-18 | 2018-09-11 | 蓝希万 | The faint Leakage Current Detector of semiconductor |
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| CN212379541U (en) * | 2020-03-26 | 2021-01-19 | 陕西三海测试技术开发有限责任公司 | MOSFET wafer leakage current parallel testing device |
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